LibDriver L3GD20H
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driver_l3gd20h.c
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1
37
38#include "driver_l3gd20h.h"
39
43#define CHIP_NAME "STMicroelectronic L3GD20H"
44#define MANUFACTURER_NAME "STMicroelectronic"
45#define SUPPLY_VOLTAGE_MIN 2.2f
46#define SUPPLY_VOLTAGE_MAX 3.6f
47#define MAX_CURRENT 5.0f
48#define TEMPERATURE_MIN -40.0f
49#define TEMPERATURE_MAX 85.0f
50#define DRIVER_VERSION 2000
51
55#define L3GD20H_REG_WHO_AM_I 0x0F
56#define L3GD20H_REG_CTRL1 0x20
57#define L3GD20H_REG_CTRL2 0x21
58#define L3GD20H_REG_CTRL3 0x22
59#define L3GD20H_REG_CTRL4 0x23
60#define L3GD20H_REG_CTRL5 0x24
61#define L3GD20H_REG_REFERENCE 0x25
62#define L3GD20H_REG_OUT_TEMP 0x26
63#define L3GD20H_REG_STATUS 0x27
64#define L3GD20H_REG_OUT_X_L 0x28
65#define L3GD20H_REG_OUT_X_H 0x29
66#define L3GD20H_REG_OUT_Y_L 0x2A
67#define L3GD20H_REG_OUT_Y_H 0x2B
68#define L3GD20H_REG_OUT_Z_L 0x2C
69#define L3GD20H_REG_OUT_Z_H 0x2D
70#define L3GD20H_REG_FIFO_CTRL 0x2E
71#define L3GD20H_REG_FIFO_SRC 0x2F
72#define L3GD20H_REG_IG_CFG 0x30
73#define L3GD20H_REG_IG_SRC 0x31
74#define L3GD20H_REG_IG_THS_XH 0x32
75#define L3GD20H_REG_IG_THS_XL 0x33
76#define L3GD20H_REG_IG_THS_YH 0x34
77#define L3GD20H_REG_IG_THS_YL 0x35
78#define L3GD20H_REG_IG_THS_ZH 0x36
79#define L3GD20H_REG_IG_THS_ZL 0x37
80#define L3GD20H_REG_IG_DURATION 0x38
81#define L3GD20H_REG_LOW_ODR 0x39
82
94static uint8_t a_l3gd20h_iic_spi_read(l3gd20h_handle_t *handle, uint8_t reg, uint8_t *buf, uint16_t len)
95{
96 if (handle->iic_spi == L3GD20H_INTERFACE_IIC) /* iic interface */
97 {
98 if (len > 1) /* len > 1 */
99 {
100 reg |= 1 << 7; /* flag bit 7 */
101 }
102
103 if (handle->iic_read(handle->iic_addr, reg, buf, len) != 0) /* read data */
104 {
105 return 1; /* return error */
106 }
107 else
108 {
109 return 0; /* success return 0 */
110 }
111 }
112 else /* spi interface */
113 {
114 if (len > 1) /* len > 1*/
115 {
116 reg |= 1 << 6; /* flag address increment */
117 }
118 reg |= 1 << 7; /* set read bit */
119
120 if (handle->spi_read(reg, buf, len) != 0) /* read data */
121 {
122 return 1; /* return error */
123 }
124 else
125 {
126 return 0; /* success return 0 */
127 }
128 }
129}
130
142static uint8_t a_l3gd20h_iic_spi_write(l3gd20h_handle_t *handle, uint8_t reg, uint8_t *buf, uint16_t len)
143{
144 if (handle->iic_spi == L3GD20H_INTERFACE_IIC) /* iic interface */
145 {
146 if (len > 1) /* len > 1 */
147 {
148 reg |= 1 << 7; /* flag bit 7 */
149 }
150
151 if (handle->iic_write(handle->iic_addr, reg, buf, len) != 0) /* write data */
152 {
153 return 1; /* return error */
154 }
155 else
156 {
157 return 0; /* success return 0 */
158 }
159 }
160 else /* spi interface */
161 {
162 if (len > 1) /* len > 1 */
163 {
164 reg |= 1 << 6; /* flag address increment */
165 }
166 reg &= ~(1 << 7); /* set write bit */
167
168 if (handle->spi_write(reg, buf, len) != 0) /* write data */
169 {
170 return 1; /* return error */
171 }
172 else
173 {
174 return 0; /* success return 0 */
175 }
176 }
177}
178
188uint8_t l3gd20h_set_interface(l3gd20h_handle_t *handle, l3gd20h_interface_t interface)
189{
190 if (handle == NULL) /* check handle */
191 {
192 return 2; /* return error */
193 }
194
195 handle->iic_spi = (uint8_t)interface; /* set the interface */
196
197 return 0; /* success return 0 */
198}
199
209uint8_t l3gd20h_get_interface(l3gd20h_handle_t *handle, l3gd20h_interface_t *interface)
210{
211 if (handle == NULL) /* check handle */
212 {
213 return 2; /* return error */
214 }
215
216 *interface = (l3gd20h_interface_t)(handle->iic_spi); /* get the interface */
217
218 return 0; /* success return 0 */
219}
220
230uint8_t l3gd20h_set_addr_pin(l3gd20h_handle_t *handle, l3gd20h_address_t addr_pin)
231{
232 if (handle == NULL) /* check handle */
233 {
234 return 2; /* return error */
235 }
236
237 handle->iic_addr = (uint8_t)addr_pin; /* set the iic address */
238
239 return 0; /* success return 0 */
240}
241
251uint8_t l3gd20h_get_addr_pin(l3gd20h_handle_t *handle, l3gd20h_address_t *addr_pin)
252{
253 if (handle == NULL) /* check handle */
254 {
255 return 2; /* return error */
256 }
257
258 *addr_pin = (l3gd20h_address_t)(handle->iic_addr); /* get the iic address */
259
260 return 0; /* success return 0 */
261}
262
274uint8_t l3gd20h_set_mode(l3gd20h_handle_t *handle, l3gd20h_mode_t mode)
275{
276 uint8_t res, prev;
277
278 if (handle == NULL) /* check handle */
279 {
280 return 2; /* return error */
281 }
282 if (handle->inited != 1) /* check handle initialization */
283 {
284 return 3; /* return error */
285 }
286
287 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL1, (uint8_t *)&prev, 1); /* read config */
288 if (res != 0) /* check result */
289 {
290 handle->debug_print("l3gd20h: read ctrl1 failed.\n"); /* read ctrl1 failed */
291
292 return 1; /* return error */
293 }
294 if (mode == L3GD20H_MODE_SLEEP) /* if sleep mode */
295 {
296 prev |= (1 << 3); /* set pd */
297 prev &= ~(0x07); /* clear config */
298
299 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_CTRL1, (uint8_t *)&prev, 1); /* write config */
300 }
301 else
302 {
303 prev &= ~(1 << 3); /* clear pd */
304 prev |= (mode << 3); /* set mode */
305 prev |= 0x07; /* set x,y,z enable */
306
307 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_CTRL1, (uint8_t *)&prev, 1); /* write config */
308 }
309}
310
322uint8_t l3gd20h_get_mode(l3gd20h_handle_t *handle, l3gd20h_mode_t *mode)
323{
324 uint8_t res, prev;
325
326 if (handle == NULL) /* check handle */
327 {
328 return 2; /* return error */
329 }
330 if (handle->inited != 1) /* check handle initialization */
331 {
332 return 3; /* return error */
333 }
334
335 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL1, (uint8_t *)&prev, 1); /* read config */
336 if (res != 0) /* check result */
337 {
338 handle->debug_print("l3gd20h: read ctrl1 failed.\n"); /* read ctrl1 failed */
339
340 return 1; /* return error */
341 }
342 if ((prev & 0x07) != 0) /* if x,y,z valid */
343 {
344 prev &= 1 << 3; /* set pd */
345 *mode = (l3gd20h_mode_t)((prev >> 3) & 0x01); /* normal or power down mode */
346 }
347 else
348 {
349 if ((prev & (1 << 3)) != 0) /* if pd == 1 */
350 {
351 *mode = L3GD20H_MODE_SLEEP; /* sleep mode*/
352 }
353 else
354 {
355 prev &= 1 << 3; /* set pd */
356 *mode = (l3gd20h_mode_t)((prev >> 3) & 0x01); /* set power down mode */
357 }
358 }
359
360 return 0; /* success return 0 */
361}
362
375uint8_t l3gd20h_set_axis(l3gd20h_handle_t *handle, l3gd20h_axis_t axis, l3gd20h_bool_t enable)
376{
377 uint8_t res, prev;
378
379 if (handle == NULL) /* check handle */
380 {
381 return 2; /* return error */
382 }
383 if (handle->inited != 1) /* check handle initialization */
384 {
385 return 3; /* return error */
386 }
387
388 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL1, (uint8_t *)&prev, 1); /* read config */
389 if (res != 0) /* check result */
390 {
391 handle->debug_print("l3gd20h: read ctrl1 failed.\n"); /* read ctrl1 failed */
392
393 return 1; /* return error */
394 }
395 prev &= ~(1 << axis); /* clear enable bit */
396 prev |= enable << axis; /* set enable */
397
398 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_CTRL1, (uint8_t *)&prev, 1); /* write config */
399}
400
413uint8_t l3gd20h_get_axis(l3gd20h_handle_t *handle, l3gd20h_axis_t axis, l3gd20h_bool_t *enable)
414{
415 uint8_t res, prev;
416
417 if (handle == NULL) /* check handle */
418 {
419 return 2; /* return error */
420 }
421 if (handle->inited != 1) /* check handle initialization */
422 {
423 return 3; /* return error */
424 }
425
426 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL1, (uint8_t *)&prev, 1); /* read config */
427 if (res != 0) /* check result */
428 {
429 handle->debug_print("l3gd20h: read ctrl1 failed.\n"); /* read ctrl1 failed */
430
431 return 1; /* return error */
432 }
433 prev &= (1 << axis); /* get enable bit */
434 *enable = (l3gd20h_bool_t)(prev >> axis); /* get bool */
435
436 return 0; /* success return 0 */
437}
438
450uint8_t l3gd20h_set_rate_bandwidth(l3gd20h_handle_t *handle, l3gd20h_lodr_odr_bw_t rate_bandwidth)
451{
452 uint8_t res, prev;
453
454 if (handle == NULL) /* check handle */
455 {
456 return 2; /* return error */
457 }
458 if (handle->inited != 1) /* check handle initialization */
459 {
460 return 3; /* return error */
461 }
462
463 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL1, (uint8_t *)&prev, 1); /* read config */
464 if (res != 0) /* check result */
465 {
466 handle->debug_print("l3gd20h: read ctrl1 failed.\n"); /* read ctrl1 failed */
467
468 return 1; /* return error */
469 }
470 prev &= ~(0xF << 4); /* clear rate and bandwidth bits */
471 prev |= (rate_bandwidth & 0xF) << 4; /* set rate and bandwidth */
472 if (a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_CTRL1, (uint8_t *)&prev, 1) != 0) /* write config */
473 {
474 handle->debug_print("l3gd20h: write ctrl1 failed.\n"); /* write ctrl1 failed */
475
476 return 1; /* return error */
477 }
478
479 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_LOW_ODR, (uint8_t *)&prev, 1); /* read low odr */
480 if (res != 0) /* check result */
481 {
482 handle->debug_print("l3gd20h: read low odr failed.\n"); /* read low odr failed */
483
484 return 1; /* return error */
485 }
486 prev &= ~(1 << 0); /* clear odr bit */
487 prev |= ((rate_bandwidth & 0x10) >> 4) & 0x01; /* set odr */
488 if (a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_LOW_ODR, (uint8_t *)&prev, 1) != 0) /* write config */
489 {
490 handle->debug_print("l3gd20h: write low odr failed.\n"); /* write low odr failed */
491
492 return 1; /* return error */
493 }
494
495 return 0; /* success return 0 */
496}
497
509uint8_t l3gd20h_get_rate_bandwidth(l3gd20h_handle_t *handle, l3gd20h_lodr_odr_bw_t *rate_bandwidth)
510{
511 uint8_t res, prev1, prev2;
512
513 if (handle == NULL) /* check handle */
514 {
515 return 2; /* return error */
516 }
517 if (handle->inited != 1) /* check handle initialization */
518 {
519 return 3; /* return error */
520 }
521
522 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL1, (uint8_t *)&prev1, 1); /* read config */
523 if (res != 0) /* check result */
524 {
525 handle->debug_print("l3gd20h: read ctrl1 failed.\n"); /* read ctrl1 failed */
526
527 return 1; /* return error */
528 }
529 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_LOW_ODR, (uint8_t *)&prev2, 1); /* read low odr */
530 if (res != 0) /* check result */
531 {
532 handle->debug_print("l3gd20h: read low odr failed.\n"); /* read low odr failed */
533
534 return 1; /* return error */
535 }
536 *rate_bandwidth = (l3gd20h_lodr_odr_bw_t)(((prev2 & 0x01) << 4) | (prev1 >> 4)); /* get rate and bandwidth */
537
538 return 0; /* success return 0 */
539}
540
552uint8_t l3gd20h_set_edge_trigger(l3gd20h_handle_t *handle, l3gd20h_bool_t enable)
553{
554 uint8_t res, prev;
555
556 if (handle == NULL) /* check handle */
557 {
558 return 2; /* return error */
559 }
560 if (handle->inited != 1) /* check handle initialization */
561 {
562 return 3; /* return error */
563 }
564
565 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL2, (uint8_t *)&prev, 1); /* read config */
566 if (res != 0) /* check result */
567 {
568 handle->debug_print("l3gd20h: read ctrl2 failed.\n"); /* read ctrl2 failed */
569
570 return 1; /* return error */
571 }
572 prev &= ~(1 << 7); /* clear enable bit */
573 prev |= enable << 7; /* set enable */
574
575 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_CTRL2, (uint8_t *)&prev, 1); /* write config */
576}
577
589uint8_t l3gd20h_get_edge_trigger(l3gd20h_handle_t *handle, l3gd20h_bool_t *enable)
590{
591 uint8_t res, prev;
592
593 if (handle == NULL) /* check handle */
594 {
595 return 2; /* return error */
596 }
597 if (handle->inited != 1) /* check handle initialization */
598 {
599 return 3; /* return error */
600 }
601
602 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL2, (uint8_t *)&prev, 1); /* read config */
603 if (res != 0) /* check result */
604 {
605 handle->debug_print("l3gd20h: read ctrl2 failed.\n"); /* read ctrl2 failed */
606
607 return 1; /* return error */
608 }
609
610 prev &= (1 << 7); /* get enable bit */
611 *enable = (l3gd20h_bool_t)(prev >> 7); /* get bool */
612
613 return 0; /* success return 0 */
614}
615
627uint8_t l3gd20h_set_level_trigger(l3gd20h_handle_t *handle, l3gd20h_bool_t enable)
628{
629 uint8_t res, prev;
630
631 if (handle == NULL) /* check handle */
632 {
633 return 2; /* return error */
634 }
635 if (handle->inited != 1) /* check handle initialization */
636 {
637 return 3; /* return error */
638 }
639
640 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL2, (uint8_t *)&prev, 1); /* read config */
641 if (res != 0) /* check result */
642 {
643 handle->debug_print("l3gd20h: read ctrl2 failed.\n"); /* read ctrl2 failed */
644
645 return 1; /* return error */
646 }
647 prev &= ~(1 << 6); /* clear settings */
648 prev |= enable << 6; /* set enable */
649
650 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_CTRL2, (uint8_t *)&prev, 1); /* write config */
651}
652
664uint8_t l3gd20h_get_level_trigger(l3gd20h_handle_t *handle, l3gd20h_bool_t *enable)
665{
666 uint8_t res, prev;
667
668 if (handle == NULL) /* check handle */
669 {
670 return 2; /* return error */
671 }
672 if (handle->inited != 1) /* check handle initialization */
673 {
674 return 3; /* return error */
675 }
676
677 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL2, (uint8_t *)&prev, 1); /* read config */
678 if (res != 0) /* check result */
679 {
680 handle->debug_print("l3gd20h: read ctrl2 failed.\n"); /* read ctrl2 failed */
681
682 return 1; /* return error */
683 }
684 prev &= (1 << 6); /* get enable */
685 *enable = (l3gd20h_bool_t)(prev >> 6); /* get bool */
686
687 return 0; /* success return 0 */
688}
689
701uint8_t l3gd20h_set_high_pass_filter_mode(l3gd20h_handle_t *handle, l3gd20h_high_pass_filter_mode_t mode)
702{
703 uint8_t res, prev;
704
705 if (handle == NULL) /* check handle */
706 {
707 return 2; /* return error */
708 }
709 if (handle->inited != 1) /* check handle initialization */
710 {
711 return 3; /* return error */
712 }
713
714 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL2, (uint8_t *)&prev, 1); /* read config */
715 if (res != 0) /* check result */
716 {
717 handle->debug_print("l3gd20h: read ctrl2 failed.\n"); /* read ctrl2 failed */
718
719 return 1; /* return error */
720 }
721 prev &= ~(3 << 4); /* clear the mode */
722 prev |= mode << 4; /* set the mode */
723
724 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_CTRL2, (uint8_t *)&prev, 1); /* write config */
725}
726
738uint8_t l3gd20h_get_high_pass_filter_mode(l3gd20h_handle_t *handle, l3gd20h_high_pass_filter_mode_t *mode)
739{
740 uint8_t res, prev;
741
742 if (handle == NULL) /* check handle */
743 {
744 return 2; /* return error */
745 }
746 if (handle->inited != 1) /* check handle initialization */
747 {
748 return 3; /* return error */
749 }
750
751 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL2, (uint8_t *)&prev, 1); /* read config */
752 if (res != 0) /* check result */
753 {
754 handle->debug_print("l3gd20h: read ctrl2 failed.\n"); /* read ctrl2 failed */
755
756 return 1; /* return error */
757 }
758 prev &= (3 << 4); /* get the mode bits */
759 *mode = (l3gd20h_high_pass_filter_mode_t)(prev >> 4); /* get the mode */
760
761 return 0; /* success return 0 */
762}
763
775uint8_t l3gd20h_set_high_pass_filter_cut_off_frequency(l3gd20h_handle_t *handle, l3gd20h_high_pass_filter_cut_off_frequency_t frequency)
776{
777 uint8_t res, prev;
778
779 if (handle == NULL) /* check handle */
780 {
781 return 2; /* return error */
782 }
783 if (handle->inited != 1) /* check handle initialization */
784 {
785 return 3; /* return error */
786 }
787
788 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL2, (uint8_t *)&prev, 1); /* read config */
789 if (res != 0) /* check result */
790 {
791 handle->debug_print("l3gd20h: read ctrl2 failed.\n"); /* read ctrl2 failed */
792
793 return 1; /* return error */
794 }
795 prev &= ~(0x0F); /* clear the cut-off frequency */
796 prev |= frequency; /* set the frequency */
797
798 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_CTRL2, (uint8_t *)&prev, 1); /* write config */
799}
800
812uint8_t l3gd20h_get_high_pass_filter_cut_off_frequency(l3gd20h_handle_t *handle, l3gd20h_high_pass_filter_cut_off_frequency_t *frequency)
813{
814 uint8_t res, prev;
815
816 if (handle == NULL) /* check handle */
817 {
818 return 2; /* return error */
819 }
820 if (handle->inited != 1) /* check handle initialization */
821 {
822 return 3; /* return error */
823 }
824
825 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL2, (uint8_t *)&prev, 1); /* read config */
826 if (res != 0) /* check result */
827 {
828 handle->debug_print("l3gd20h: read ctrl2 failed.\n"); /* read ctrl2 failed */
829
830 return 1; /* return error */
831 }
832 prev &= 0x0F; /* get the cut-off frequency */
833 *frequency = (l3gd20h_high_pass_filter_cut_off_frequency_t)(prev >> 0); /* get the frequency */
834
835 return 0; /* success return 0 */
836}
837
849uint8_t l3gd20h_set_interrupt1(l3gd20h_handle_t *handle, l3gd20h_bool_t enable)
850{
851 uint8_t res, prev;
852
853 if (handle == NULL) /* check handle */
854 {
855 return 2; /* return error */
856 }
857 if (handle->inited != 1) /* check handle initialization */
858 {
859 return 3; /* return error */
860 }
861
862 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL3, (uint8_t *)&prev, 1); /* read config */
863 if (res != 0) /* check result */
864 {
865 handle->debug_print("l3gd20h: read ctrl3 failed.\n"); /* read ctrl3 failed */
866
867 return 1; /* return error */
868 }
869 prev &= ~(1 << 7); /* clear enable */
870 prev |= enable << 7; /* set enable */
871
872 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_CTRL3, (uint8_t *)&prev, 1); /* write config */
873}
874
886uint8_t l3gd20h_get_interrupt1(l3gd20h_handle_t *handle, l3gd20h_bool_t *enable)
887{
888 uint8_t res, prev;
889
890 if (handle == NULL) /* check handle */
891 {
892 return 2; /* return error */
893 }
894 if (handle->inited != 1) /* check handle initialization */
895 {
896 return 3; /* return error */
897 }
898
899 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL3, (uint8_t *)&prev, 1); /* read config */
900 if (res != 0) /* check result */
901 {
902 handle->debug_print("l3gd20h: read ctrl3 failed.\n"); /* read ctrl3 failed */
903
904 return 1; /* return error */
905 }
906 prev &= (1 << 7); /* get enable bit */
907 *enable = (l3gd20h_bool_t)(prev >> 7); /* get bool */
908
909 return 0; /* success return 0 */
910}
911
923uint8_t l3gd20h_set_boot_on_interrupt1(l3gd20h_handle_t *handle, l3gd20h_bool_t enable)
924{
925 uint8_t res, prev;
926
927 if (handle == NULL) /* check handle */
928 {
929 return 2; /* return error */
930 }
931 if (handle->inited != 1) /* check handle initialization */
932 {
933 return 3; /* return error */
934 }
935
936 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL3, (uint8_t *)&prev, 1); /* read config */
937 if (res != 0) /* check result */
938 {
939 handle->debug_print("l3gd20h: read ctrl3 failed.\n"); /* read ctrl3 failed */
940
941 return 1; /* return error */
942 }
943 prev &= ~(1 << 6); /* clear enable bit */
944 prev |= enable << 6; /* set enable */
945
946 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_CTRL3, (uint8_t *)&prev, 1); /* write config */
947}
948
960uint8_t l3gd20h_get_boot_on_interrupt1(l3gd20h_handle_t *handle, l3gd20h_bool_t *enable)
961{
962 uint8_t res, prev;
963
964 if (handle == NULL) /* check handle */
965 {
966 return 2; /* return error */
967 }
968 if (handle->inited != 1) /* check handle initialization */
969 {
970 return 3; /* return error */
971 }
972
973 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL3, (uint8_t *)&prev, 1); /* read config */
974 if (res != 0) /* check result */
975 {
976 handle->debug_print("l3gd20h: read ctrl3 failed.\n"); /* read ctrl3 failed */
977
978 return 1; /* return error */
979 }
980 prev &= (1 << 6); /* get enable bit */
981 *enable = (l3gd20h_bool_t)(prev >> 6); /* get bool */
982
983 return 0; /* success return 0 */
984}
985
997uint8_t l3gd20h_set_interrupt_active_level(l3gd20h_handle_t *handle, l3gd20h_interrupt_active_level_t level)
998{
999 uint8_t res, prev;
1000
1001 if (handle == NULL) /* check handle */
1002 {
1003 return 2; /* return error */
1004 }
1005 if (handle->inited != 1) /* check handle initialization */
1006 {
1007 return 3; /* return error */
1008 }
1009
1010 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL3, (uint8_t *)&prev, 1); /* read config */
1011 if (res != 0) /* check result */
1012 {
1013 handle->debug_print("l3gd20h: read ctrl3 failed.\n"); /* read ctrl3 failed */
1014
1015 return 1; /* return error */
1016 }
1017 prev &= ~(1 << 5); /* clear level bit */
1018 prev |= level << 5; /* set level bit */
1019
1020 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_CTRL3, (uint8_t *)&prev, 1); /* write config */
1021}
1022
1034uint8_t l3gd20h_get_interrupt_active_level(l3gd20h_handle_t *handle, l3gd20h_interrupt_active_level_t *level)
1035{
1036 uint8_t res, prev;
1037
1038 if (handle == NULL) /* check handle */
1039 {
1040 return 2; /* return error */
1041 }
1042 if (handle->inited != 1) /* check handle initialization */
1043 {
1044 return 3; /* return error */
1045 }
1046
1047 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL3, (uint8_t *)&prev, 1); /* read config */
1048 if (res != 0) /* check result */
1049 {
1050 handle->debug_print("l3gd20h: read ctrl3 failed.\n"); /* read ctrl3 failed */
1051
1052 return 1; /* return error */
1053 }
1054 prev &= (1 << 5); /* get the level bit */
1055 *level = (l3gd20h_interrupt_active_level_t)(prev >> 5); /* get the level */
1056
1057 return 0; /* success return 0 */
1058}
1059
1071uint8_t l3gd20h_set_interrupt_pin_type(l3gd20h_handle_t *handle, l3gd20h_pin_type_t pin_type)
1072{
1073 uint8_t res, prev;
1074
1075 if (handle == NULL) /* check handle */
1076 {
1077 return 2; /* return error */
1078 }
1079 if (handle->inited != 1) /* check handle initialization */
1080 {
1081 return 3; /* return error */
1082 }
1083
1084 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL3, (uint8_t *)&prev, 1); /* read config */
1085 if (res != 0) /* check result */
1086 {
1087 handle->debug_print("l3gd20h: read ctrl3 failed.\n"); /* read ctrl3 failed */
1088
1089 return 1; /* return error */
1090 }
1091 prev &= ~(1 << 4); /* clear pin type bit */
1092 prev |= pin_type << 4; /* set pin type */
1093
1094 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_CTRL3, (uint8_t *)&prev, 1); /* write config */
1095}
1096
1108uint8_t l3gd20h_get_interrupt_pin_type(l3gd20h_handle_t *handle, l3gd20h_pin_type_t *pin_type)
1109{
1110 uint8_t res, prev;
1111
1112 if (handle == NULL) /* check handle */
1113 {
1114 return 2; /* return error */
1115 }
1116 if (handle->inited != 1) /* check handle initialization */
1117 {
1118 return 3; /* return error */
1119 }
1120
1121 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL3, (uint8_t *)&prev, 1); /* read config */
1122 if (res != 0) /* check result */
1123 {
1124 handle->debug_print("l3gd20h: read ctrl3 failed.\n"); /* read ctrl3 failed */
1125
1126 return 1; /* return error */
1127 }
1128 prev &= (1 << 4); /* get pin type bit */
1129 *pin_type = (l3gd20h_pin_type_t)(prev >> 4); /* get pin type */
1130
1131 return 0; /* success return 0 */
1132}
1133
1145uint8_t l3gd20h_set_data_ready_on_interrupt2(l3gd20h_handle_t *handle, l3gd20h_bool_t enable)
1146{
1147 uint8_t res, prev;
1148
1149 if (handle == NULL) /* check handle */
1150 {
1151 return 2; /* return error */
1152 }
1153 if (handle->inited != 1) /* check handle initialization */
1154 {
1155 return 3; /* return error */
1156 }
1157
1158 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL3, (uint8_t *)&prev, 1); /* read config */
1159 if (res != 0) /* check result */
1160 {
1161 handle->debug_print("l3gd20h: read ctrl3 failed.\n"); /* read ctrl3 failed */
1162
1163 return 1; /* return error */
1164 }
1165 prev &= ~(1 << 3); /* clear data ready bit */
1166 prev |= enable << 3; /* set data ready */
1167
1168 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_CTRL3, (uint8_t *)&prev, 1); /* write config */
1169}
1170
1182uint8_t l3gd20h_get_data_ready_on_interrupt2(l3gd20h_handle_t *handle, l3gd20h_bool_t *enable)
1183{
1184 uint8_t res, prev;
1185
1186 if (handle == NULL) /* check handle */
1187 {
1188 return 2; /* return error */
1189 }
1190 if (handle->inited != 1) /* check handle initialization */
1191 {
1192 return 3; /* return error */
1193 }
1194
1195 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL3, (uint8_t *)&prev, 1); /* read config */
1196 if (res != 0) /* check result */
1197 {
1198 handle->debug_print("l3gd20h: read ctrl3 failed.\n"); /* read ctrl3 failed */
1199
1200 return 1; /* return error */
1201 }
1202 prev &= (1 << 3); /* get enable bit */
1203 *enable = (l3gd20h_bool_t)(prev >> 3); /* get bool */
1204
1205 return 0; /* success return 0 */
1206}
1207
1219uint8_t l3gd20h_set_fifo_threshold_on_interrupt2(l3gd20h_handle_t *handle, l3gd20h_bool_t enable)
1220{
1221 uint8_t res, prev;
1222
1223 if (handle == NULL) /* check handle */
1224 {
1225 return 2; /* return error */
1226 }
1227 if (handle->inited != 1) /* check handle initialization */
1228 {
1229 return 3; /* return error */
1230 }
1231
1232 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL3, (uint8_t *)&prev, 1); /* read config */
1233 if (res != 0) /* check result */
1234 {
1235 handle->debug_print("l3gd20h: read ctrl3 failed.\n"); /* read ctrl3 failed */
1236
1237 return 1; /* return error */
1238 }
1239 prev &= ~(1 << 2); /* clear enable bit */
1240 prev |= enable << 2; /* set enable */
1241
1242 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_CTRL3, (uint8_t *)&prev, 1); /* write config */
1243}
1244
1256uint8_t l3gd20h_get_fifo_threshold_on_interrupt2(l3gd20h_handle_t *handle, l3gd20h_bool_t *enable)
1257{
1258 uint8_t res, prev;
1259
1260 if (handle == NULL) /* check handle */
1261 {
1262 return 2; /* return error */
1263 }
1264 if (handle->inited != 1) /* check handle initialization */
1265 {
1266 return 3; /* return error */
1267 }
1268
1269 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL3, (uint8_t *)&prev, 1); /* read config */
1270 if (res != 0) /* check result */
1271 {
1272 handle->debug_print("l3gd20h: read ctrl3 failed.\n"); /* read ctrl3 failed */
1273
1274 return 1; /* return error */
1275 }
1276 prev &= (1 << 2); /* get enable bit */
1277 *enable = (l3gd20h_bool_t)(prev >> 2); /* get bool */
1278
1279 return 0; /* success return 0 */
1280}
1281
1293uint8_t l3gd20h_set_fifo_overrun_on_interrupt2(l3gd20h_handle_t *handle, l3gd20h_bool_t enable)
1294{
1295 uint8_t res, prev;
1296
1297 if (handle == NULL) /* check handle */
1298 {
1299 return 2; /* return error */
1300 }
1301 if (handle->inited != 1) /* check handle initialization */
1302 {
1303 return 3; /* return error */
1304 }
1305
1306 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL3, (uint8_t *)&prev, 1); /* read config */
1307 if (res != 0) /* check result */
1308 {
1309 handle->debug_print("l3gd20h: read ctrl3 failed.\n"); /* read ctrl3 failed */
1310
1311 return 1; /* return error */
1312 }
1313 prev &= ~(1 << 1); /* clear enable bit */
1314 prev |= enable << 1; /* set enable */
1315
1316 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_CTRL3, (uint8_t *)&prev, 1); /* write config */
1317}
1318
1330uint8_t l3gd20h_get_fifo_overrun_on_interrupt2(l3gd20h_handle_t *handle, l3gd20h_bool_t *enable)
1331{
1332 uint8_t res, prev;
1333
1334 if (handle == NULL) /* check handle */
1335 {
1336 return 2; /* return error */
1337 }
1338 if (handle->inited != 1) /* check handle initialization */
1339 {
1340 return 3; /* return error */
1341 }
1342
1343 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL3, (uint8_t *)&prev, 1); /* read config */
1344 if (res != 0) /* check result */
1345 {
1346 handle->debug_print("l3gd20h: read ctrl3 failed.\n"); /* read ctrl3 failed */
1347
1348 return 1; /* return error */
1349 }
1350 prev &= (1 << 1); /* get enable bit */
1351 *enable = (l3gd20h_bool_t)(prev >> 1); /* get bool */
1352
1353 return 0; /* success return 0 */
1354}
1355
1367uint8_t l3gd20h_set_fifo_empty_on_interrupt2(l3gd20h_handle_t *handle, l3gd20h_bool_t enable)
1368{
1369 uint8_t res, prev;
1370
1371 if (handle == NULL) /* check handle */
1372 {
1373 return 2; /* return error */
1374 }
1375 if (handle->inited != 1) /* check handle initialization */
1376 {
1377 return 3; /* return error */
1378 }
1379
1380 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL3, (uint8_t *)&prev, 1); /* read config */
1381 if (res != 0) /* check result */
1382 {
1383 handle->debug_print("l3gd20h: read ctrl3 failed.\n"); /* read ctrl3 failed */
1384
1385 return 1; /* return error */
1386 }
1387 prev &= ~(1 << 0); /* clear enable bit */
1388 prev |= enable << 0; /* set enable */
1389
1390 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_CTRL3, (uint8_t *)&prev, 1); /* write config */
1391}
1392
1404uint8_t l3gd20h_get_fifo_empty_on_interrupt2(l3gd20h_handle_t *handle, l3gd20h_bool_t *enable)
1405{
1406 uint8_t res, prev;
1407
1408 if (handle == NULL) /* check handle */
1409 {
1410 return 2; /* return error */
1411 }
1412 if (handle->inited != 1) /* check handle initialization */
1413 {
1414 return 3; /* return error */
1415 }
1416
1417 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL3, (uint8_t *)&prev, 1); /* read config */
1418 if (res != 0) /* check result */
1419 {
1420 handle->debug_print("l3gd20h: read ctrl3 failed.\n"); /* read ctrl3 failed */
1421
1422 return 1; /* return error */
1423 }
1424 prev &= (1 << 0); /* get enable bit */
1425 *enable = (l3gd20h_bool_t)(prev >> 0); /* get bool */
1426
1427 return 0; /* success return 0 */
1428}
1429
1441uint8_t l3gd20h_set_block_data_update(l3gd20h_handle_t *handle, l3gd20h_bool_t enable)
1442{
1443 uint8_t res, prev;
1444
1445 if (handle == NULL) /* check handle */
1446 {
1447 return 2; /* return error */
1448 }
1449 if (handle->inited != 1) /* check handle initialization */
1450 {
1451 return 3; /* return error */
1452 }
1453
1454 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL4, (uint8_t *)&prev, 1); /* read config */
1455 if (res != 0) /* check result */
1456 {
1457 handle->debug_print("l3gd20h: read ctrl4 failed.\n"); /* read ctrl4 failed */
1458
1459 return 1; /* return error */
1460 }
1461 prev &= ~(1 << 7); /* clear enable bit */
1462 prev |= enable << 7; /* set enable */
1463
1464 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_CTRL4, (uint8_t *)&prev, 1); /* write config */
1465}
1466
1478uint8_t l3gd20h_get_block_data_update(l3gd20h_handle_t *handle, l3gd20h_bool_t *enable)
1479{
1480 uint8_t res, prev;
1481
1482 if (handle == NULL) /* check handle */
1483 {
1484 return 2; /* return error */
1485 }
1486 if (handle->inited != 1) /* check handle initialization */
1487 {
1488 return 3; /* return error */
1489 }
1490
1491 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL4, (uint8_t *)&prev, 1); /* read config */
1492 if (res != 0) /* check result */
1493 {
1494 handle->debug_print("l3gd20h: read ctrl4 failed.\n"); /* read ctrl4 failed */
1495
1496 return 1; /* return error */
1497 }
1498 prev &= (1 << 7); /* get enable bit */
1499 *enable = (l3gd20h_bool_t)(prev >> 7); /* get bool */
1500
1501 return 0; /* success return 0 */
1502}
1503
1515uint8_t l3gd20h_set_data_format(l3gd20h_handle_t *handle, l3gd20h_data_format_t data_format)
1516{
1517 uint8_t res, prev;
1518
1519 if (handle == NULL) /* check handle */
1520 {
1521 return 2; /* return error */
1522 }
1523 if (handle->inited != 1) /* check handle initialization */
1524 {
1525 return 3; /* return error */
1526 }
1527
1528 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL4, (uint8_t *)&prev, 1); /* read config */
1529 if (res != 0) /* check result */
1530 {
1531 handle->debug_print("l3gd20h: read ctrl4 failed.\n"); /* read ctrl4 failed */
1532
1533 return 1; /* return error */
1534 }
1535 prev &= ~(1 << 6); /* clear enable bit */
1536 prev |= data_format << 6; /* set enable */
1537
1538 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_CTRL4, (uint8_t *)&prev, 1); /* write config */
1539}
1540
1552uint8_t l3gd20h_get_data_format(l3gd20h_handle_t *handle, l3gd20h_data_format_t *data_format)
1553{
1554 uint8_t res, prev;
1555
1556 if (handle == NULL) /* check handle */
1557 {
1558 return 2; /* return error */
1559 }
1560 if (handle->inited != 1) /* check handle initialization */
1561 {
1562 return 3; /* return error */
1563 }
1564
1565 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL4, (uint8_t *)&prev, 1); /* read config */
1566 if (res != 0) /* check result */
1567 {
1568 handle->debug_print("l3gd20h: read ctrl4 failed.\n"); /* read ctrl4 failed */
1569
1570 return 1; /* return error */
1571 }
1572 prev &= (1 << 6); /* get enable bit */
1573 *data_format = (l3gd20h_data_format_t)(prev >> 6); /* set enable */
1574
1575 return 0; /* success return 0 */
1576}
1577
1589uint8_t l3gd20h_set_full_scale(l3gd20h_handle_t *handle, l3gd20h_full_scale_t full_scale)
1590{
1591 uint8_t res, prev;
1592
1593 if (handle == NULL) /* check handle */
1594 {
1595 return 2; /* return error */
1596 }
1597 if (handle->inited != 1) /* check handle initialization */
1598 {
1599 return 3; /* return error */
1600 }
1601
1602 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL4, (uint8_t *)&prev, 1); /* read config */
1603 if (res != 0) /* check result */
1604 {
1605 handle->debug_print("l3gd20h: read ctrl4 failed.\n"); /* read ctrl4 failed */
1606
1607 return 1; /* return error */
1608 }
1609 prev &= ~(3 << 4); /* clear the scale bits */
1610 prev |= full_scale << 4; /* set scale */
1611
1612 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_CTRL4, (uint8_t *)&prev, 1); /* write config */
1613}
1614
1626uint8_t l3gd20h_get_full_scale(l3gd20h_handle_t *handle, l3gd20h_full_scale_t *full_scale)
1627{
1628 uint8_t res, prev;
1629
1630 if (handle == NULL) /* check handle */
1631 {
1632 return 2; /* return error */
1633 }
1634 if (handle->inited != 1) /* check handle initialization */
1635 {
1636 return 3; /* return error */
1637 }
1638
1639 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL4, (uint8_t *)&prev, 1); /* read config */
1640 if (res != 0) /* check result */
1641 {
1642 handle->debug_print("l3gd20h: read ctrl4 failed.\n"); /* read ctrl4 failed */
1643
1644 return 1; /* return error */
1645 }
1646 prev &= (3 << 4); /* get scale bits */
1647 *full_scale = (l3gd20h_full_scale_t)(prev >> 4); /* get scale */
1648
1649 return 0; /* success return 0 */
1650}
1651
1663uint8_t l3gd20h_set_level_sensitive_latched(l3gd20h_handle_t *handle, l3gd20h_bool_t enable)
1664{
1665 uint8_t res, prev;
1666
1667 if (handle == NULL) /* check handle */
1668 {
1669 return 2; /* return error */
1670 }
1671 if (handle->inited != 1) /* check handle initialization */
1672 {
1673 return 3; /* return error */
1674 }
1675
1676 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL4, (uint8_t *)&prev, 1); /* read config */
1677 if (res != 0) /* check result */
1678 {
1679 handle->debug_print("l3gd20h: read ctrl4 failed.\n"); /* read ctrl4 failed */
1680
1681 return 1; /* return error */
1682 }
1683 prev &= ~(1 << 3); /* clear enable bit */
1684 prev |= enable << 3; /* set enable */
1685
1686 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_CTRL4, (uint8_t *)&prev, 1); /* write config */
1687}
1688
1700uint8_t l3gd20h_get_level_sensitive_latched(l3gd20h_handle_t *handle, l3gd20h_bool_t *enable)
1701{
1702 uint8_t res, prev;
1703
1704 if (handle == NULL) /* check handle */
1705 {
1706 return 2; /* return error */
1707 }
1708 if (handle->inited != 1) /* check handle initialization */
1709 {
1710 return 3; /* return error */
1711 }
1712
1713 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL4, (uint8_t *)&prev, 1); /* read config */
1714 if (res != 0) /* check result */
1715 {
1716 handle->debug_print("l3gd20h: read ctrl4 failed.\n"); /* read ctrl4 failed */
1717
1718 return 1; /* return error */
1719 }
1720 prev &= (1 << 3); /* get enable bit */
1721 *enable = (l3gd20h_bool_t)(prev >> 3); /* get bool */
1722
1723 return 0; /* success return 0 */
1724}
1725
1737uint8_t l3gd20h_set_self_test(l3gd20h_handle_t *handle, l3gd20h_self_test_t self_test)
1738{
1739 uint8_t res, prev;
1740
1741 if (handle == NULL) /* check handle */
1742 {
1743 return 2; /* return error */
1744 }
1745 if (handle->inited != 1) /* check handle initialization */
1746 {
1747 return 3; /* return error */
1748 }
1749
1750 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL4, (uint8_t *)&prev, 1); /* read config */
1751 if (res != 0) /* check result */
1752 {
1753 handle->debug_print("l3gd20h: read ctrl4 failed.\n"); /* read ctrl4 failed */
1754
1755 return 1; /* return error */
1756 }
1757 prev &= ~(3 << 1); /* clear self test bits */
1758 prev |= self_test << 1; /* set self test */
1759
1760 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_CTRL4, (uint8_t *)&prev, 1); /* write config */
1761}
1762
1774uint8_t l3gd20h_get_self_test(l3gd20h_handle_t *handle, l3gd20h_self_test_t *self_test)
1775{
1776 uint8_t res, prev;
1777
1778 if (handle == NULL) /* check handle */
1779 {
1780 return 2; /* return error */
1781 }
1782 if (handle->inited != 1) /* check handle initialization */
1783 {
1784 return 3; /* return error */
1785 }
1786
1787 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL4, (uint8_t *)&prev, 1); /* read config */
1788 if (res != 0) /* check result */
1789 {
1790 handle->debug_print("l3gd20h: read ctrl4 failed.\n"); /* read ctrl4 failed */
1791
1792 return 1; /* return error */
1793 }
1794 prev &= (3 << 1); /* get self test bits */
1795 *self_test = (l3gd20h_self_test_t)(prev >> 1); /* get self test */
1796
1797 return 0; /* success return 0 */
1798}
1799
1811uint8_t l3gd20h_set_spi_wire(l3gd20h_handle_t *handle, l3gd20h_spi_wire_t spi_wire)
1812{
1813 uint8_t res, prev;
1814
1815 if (handle == NULL) /* check handle */
1816 {
1817 return 2; /* return error */
1818 }
1819 if (handle->inited != 1) /* check handle initialization */
1820 {
1821 return 3; /* return error */
1822 }
1823
1824 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL4, (uint8_t *)&prev, 1); /* read config */
1825 if (res != 0) /* check result */
1826 {
1827 handle->debug_print("l3gd20h: read ctrl4 failed.\n"); /* read ctrl4 failed */
1828
1829 return 1; /* return error */
1830 }
1831 prev &= ~(1 << 0); /* clear spi wire bit */
1832 prev |= spi_wire << 0; /* set spi wire */
1833
1834 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_CTRL4, (uint8_t *)&prev, 1); /* write config */
1835}
1836
1848uint8_t l3gd20h_get_spi_wire(l3gd20h_handle_t *handle, l3gd20h_spi_wire_t *spi_wire)
1849{
1850 uint8_t res, prev;
1851
1852 if (handle == NULL) /* check handle */
1853 {
1854 return 2; /* return error */
1855 }
1856 if (handle->inited != 1) /* check handle initialization */
1857 {
1858 return 3; /* return error */
1859 }
1860
1861 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL4, (uint8_t *)&prev, 1); /* read config */
1862 if (res != 0) /* check result */
1863 {
1864 handle->debug_print("l3gd20h: read ctrl4 failed.\n"); /* read ctrl4 failed */
1865
1866 return 1; /* return error */
1867 }
1868 prev &= (1 << 0); /* get spi wire bit */
1869 *spi_wire = (l3gd20h_spi_wire_t)(prev >> 0); /* get spi wire */
1870
1871 return 0; /* success return 0 */
1872}
1873
1885uint8_t l3gd20h_set_boot(l3gd20h_handle_t *handle, l3gd20h_boot_t boot)
1886{
1887 uint8_t res, prev;
1888
1889 if (handle == NULL) /* check handle */
1890 {
1891 return 2; /* return error */
1892 }
1893 if (handle->inited != 1) /* check handle initialization */
1894 {
1895 return 3; /* return error */
1896 }
1897
1898 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL5, (uint8_t *)&prev, 1); /* read config */
1899 if (res != 0) /* check result */
1900 {
1901 handle->debug_print("l3gd20h: read ctrl5 failed.\n"); /* read ctrl5 failed */
1902
1903 return 1; /* return error */
1904 }
1905 prev &= ~(1 << 7); /* clear boot */
1906 prev |= boot << 7; /* set boot */
1907
1908 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_CTRL5, (uint8_t *)&prev, 1); /* write config */
1909}
1910
1922uint8_t l3gd20h_get_boot(l3gd20h_handle_t *handle, l3gd20h_boot_t *boot)
1923{
1924 uint8_t res, prev;
1925
1926 if (handle == NULL) /* check handle */
1927 {
1928 return 2; /* return error */
1929 }
1930 if (handle->inited != 1) /* check handle initialization */
1931 {
1932 return 3; /* return error */
1933 }
1934
1935 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL5, (uint8_t *)&prev, 1); /* read config */
1936 if (res != 0) /* check result */
1937 {
1938 handle->debug_print("l3gd20h: read ctrl5 failed.\n"); /* read ctrl5 failed */
1939
1940 return 1; /* return error */
1941 }
1942 prev &= (1 << 7); /* get enable bit */
1943 *boot = (l3gd20h_boot_t)(prev >> 7); /* get bool */
1944
1945 return 0; /* success return 0 */
1946}
1947
1959uint8_t l3gd20h_set_fifo(l3gd20h_handle_t *handle, l3gd20h_bool_t enable)
1960{
1961 uint8_t res, prev;
1962
1963 if (handle == NULL) /* check handle */
1964 {
1965 return 2; /* return error */
1966 }
1967 if (handle->inited != 1) /* check handle initialization */
1968 {
1969 return 3; /* return error */
1970 }
1971
1972 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL5, (uint8_t *)&prev, 1); /* read config */
1973 if (res != 0) /* check result */
1974 {
1975 handle->debug_print("l3gd20h: read ctrl5 failed.\n"); /* read ctrl5 failed */
1976
1977 return 1; /* return error */
1978 }
1979 prev &= ~(1 << 6); /* clear enable bit */
1980 prev |= enable << 6; /* set enable */
1981
1982 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_CTRL5, (uint8_t *)&prev, 1); /* write config */
1983}
1984
1996uint8_t l3gd20h_get_fifo(l3gd20h_handle_t *handle, l3gd20h_bool_t *enable)
1997{
1998 uint8_t res, prev;
1999
2000 if (handle == NULL) /* check handle */
2001 {
2002 return 2; /* return error */
2003 }
2004 if (handle->inited != 1) /* check handle initialization */
2005 {
2006 return 3; /* return error */
2007 }
2008
2009 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL5, (uint8_t *)&prev, 1); /* read config */
2010 if (res != 0) /* check result */
2011 {
2012 handle->debug_print("l3gd20h: read ctrl5 failed.\n"); /* read ctrl5 failed */
2013
2014 return 1; /* return error */
2015 }
2016 prev &= (1 << 6); /* get enable bit */
2017 *enable = (l3gd20h_bool_t)(prev >> 6); /* get bool */
2018
2019 return 0; /* success return 0 */
2020}
2021
2033uint8_t l3gd20h_set_stop_on_fifo_threshold(l3gd20h_handle_t *handle, l3gd20h_bool_t enable)
2034{
2035 uint8_t res, prev;
2036
2037 if (handle == NULL) /* check handle */
2038 {
2039 return 2; /* return error */
2040 }
2041 if (handle->inited != 1) /* check handle initialization */
2042 {
2043 return 3; /* return error */
2044 }
2045
2046 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL5, (uint8_t *)&prev, 1); /* read config */
2047 if (res != 0) /* check result */
2048 {
2049 handle->debug_print("l3gd20h: read ctrl5 failed.\n"); /* read ctrl5 failed */
2050
2051 return 1; /* return error */
2052 }
2053 prev &= ~(1 << 5); /* clear bit */
2054 prev |= enable << 5; /* set enable */
2055
2056 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_CTRL5, (uint8_t *)&prev, 1); /* write config */
2057}
2058
2070uint8_t l3gd20h_get_stop_on_fifo_threshold(l3gd20h_handle_t *handle, l3gd20h_bool_t *enable)
2071{
2072 uint8_t res, prev;
2073
2074 if (handle == NULL) /* check handle */
2075 {
2076 return 2; /* return error */
2077 }
2078 if (handle->inited != 1) /* check handle initialization */
2079 {
2080 return 3; /* return error */
2081 }
2082
2083 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL5, (uint8_t *)&prev, 1); /* read config */
2084 if (res != 0) /* check result */
2085 {
2086 handle->debug_print("l3gd20h: read ctrl5 failed.\n"); /* read ctrl5 failed */
2087
2088 return 1; /* return error */
2089 }
2090 prev &= (1 << 5); /* get enable bit */
2091 *enable = (l3gd20h_bool_t)(prev >> 5); /* get bool */
2092
2093 return 0; /* success return 0 */
2094}
2095
2107uint8_t l3gd20h_set_high_pass_filter(l3gd20h_handle_t *handle, l3gd20h_bool_t enable)
2108{
2109 uint8_t res, prev;
2110
2111 if (handle == NULL) /* check handle */
2112 {
2113 return 2; /* return error */
2114 }
2115 if (handle->inited != 1) /* check handle initialization */
2116 {
2117 return 3; /* return error */
2118 }
2119
2120 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL5, (uint8_t *)&prev, 1); /* read config */
2121 if (res != 0) /* check result */
2122 {
2123 handle->debug_print("l3gd20h: read ctrl5 failed.\n"); /* read ctrl5 failed */
2124
2125 return 1; /* return error */
2126 }
2127 prev &= ~(1 << 4); /* clear enable bit */
2128 prev |= enable << 4; /* set enable */
2129
2130 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_CTRL5, (uint8_t *)&prev, 1); /* write config */
2131}
2132
2144uint8_t l3gd20h_get_high_pass_filter(l3gd20h_handle_t *handle, l3gd20h_bool_t *enable)
2145{
2146 uint8_t res, prev;
2147
2148 if (handle == NULL) /* check handle */
2149 {
2150 return 2; /* return error */
2151 }
2152 if (handle->inited != 1) /* check handle initialization */
2153 {
2154 return 3; /* return error */
2155 }
2156
2157 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL5, (uint8_t *)&prev, 1); /* read config */
2158 if (res != 0) /* check result */
2159 {
2160 handle->debug_print("l3gd20h: read ctrl5 failed.\n"); /* read ctrl5 failed */
2161
2162 return 1; /* return error */
2163 }
2164 prev &= (1 << 4); /* get enable bit */
2165 *enable = (l3gd20h_bool_t)(prev >> 4); /* get bool */
2166
2167 return 0; /* success return 0 */
2168}
2169
2181uint8_t l3gd20h_set_interrupt_selection(l3gd20h_handle_t *handle, l3gd20h_selection_t selection)
2182{
2183 uint8_t res, prev;
2184
2185 if (handle == NULL) /* check handle */
2186 {
2187 return 2; /* return error */
2188 }
2189 if (handle->inited != 1) /* check handle initialization */
2190 {
2191 return 3; /* return error */
2192 }
2193
2194 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL5, (uint8_t *)&prev, 1); /* read config */
2195 if (res != 0) /* check result */
2196 {
2197 handle->debug_print("l3gd20h: read ctrl5 failed.\n"); /* read ctrl5 failed */
2198
2199 return 1; /* return error */
2200 }
2201 prev &= ~(3 << 2); /* clear selection */
2202 prev |= selection << 2; /* set selection */
2203
2204 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_CTRL5, (uint8_t *)&prev, 1); /* write config */
2205}
2206
2218uint8_t l3gd20h_get_interrupt_selection(l3gd20h_handle_t *handle, l3gd20h_selection_t *selection)
2219{
2220 uint8_t res, prev;
2221
2222 if (handle == NULL) /* check handle */
2223 {
2224 return 2; /* return error */
2225 }
2226 if (handle->inited != 1) /* check handle initialization */
2227 {
2228 return 3; /* return error */
2229 }
2230
2231 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL5, (uint8_t *)&prev, 1); /* read config */
2232 if (res != 0) /* check result */
2233 {
2234 handle->debug_print("l3gd20h: read ctrl5 failed.\n"); /* read ctrl5 failed */
2235
2236 return 1; /* return error */
2237 }
2238 prev &= (3 << 2); /* get the selection bits */
2239 *selection = (l3gd20h_selection_t)(prev >> 2); /* get the selection */
2240
2241 return 0; /* success return 0 */
2242}
2243
2255uint8_t l3gd20h_set_out_selection(l3gd20h_handle_t *handle, l3gd20h_selection_t selection)
2256{
2257 uint8_t res, prev;
2258
2259 if (handle == NULL) /* check handle */
2260 {
2261 return 2; /* return error */
2262 }
2263 if (handle->inited != 1) /* check handle initialization */
2264 {
2265 return 3; /* return error */
2266 }
2267
2268 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL5, (uint8_t *)&prev, 1); /* read config */
2269 if (res != 0) /* check result */
2270 {
2271 handle->debug_print("l3gd20h: read ctrl5 failed.\n"); /* read ctrl5 failed */
2272
2273 return 1; /* return error */
2274 }
2275 prev &= ~(3 << 0); /* clear the selection bits */
2276 prev |= selection << 0; /* set the selection */
2277
2278 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_CTRL5, (uint8_t *)&prev, 1); /* write config */
2279}
2280
2292uint8_t l3gd20h_get_out_selection(l3gd20h_handle_t *handle, l3gd20h_selection_t *selection)
2293{
2294 uint8_t res, prev;
2295
2296 if (handle == NULL) /* check handle */
2297 {
2298 return 2; /* return error */
2299 }
2300 if (handle->inited != 1) /* check handle initialization */
2301 {
2302 return 3; /* return error */
2303 }
2304
2305 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL5, (uint8_t *)&prev, 1); /* read config */
2306 if (res != 0) /* check result */
2307 {
2308 handle->debug_print("l3gd20h: read ctrl5 failed.\n"); /* read ctrl5 failed */
2309
2310 return 1; /* return error */
2311 }
2312 prev &= (3 << 0); /* get the selection bits */
2313 *selection = (l3gd20h_selection_t)(prev >> 0); /* get the selection */
2314
2315 return 0; /* success return 0 */
2316}
2317
2329uint8_t l3gd20h_set_high_pass_filter_reference(l3gd20h_handle_t *handle, uint8_t value)
2330{
2331 if (handle == NULL) /* check handle */
2332 {
2333 return 2; /* return error */
2334 }
2335 if (handle->inited != 1) /* check handle initialization */
2336 {
2337 return 3; /* return error */
2338 }
2339
2340 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_REFERENCE, (uint8_t *)&value, 1); /* write config */
2341}
2342
2354uint8_t l3gd20h_get_high_pass_filter_reference(l3gd20h_handle_t *handle, uint8_t *value)
2355{
2356 if (handle == NULL) /* check handle */
2357 {
2358 return 2; /* return error */
2359 }
2360 if (handle->inited != 1) /* check handle initialization */
2361 {
2362 return 3; /* return error */
2363 }
2364
2365 return a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_REFERENCE, (uint8_t *)value, 1); /* read config */
2366}
2367
2380uint8_t l3gd20h_read_temperature(l3gd20h_handle_t *handle, int8_t *raw, float *temp)
2381{
2382 uint8_t res;
2383
2384 if (handle == NULL) /* check handle */
2385 {
2386 return 2; /* return error */
2387 }
2388 if (handle->inited != 1) /* check handle initialization */
2389 {
2390 return 3; /* return error */
2391 }
2392
2393 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_OUT_TEMP, (uint8_t *)raw, 1); /* read data */
2394 if (res != 0) /* check result */
2395 {
2396 handle->debug_print("l3gd20h: read temperature failed.\n"); /* read temperature failed */
2397
2398 return 1; /* return error */
2399 }
2400 *temp = (float)(*raw) * (-1.0f) + 25.0f; /* convert the raw data */
2401
2402 return 0; /* success return 0 */
2403}
2404
2416uint8_t l3gd20h_get_status(l3gd20h_handle_t *handle, uint8_t *status)
2417{
2418 if (handle == NULL) /* check handle */
2419 {
2420 return 2; /* return error */
2421 }
2422 if (handle->inited != 1) /* check handle initialization */
2423 {
2424 return 3; /* return error */
2425 }
2426
2427 return a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_STATUS, (uint8_t *)status, 1); /* read config */
2428}
2429
2441uint8_t l3gd20h_set_fifo_mode(l3gd20h_handle_t *handle, l3gd20h_fifo_mode_t fifo_mode)
2442{
2443 uint8_t res, prev;
2444
2445 if (handle == NULL) /* check handle */
2446 {
2447 return 2; /* return error */
2448 }
2449 if (handle->inited != 1) /* check handle initialization */
2450 {
2451 return 3; /* return error */
2452 }
2453
2454 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_FIFO_CTRL, (uint8_t *)&prev, 1); /* read config */
2455 if (res != 0) /* check result */
2456 {
2457 handle->debug_print("l3gd20h: read fifo ctrl failed.\n"); /* read fifo ctrl failed */
2458
2459 return 1; /* return error */
2460 }
2461 prev &= ~(7 << 5); /* clear fifo mode bits */
2462 prev |= fifo_mode << 5; /* set fifo mode */
2463
2464 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_FIFO_CTRL, (uint8_t *)&prev, 1); /* write config */
2465}
2466
2478uint8_t l3gd20h_get_fifo_mode(l3gd20h_handle_t *handle, l3gd20h_fifo_mode_t *fifo_mode)
2479{
2480 uint8_t res, prev;
2481
2482 if (handle == NULL) /* check handle */
2483 {
2484 return 2; /* return error */
2485 }
2486 if (handle->inited != 1) /* check handle initialization */
2487 {
2488 return 3; /* return error */
2489 }
2490
2491 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_FIFO_CTRL, (uint8_t *)&prev, 1); /* read config */
2492 if (res != 0) /* check result */
2493 {
2494 handle->debug_print("l3gd20h: read fifo ctrl failed.\n"); /* read fifo ctrl failed */
2495
2496 return 1; /* return error */
2497 }
2498 prev &= (7 << 5); /* get fifo mode bits */
2499 *fifo_mode = (l3gd20h_fifo_mode_t)(prev >> 5); /* get fifo mode */
2500
2501 return 0; /* success return 0 */
2502}
2503
2516uint8_t l3gd20h_set_fifo_threshold(l3gd20h_handle_t *handle, uint8_t threshold)
2517{
2518 uint8_t res, prev;
2519
2520 if (handle == NULL) /* check handle */
2521 {
2522 return 2; /* return error */
2523 }
2524 if (handle->inited != 1) /* check handle initialization */
2525 {
2526 return 3; /* return error */
2527 }
2528
2529 if (threshold > 31) /* check the threshold */
2530 {
2531 handle->debug_print("l3gd20h: threshold is invalid.\n"); /* threshold is invalid */
2532
2533 return 4; /* return error */
2534 }
2535 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_FIFO_CTRL, (uint8_t *)&prev, 1); /* read config */
2536 if (res != 0) /* check result */
2537 {
2538 handle->debug_print("l3gd20h: read fifo ctrl failed.\n"); /* read fifo ctrl failed */
2539
2540 return 1; /* return error */
2541 }
2542 prev &= ~(0x1F); /* clear the threshold bits */
2543 prev |= threshold; /* set the threshold */
2544
2545 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_FIFO_CTRL, (uint8_t *)&prev, 1); /* write config */
2546}
2547
2559uint8_t l3gd20h_get_fifo_threshold(l3gd20h_handle_t *handle, uint8_t *threshold)
2560{
2561 uint8_t res, prev;
2562
2563 if (handle == NULL) /* check handle */
2564 {
2565 return 2; /* return error */
2566 }
2567 if (handle->inited != 1) /* check handle initialization */
2568 {
2569 return 3; /* return error */
2570 }
2571
2572 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_FIFO_CTRL, (uint8_t *)&prev, 1); /* read config */
2573 if (res != 0) /* check result */
2574 {
2575 handle->debug_print("l3gd20h: read fifo ctrl failed.\n"); /* read fifo ctrl failed */
2576
2577 return 1; /* return error */
2578 }
2579 prev &= (0x1F); /* get threshold bits */
2580 *threshold = prev; /* set threshold */
2581
2582 return 0; /* success return 0 */
2583}
2584
2596uint8_t l3gd20h_get_fifo_level(l3gd20h_handle_t *handle, uint8_t *level)
2597{
2598 uint8_t res, prev;
2599
2600 if (handle == NULL) /* check handle */
2601 {
2602 return 2; /* return error */
2603 }
2604 if (handle->inited != 1) /* check handle initialization */
2605 {
2606 return 3; /* return error */
2607 }
2608
2609 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_FIFO_SRC, (uint8_t *)&prev, 1); /* read config */
2610 if (res != 0) /* check result */
2611 {
2612 handle->debug_print("l3gd20h: read fifo src failed.\n"); /* read fifo src failed */
2613
2614 return 1; /* return error */
2615 }
2616 prev &= (0x1F); /* get level bits */
2617 *level = prev; /* get level */
2618
2619 return 0; /* success return 0 */
2620}
2621
2634uint8_t l3gd20h_set_interrupt_event(l3gd20h_handle_t *handle, l3gd20h_interrupt_event_t interrupt_event, l3gd20h_bool_t enable)
2635{
2636 uint8_t res, prev;
2637
2638 if (handle == NULL) /* check handle */
2639 {
2640 return 2; /* return error */
2641 }
2642 if (handle->inited != 1) /* check handle initialization */
2643 {
2644 return 3; /* return error */
2645 }
2646
2647 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_IG_CFG, (uint8_t *)&prev, 1); /* read config */
2648 if (res != 0) /* check result */
2649 {
2650 handle->debug_print("l3gd20h: read interrupt cfg failed.\n"); /* read interrupt cfg failed */
2651
2652 return 1; /* return error */
2653 }
2654 prev &= ~(1 << interrupt_event); /* clear event bit */
2655 prev |= enable << interrupt_event; /* set event bit */
2656
2657 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_IG_CFG, (uint8_t *)&prev, 1); /* write config */
2658}
2659
2672uint8_t l3gd20h_get_interrupt_event(l3gd20h_handle_t *handle, l3gd20h_interrupt_event_t interrupt_event, l3gd20h_bool_t *enable)
2673{
2674 uint8_t res, prev;
2675
2676 if (handle == NULL) /* check handle */
2677 {
2678 return 2; /* return error */
2679 }
2680 if (handle->inited != 1) /* check handle initialization */
2681 {
2682 return 3; /* return error */
2683 }
2684
2685 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_IG_CFG, (uint8_t *)&prev, 1); /* read config */
2686 if (res != 0) /* check result */
2687 {
2688 handle->debug_print("l3gd20h: read interrupt cfg failed.\n"); /* read interrupt cfg failed */
2689
2690 return 1; /* return error */
2691 }
2692 prev &= (1 << interrupt_event); /* get interrupt bit */
2693 *enable = (l3gd20h_bool_t)(prev >> interrupt_event); /* get interrupt */
2694
2695 return 0; /* success return 0 */
2696}
2697
2709uint8_t l3gd20h_get_interrupt_source(l3gd20h_handle_t *handle, uint8_t *src)
2710{
2711 uint8_t res;
2712
2713 if (handle == NULL) /* check handle */
2714 {
2715 return 2; /* return error */
2716 }
2717 if (handle->inited != 1) /* check handle initialization */
2718 {
2719 return 3; /* return error */
2720 }
2721
2722 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_IG_SRC, (uint8_t *)src, 1); /* read config */
2723 if (res != 0) /* check result */
2724 {
2725 handle->debug_print("l3gd20h: read interrupt source failed.\n"); /* read interrupt source failed */
2726
2727 return 1; /* return error */
2728 }
2729
2730 return 0; /* success return 0 */
2731}
2732
2745uint8_t l3gd20h_set_x_interrupt_threshold(l3gd20h_handle_t *handle, uint16_t threshold)
2746{
2747 uint8_t res;
2748 uint8_t buf[2];
2749
2750 if (handle == NULL) /* check handle */
2751 {
2752 return 2; /* return error */
2753 }
2754 if (handle->inited != 1) /* check handle initialization */
2755 {
2756 return 3; /* return error */
2757 }
2758 if (threshold > 0x8000U) /* check the threshold */
2759 {
2760 handle->debug_print("l3gd20h: threshold is invalid.\n"); /* threshold is invalid */
2761
2762 return 4; /* return error */
2763 }
2764
2765 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_IG_THS_XH, (uint8_t *)buf, 1); /* read x interrupt threshold */
2766 if (res != 0) /* check result */
2767 {
2768 handle->debug_print("l3gd20h: read x interrupt threshold failed.\n"); /* read x interrupt threshold failed */
2769
2770 return 1; /* return error */
2771 }
2772 buf[0] = (buf[0] & 0x80) | ((threshold >> 8) & 0x7F); /* set threshold high */
2773 buf[1] = (threshold) & 0xFF; /* set threshold low*/
2774
2775 res = a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_IG_THS_XH, (uint8_t *)&buf[0], 1); /* write config */
2776 if (res != 0) /* check result */
2777 {
2778 handle->debug_print("l3gd20h: write x interrupt high threshold failed.\n"); /* write x interrupt high threshold failed */
2779
2780 return 1; /* return error */
2781 }
2782
2783 res = a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_IG_THS_XL, (uint8_t *)&buf[1], 1); /* write config */
2784 if (res != 0) /* check result */
2785 {
2786 handle->debug_print("l3gd20h: write x interrupt low threshold failed.\n"); /* write x interrupt low threshold failed */
2787
2788 return 1; /* return error */
2789 }
2790
2791 return 0; /* success return 0 */
2792}
2793
2805uint8_t l3gd20h_get_x_interrupt_threshold(l3gd20h_handle_t *handle, uint16_t *threshold)
2806{
2807 uint8_t buf[2];
2808
2809 if (handle == NULL) /* check handle */
2810 {
2811 return 2; /* return error */
2812 }
2813 if (handle->inited != 1) /* check handle initialization */
2814 {
2815 return 3; /* return error */
2816 }
2817
2818 if (a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_IG_THS_XH, (uint8_t *)&buf[0], 1) != 0) /* read x interrupt high threshold */
2819 {
2820 handle->debug_print("l3gd20h: read x interrupt high threshold failed.\n"); /* read x interrupt high threshold failed */
2821
2822 return 1; /* return error */
2823 }
2824 if (a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_IG_THS_XL, (uint8_t *)&buf[1], 1) != 0) /* read x interrupt low threshold */
2825 {
2826 handle->debug_print("l3gd20h: read x interrupt low threshold failed.\n"); /* read x interrupt low threshold failed */
2827
2828 return 1; /* return error */
2829 }
2830 *threshold = (uint16_t)((uint16_t)buf[0] << 8) | buf[1]; /* get the threshold */
2831 *threshold &= ~(1 << 15); /* clear the 15th bit */
2832
2833 return 0; /* success return 0 */
2834}
2835
2848uint8_t l3gd20h_set_y_interrupt_threshold(l3gd20h_handle_t *handle, uint16_t threshold)
2849{
2850 uint8_t res;
2851 uint8_t buf[2];
2852
2853 if (handle == NULL) /* check handle */
2854 {
2855 return 2; /* return error */
2856 }
2857 if (handle->inited != 1) /* check handle initialization */
2858 {
2859 return 3; /* return error */
2860 }
2861 if (threshold > 0x8000U) /* check the threshold */
2862 {
2863 handle->debug_print("l3gd20h: threshold is invalid.\n"); /* threshold is invalid */
2864
2865 return 4; /* return error */
2866 }
2867
2868 buf[0] = (threshold >> 8) & 0xFF; /* set the high threshold */
2869 buf[1] = (threshold) & 0xFF; /* set the low threshold */
2870
2871 res = a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_IG_THS_YH, (uint8_t *)&buf[0], 1); /* write the config */
2872 if (res != 0) /* check result */
2873 {
2874 handle->debug_print("l3gd20h: write y interrupt high threshold failed.\n"); /* write y interrupt high threshold failed */
2875
2876 return 1; /* return error */
2877 }
2878 res = a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_IG_THS_YL, (uint8_t *)&buf[1], 1); /* write the config */
2879 if (res != 0) /* check result */
2880 {
2881 handle->debug_print("l3gd20h: write y interrupt low threshold failed.\n"); /* write y interrupt low threshold failed */
2882
2883 return 1; /* return error */
2884 }
2885
2886 return 0; /* success return 0 */
2887}
2888
2900uint8_t l3gd20h_get_y_interrupt_threshold(l3gd20h_handle_t *handle, uint16_t *threshold)
2901{
2902 uint8_t buf[2];
2903
2904 if (handle == NULL) /* check handle */
2905 {
2906 return 2; /* return error */
2907 }
2908 if (handle->inited != 1) /* check handle initialization */
2909 {
2910 return 3; /* return error */
2911 }
2912
2913 if (a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_IG_THS_YH, (uint8_t *)&buf[0], 1) != 0) /* read y interrupt high threshold */
2914 {
2915 handle->debug_print("l3gd20h: read y interrupt high threshold failed.\n"); /* read y interrupt high threshold failed */
2916
2917 return 1; /* return error */
2918 }
2919 if (a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_IG_THS_YL, (uint8_t *)&buf[1], 1) != 0) /* read y interrupt low threshold */
2920 {
2921 handle->debug_print("l3gd20h: read y interrupt low threshold failed.\n"); /* read y interrupt low threshold failed */
2922
2923 return 1; /* return error */
2924 }
2925 *threshold = (uint16_t)(buf[0] << 8) | buf[1]; /* get the threshold */
2926 *threshold &= ~(1 << 15); /* clear the 15th bit */
2927
2928 return 0; /* success return 0 */
2929}
2930
2943uint8_t l3gd20h_set_z_interrupt_threshold(l3gd20h_handle_t *handle, uint16_t threshold)
2944{
2945 uint8_t res;
2946 uint8_t buf[2];
2947
2948 if (handle == NULL) /* check handle */
2949 {
2950 return 2; /* return error */
2951 }
2952 if (handle->inited != 1) /* check handle initialization */
2953 {
2954 return 3; /* return error */
2955 }
2956 if (threshold > 0x8000U) /* check the threshold */
2957 {
2958 handle->debug_print("l3gd20h: threshold is invalid.\n"); /* threshold is invalid */
2959
2960 return 4; /* return error */
2961 }
2962
2963 buf[0] = (threshold >> 8) & 0xFF; /* set the high threshold */
2964 buf[1] = (threshold) & 0xFF; /* set the low threshold */
2965
2966 res = a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_IG_THS_ZH, (uint8_t *)&buf[0], 1); /* write config */
2967 if (res != 0) /* check result */
2968 {
2969 handle->debug_print("l3gd20h: write z interrupt high threshold failed.\n"); /* write z interrupt high threshold failed */
2970
2971 return 1; /* return error */
2972 }
2973 res = a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_IG_THS_ZL, (uint8_t *)&buf[1], 1); /* write config */
2974 if (res != 0) /* check result */
2975 {
2976 handle->debug_print("l3gd20h: write z interrupt low threshold failed.\n"); /* write z interrupt low threshold failed */
2977
2978 return 1; /* return error */
2979 }
2980
2981 return 0; /* success return 0 */
2982}
2983
2995uint8_t l3gd20h_get_z_interrupt_threshold(l3gd20h_handle_t *handle, uint16_t *threshold)
2996{
2997 uint8_t buf[2];
2998
2999 if (handle == NULL) /* check handle */
3000 {
3001 return 2; /* return error */
3002 }
3003 if (handle->inited != 1) /* check handle initialization */
3004 {
3005 return 3; /* return error */
3006 }
3007
3008 if (a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_IG_THS_ZH, (uint8_t *)&buf[0], 1) != 0) /* read the config */
3009 {
3010 handle->debug_print("l3gd20h: read z interrupt high threshold failed.\n"); /* read z interrupt high threshold failed */
3011
3012 return 1; /* return error */
3013 }
3014 if (a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_IG_THS_ZL, (uint8_t *)&buf[1], 1) != 0) /* read the config */
3015 {
3016 handle->debug_print("l3gd20h: read z interrupt low threshold failed.\n"); /* read z interrupt low threshold failed */
3017
3018 return 1; /* return error */
3019 }
3020 *threshold = (uint16_t)((uint16_t)buf[0] << 8) | buf[1]; /* get the threshold */
3021 *threshold &= ~(1 << 15); /* clear the 15th bit */
3022
3023 return 0; /* success return 0 */
3024}
3025
3037uint8_t l3gd20h_set_counter_mode(l3gd20h_handle_t *handle, l3gd20h_counter_mode_t counter_mode)
3038{
3039 uint8_t res, prev;
3040
3041 if (handle == NULL) /* check handle */
3042 {
3043 return 2; /* return error */
3044 }
3045 if (handle->inited != 1) /* check handle initialization */
3046 {
3047 return 3; /* return error */
3048 }
3049
3050 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_IG_THS_XH, (uint8_t *)&prev, 1); /* read config */
3051 if (res != 0) /* check result */
3052 {
3053 handle->debug_print("l3gd20h: read x interrupt threshold failed.\n"); /* read x interrupt threshold failed */
3054
3055 return 1; /* return error */
3056 }
3057 prev &= ~(1 << 7); /* clear the counter mode bit */
3058 prev |= counter_mode << 7; /* set the counter mode */
3059
3060 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_IG_THS_XH, (uint8_t *)&prev, 1); /* write config */
3061}
3062
3074uint8_t l3gd20h_get_counter_mode(l3gd20h_handle_t *handle, l3gd20h_counter_mode_t *counter_mode)
3075{
3076 uint8_t res, prev;
3077
3078 if (handle == NULL) /* check handle */
3079 {
3080 return 2; /* return error */
3081 }
3082 if (handle->inited != 1) /* check handle initialization */
3083 {
3084 return 3; /* return error */
3085 }
3086
3087 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_IG_THS_XH, (uint8_t *)&prev, 1); /* read config */
3088 if (res != 0) /* check result */
3089 {
3090 handle->debug_print("l3gd20h: read x interrupt threshold failed.\n"); /* read x interrupt threshold failed */
3091
3092 return 1; /* return error */
3093 }
3094 prev &= (1 << 7); /* get the counter mode bit */
3095 *counter_mode = (l3gd20h_counter_mode_t)(prev >> 7); /* get the counter mode */
3096
3097 return 0; /* success return 0 */
3098}
3099
3111uint8_t l3gd20h_set_wait(l3gd20h_handle_t *handle, l3gd20h_bool_t enable)
3112{
3113 uint8_t res, prev;
3114
3115 if (handle == NULL) /* check handle */
3116 {
3117 return 2; /* return error */
3118 }
3119 if (handle->inited != 1) /* check handle initialization */
3120 {
3121 return 3; /* return error */
3122 }
3123
3124 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_IG_DURATION, (uint8_t *)&prev, 1); /* read config */
3125 if (res != 0) /* check result */
3126 {
3127 handle->debug_print("l3gd20h: read duration failed.\n"); /* read duration failed */
3128
3129 return 1; /* return error */
3130 }
3131 prev &= ~(1 << 7); /* clear enable bit */
3132 prev |= enable << 7; /* set enable */
3133
3134 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_IG_DURATION, (uint8_t *)&prev, 1); /* write config */
3135}
3136
3148uint8_t l3gd20h_get_wait(l3gd20h_handle_t *handle, l3gd20h_bool_t *enable)
3149{
3150 uint8_t res, prev;
3151
3152 if (handle == NULL) /* check handle */
3153 {
3154 return 2; /* return error */
3155 }
3156 if (handle->inited != 1) /* check handle initialization */
3157 {
3158 return 3; /* return error */
3159 }
3160
3161 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_IG_DURATION, (uint8_t *)&prev, 1); /* read config */
3162 if (res != 0) /* check result */
3163 {
3164 handle->debug_print("l3gd20h: read duration failed.\n"); /* read duration failed */
3165
3166 return 1; /* return error */
3167 }
3168 prev &= (1 << 7); /* get the wait bit */
3169 *enable = (l3gd20h_bool_t)(prev >> 7); /* get bool */
3170
3171 return 0; /* success return 0 */
3172}
3173
3185uint8_t l3gd20h_set_duration(l3gd20h_handle_t *handle, uint8_t duration)
3186{
3187 uint8_t res, prev;
3188
3189 if (handle == NULL) /* check handle */
3190 {
3191 return 2; /* return error */
3192 }
3193 if (handle->inited != 1) /* check handle initialization */
3194 {
3195 return 3; /* return error */
3196 }
3197 if (duration > 0x7F) /* check the duration */
3198 {
3199 handle->debug_print("l3gd20h: duration is over 0x7F.\n"); /* duration is over 0x7F */
3200
3201 return 1; /* return error */
3202 }
3203
3204 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_IG_DURATION, (uint8_t *)&prev, 1); /* read config */
3205 if (res != 0) /* check result */
3206 {
3207 handle->debug_print("l3gd20h: read duration failed.\n"); /* read duration failed */
3208
3209 return 1; /* return error */
3210 }
3211 prev |= duration & 0x7F; /* set the duration */
3212
3213 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_IG_DURATION, (uint8_t *)&prev, 1); /* write config */
3214}
3215
3227uint8_t l3gd20h_get_duration(l3gd20h_handle_t *handle, uint8_t *duration)
3228{
3229 uint8_t res, prev;
3230
3231 if (handle == NULL) /* check handle */
3232 {
3233 return 2; /* return error */
3234 }
3235 if (handle->inited != 1) /* check handle initialization */
3236 {
3237 return 3; /* return error */
3238 }
3239
3240 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_IG_DURATION, (uint8_t *)&prev, 1); /* read config */
3241 if (res != 0) /* check result */
3242 {
3243 handle->debug_print("l3gd20h: read duration failed.\n"); /* read duration failed */
3244
3245 return 1; /* return error */
3246 }
3247 prev &= 0x7F; /* get duration bits */
3248 *duration = prev; /* get duration */
3249
3250 return 0; /* success return 0 */
3251}
3252
3264uint8_t l3gd20h_set_data_ready_active_level(l3gd20h_handle_t *handle, l3gd20h_interrupt_active_level_t level)
3265{
3266 uint8_t res, prev;
3267
3268 if (handle == NULL) /* check handle */
3269 {
3270 return 2; /* return error */
3271 }
3272 if (handle->inited != 1) /* check handle initialization */
3273 {
3274 return 3; /* return error */
3275 }
3276
3277 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_LOW_ODR, (uint8_t *)&prev, 1); /* read config */
3278 if (res != 0) /* check result */
3279 {
3280 handle->debug_print("l3gd20h: read low odr failed.\n"); /* read low odr failed */
3281
3282 return 1; /* return error */
3283 }
3284 prev &= ~(1 << 5); /* clear level bit */
3285 prev |= level << 5; /* set level */
3286
3287 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_LOW_ODR, (uint8_t *)&prev, 1); /* write config */
3288}
3289
3301uint8_t l3gd20h_get_data_ready_active_level(l3gd20h_handle_t *handle, l3gd20h_interrupt_active_level_t *level)
3302{
3303 uint8_t res, prev;
3304
3305 if (handle == NULL) /* check handle */
3306 {
3307 return 2; /* return error */
3308 }
3309 if (handle->inited != 1) /* check handle initialization */
3310 {
3311 return 3; /* return error */
3312 }
3313
3314 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_LOW_ODR, (uint8_t *)&prev, 1); /* read config */
3315 if (res != 0) /* check result */
3316 {
3317 handle->debug_print("l3gd20h: read low odr failed.\n"); /* return error */
3318
3319 return 1; /* return error */
3320 }
3321 prev &= (1 << 5); /* get pin level bit */
3322 *level = (l3gd20h_interrupt_active_level_t)(prev >> 5); /* get pin level */
3323
3324 return 0; /* success return 0 */
3325}
3326
3338uint8_t l3gd20h_set_iic(l3gd20h_handle_t *handle, l3gd20h_bool_t enable)
3339{
3340 uint8_t res, prev;
3341
3342 if (handle == NULL) /* check handle */
3343 {
3344 return 2; /* return error */
3345 }
3346 if (handle->inited != 1) /* check handle initialization */
3347 {
3348 return 3; /* return error */
3349 }
3350
3351 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_LOW_ODR, (uint8_t *)&prev, 1); /* read config */
3352 if (res != 0) /* check result */
3353 {
3354 handle->debug_print("l3gd20h: read low odr failed.\n"); /* read low odr failed */
3355
3356 return 1; /* return error */
3357 }
3358 prev &= ~(1 << 3); /* clear enable bit */
3359 prev |= enable << 3; /* set enable */
3360
3361 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_LOW_ODR, (uint8_t *)&prev, 1); /* write config */
3362}
3363
3375uint8_t l3gd20h_get_iic(l3gd20h_handle_t *handle, l3gd20h_bool_t *enable)
3376{
3377 uint8_t res, prev;
3378
3379 if (handle == NULL) /* check handle */
3380 {
3381 return 2; /* return error */
3382 }
3383 if (handle->inited != 1) /* check handle initialization */
3384 {
3385 return 3; /* return error */
3386 }
3387
3388 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_LOW_ODR, (uint8_t *)&prev, 1); /* read config */
3389 if (res != 0) /* check result */
3390 {
3391 handle->debug_print("l3gd20h: read low odr failed.\n"); /* read low odr failed */
3392
3393 return 1; /* return error */
3394 }
3395 prev &= (1 << 3); /* get enable bit */
3396 *enable = (l3gd20h_bool_t)(prev >> 3); /* get bool */
3397
3398 return 0; /* success return 0 */
3399}
3400
3411uint8_t l3gd20h_soft_reset(l3gd20h_handle_t *handle)
3412{
3413 uint8_t res, prev;
3414
3415 if (handle == NULL) /* check handle */
3416 {
3417 return 2; /* return error */
3418 }
3419 if (handle->inited != 1) /* check handle initialization */
3420 {
3421 return 3; /* return error */
3422 }
3423
3424 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_LOW_ODR, (uint8_t *)&prev, 1); /* read config */
3425 if (res != 0) /* check result */
3426 {
3427 handle->debug_print("l3gd20h: read low odr failed.\n"); /* read low odr failed */
3428
3429 return 1; /* return error */
3430 }
3431 prev &= ~(1 << 2); /* clear reset bit */
3432 prev |= 1 << 2; /* set reset bit */
3433
3434 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_LOW_ODR, (uint8_t *)&prev, 1); /* write config */
3435}
3436
3449uint8_t l3gd20h_interrupt_threshold_convert_to_register(l3gd20h_handle_t *handle, float dps, uint16_t *reg)
3450{
3451 uint8_t range, prev;
3452
3453 if (handle == NULL) /* check handle */
3454 {
3455 return 2; /* return error */
3456 }
3457 if (handle->inited != 1) /* check handle initialization */
3458 {
3459 return 3; /* return error */
3460 }
3461
3462 if (a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL4, (uint8_t *)&prev, 1) != 0) /* read config */
3463 {
3464 handle->debug_print("l3gd20h: read ctrl4 failed.\n"); /* read ctrl4 failed */
3465
3466 return 1; /* return error */
3467 }
3468 range = (prev & (3 << 4)) >> 4; /* get range */
3469 if (range == 0)
3470 {
3471 *reg = (uint16_t)(dps * 1000.0f / 8.75f); /* convert */
3472 }
3473 else if (range == 1)
3474 {
3475 *reg = (uint16_t)(dps * 1000.0f / 17.50f); /* convert */
3476 }
3477 else
3478 {
3479 *reg = (uint16_t)(dps * 1000.0f / 70.0f); /* convert */
3480 }
3481
3482 return 0; /* success return 0 */
3483}
3484
3497uint8_t l3gd20h_interrupt_threshold_convert_to_data(l3gd20h_handle_t *handle, uint16_t reg, float *dps)
3498{
3499 uint8_t range, prev;
3500
3501 if (handle == NULL) /* check handle */
3502 {
3503 return 2; /* return error */
3504 }
3505 if (handle->inited != 1) /* check handle initialization */
3506 {
3507 return 3; /* return error */
3508 }
3509
3510 if (a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL4, (uint8_t *)&prev, 1) != 0) /* read config */
3511 {
3512 handle->debug_print("l3gd20h: read ctrl4 failed.\n"); /* read ctrl4 failed */
3513
3514 return 1; /* return error */
3515 }
3516 range = (prev & (3 << 4)) >> 4; /* get range */
3517 if (range == 0)
3518 {
3519 *dps = (float)(reg * 8.75f / 1000.0f); /* convert */
3520 }
3521 else if (range == 1)
3522 {
3523 *dps = (float)(reg * 17.50f / 1000.0f); /* convert */
3524 }
3525 else
3526 {
3527 *dps = (float)(reg * 70.0f / 1000.0f); /* convert */
3528 }
3529
3530 return 0; /* success return 0 */
3531}
3532
3544uint8_t l3gd20h_irq_handler(l3gd20h_handle_t *handle, uint8_t num)
3545{
3546 uint8_t res, prev;
3547
3548 if (handle == NULL) /* check handle */
3549 {
3550 return 2; /* return error */
3551 }
3552 if (handle->inited != 1) /* check handle initialization */
3553 {
3554 return 3; /* return error */
3555 }
3556
3557 if (num == 1) /* interrupt 1 */
3558 {
3559 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_IG_SRC, (uint8_t *)&prev, 1); /* read config */
3560 if (res != 0) /* check result */
3561 {
3562 handle->debug_print("l3gd20h: read interrupt source failed.\n"); /* read interrupt source failed */
3563
3564 return 1; /* return error */
3565 }
3566 if ((prev & (1 << 6)) != 0) /* check active */
3567 {
3568 if (handle->receive_callback != NULL) /* receive callback is valid */
3569 {
3570 handle->receive_callback(L3GD20H_INTERRUPT1_INTERRUPT_ACTIVE); /* run receive callback */
3571 }
3572 }
3573 if ((prev & (1 << 5)) != 0) /* check z high */
3574 {
3575 if (handle->receive_callback != NULL) /* receive callback is valid */
3576 {
3577 handle->receive_callback(L3GD20H_INTERRUPT1_Z_HIGH); /* run receive callback */
3578 }
3579 }
3580 if ((prev & (1 << 4)) != 0) /* check z low */
3581 {
3582 if (handle->receive_callback != NULL) /* receive callback is valid */
3583 {
3584 handle->receive_callback(L3GD20H_INTERRUPT1_Z_LOW); /* run receive callback */
3585 }
3586 }
3587 if ((prev & (1 << 3)) != 0) /* check y high */
3588 {
3589 if (handle->receive_callback != NULL) /* receive callback is valid */
3590 {
3591 handle->receive_callback(L3GD20H_INTERRUPT1_Y_HIGH); /* run receive callback */
3592 }
3593 }
3594 if ((prev & (1 << 2)) != 0) /* check y low */
3595 { /* check y low */
3596 if (handle->receive_callback != NULL) /* receive callback is valid */
3597 {
3598 handle->receive_callback(L3GD20H_INTERRUPT1_Y_LOW); /* run receive callback */
3599 }
3600 }
3601 if ((prev & (1 << 1)) != 0) /* check x high */
3602 {
3603 if (handle->receive_callback != NULL) /* receive callback is valid */
3604 {
3605 handle->receive_callback(L3GD20H_INTERRUPT1_X_HIGH); /* run receive callback */
3606 }
3607 }
3608 if ((prev & (1 << 0)) != 0) /* check x low */
3609 {
3610 if (handle->receive_callback != NULL) /* receive callback is valid */
3611 {
3612 handle->receive_callback(L3GD20H_INTERRUPT1_X_LOW); /* run receive callback */
3613 }
3614 }
3615
3616 return 0; /* success return 0 */
3617 }
3618 else if (num == 2) /* interrupt 2 */
3619 {
3620 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_STATUS, (uint8_t *)&prev, 1); /* read config */
3621 if (res != 0) /* check result */
3622 {
3623 handle->debug_print("l3gd20h: read status failed.\n"); /* read status failed */
3624
3625 return 1; /* return error */
3626 }
3627 if ((prev & (1 << L3GD20H_STATUS_XYZ_OVERRUN)) != 0) /* check status xyz overrun */
3628 {
3629 if (handle->receive_callback != NULL) /* receive callback is valid */
3630 {
3631 handle->receive_callback(L3GD20H_INTERRUPT2_XYZ_OVERRUN); /* run receive callback */
3632 }
3633 }
3634 if ((prev & (1 << L3GD20H_STATUS_Z_OVERRUN)) != 0) /* check status z overrun */
3635 {
3636 if (handle->receive_callback != NULL) /* receive callback is valid */
3637 {
3638 handle->receive_callback(L3GD20H_INTERRUPT2_Z_OVERRUN); /* run receive callback */
3639 }
3640 }
3641 if ((prev & (1 << L3GD20H_STATUS_Y_OVERRUN)) != 0) /* check status y overrun */
3642 {
3643 if (handle->receive_callback != NULL) /* receive callback is valid */
3644 {
3645 handle->receive_callback(L3GD20H_INTERRUPT2_Y_OVERRUN); /* run receive callback */
3646 }
3647 }
3648 if ((prev & (1 << L3GD20H_STATUS_X_OVERRUN)) != 0) /* check status x overrun */
3649 {
3650 if (handle->receive_callback != NULL) /* receive callback is valid */
3651 {
3652 handle->receive_callback(L3GD20H_INTERRUPT2_X_OVERRUN); /* run receive callback */
3653 }
3654 }
3655 if ((prev & (1 << L3GD20H_STATUS_XYZ_DATA_READY)) != 0) /* check status xyz data ready */
3656 {
3657 if (handle->receive_callback != NULL) /* receive callback is valid */
3658 {
3659 handle->receive_callback(L3GD20H_INTERRUPT2_XYZ_DATA_READY); /* run receive callback */
3660 }
3661 }
3662 if ((prev & (1 << L3GD20H_STATUS_Z_DATA_READY)) != 0) /* check status z data ready */
3663 {
3664 if (handle->receive_callback != NULL) /* receive callback is valid */
3665 {
3666 handle->receive_callback(L3GD20H_INTERRUPT2_Z_DATA_READY); /* run receive callback */
3667 }
3668 }
3669 if ((prev & (1 << L3GD20H_STATUS_Y_DATA_READY)) != 0) /* check status y data ready */
3670 {
3671 if (handle->receive_callback != NULL) /* receive callback is valid */
3672 {
3673 handle->receive_callback(L3GD20H_INTERRUPT2_Y_DATA_READY); /* run receive callback */
3674 }
3675 }
3676 if ((prev & (1 << L3GD20H_STATUS_X_DATA_READY)) != 0) /* check status x data ready */
3677 {
3678 if (handle->receive_callback != NULL) /* receive callback is valid */
3679 {
3680 handle->receive_callback(L3GD20H_INTERRUPT2_X_DATA_READY); /* run receive callback */
3681 }
3682 }
3683
3684 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_FIFO_SRC, (uint8_t *)&prev, 1); /* read config */
3685 if (res != 0) /* check result */
3686 {
3687 handle->debug_print("l3gd20h: read fifo source failed.\n"); /* read fifo source failed*/
3688
3689 return 1; /* return error */
3690 }
3691 if ((prev & (1 << 7)) != 0) /* check fifo threshold */
3692 {
3693 if (handle->receive_callback != NULL) /* receive callback is valid */
3694 {
3695 handle->receive_callback(L3GD20H_INTERRUPT2_FIFO_THRESHOLD); /* run receive callback */
3696 }
3697 }
3698 if ((prev & (1 << 6)) != 0) /* check fifo overrun */
3699 {
3700 if (handle->receive_callback != NULL) /* receive callback is valid */
3701 {
3702 handle->receive_callback(L3GD20H_INTERRUPT2_FIFO_OVERRRUN); /* run receive callback */
3703 }
3704 }
3705 if ((prev & (1 << 5)) != 0) /* check fifo empty */
3706 {
3707 if (handle->receive_callback != NULL) /* receive callback is valid */
3708 {
3709 handle->receive_callback(L3GD20H_INTERRUPT2_FIFO_EMPTY); /* run receive callback */
3710 }
3711 }
3712
3713 return 0; /* success return 0 */
3714 }
3715 else
3716 {
3717 handle->debug_print("l3gd20h: interrupt number is invalid.\n"); /* interrupt number is invalid */
3718
3719 return 1; /* return error */
3720 }
3721}
3722
3734uint8_t l3gd20h_init(l3gd20h_handle_t *handle)
3735{
3736 uint8_t res, prev;
3737 uint8_t id;
3738
3739 if (handle == NULL) /* check handle */
3740 {
3741 return 2; /* return error */
3742 }
3743 if (handle->debug_print == NULL) /* check debug_print */
3744 {
3745 return 3; /* return error */
3746 }
3747 if (handle->iic_init == NULL) /* check iic_init */
3748 {
3749 handle->debug_print("l3gd20h: iic_init is null.\n"); /* iic_init is null */
3750
3751 return 3; /* return error */
3752 }
3753 if (handle->iic_deinit == NULL) /* check iic_deinit */
3754 {
3755 handle->debug_print("l3gd20h: iic_deinit is null.\n"); /* iic_deinit is null */
3756
3757 return 3; /* return error */
3758 }
3759 if (handle->iic_read == NULL) /* check iic_read */
3760 {
3761 handle->debug_print("l3gd20h: iic_read is null.\n"); /* iic_read is null */
3762
3763 return 3; /* return error */
3764 }
3765 if (handle->iic_write == NULL) /* check iic_write */
3766 {
3767 handle->debug_print("l3gd20h: iic_write is null.\n"); /* iic_write is null */
3768
3769 return 3; /* return error */
3770 }
3771 if (handle->spi_init == NULL) /* check spi_init */
3772 {
3773 handle->debug_print("l3gd20h: spi_init is null.\n"); /* spi_init is null */
3774
3775 return 3; /* return error */
3776 }
3777 if (handle->spi_deinit == NULL) /* check spi_deinit */
3778 {
3779 handle->debug_print("l3gd20h: spi_deinit is null.\n"); /* spi_deinit is null */
3780
3781 return 3; /* return error */
3782 }
3783 if (handle->spi_read == NULL) /* check spi_read */
3784 {
3785 handle->debug_print("l3gd20h: spi_read is null.\n"); /* spi_read is null */
3786
3787 return 3; /* return error */
3788 }
3789 if (handle->spi_write == NULL) /* check spi_write */
3790 {
3791 handle->debug_print("l3gd20h: spi_write is null.\n"); /* spi_write is null */
3792
3793 return 3; /* return error */
3794 }
3795 if (handle->delay_ms == NULL) /* check delay_ms */
3796 {
3797 handle->debug_print("l3gd20h: delay_ms is null.\n"); /* delay_ms is null */
3798
3799 return 3; /* return error */
3800 }
3801
3802 if (handle->iic_spi == L3GD20H_INTERFACE_IIC) /* iic interface */
3803 {
3804 if (handle->iic_init() != 0) /* initialize iic bus */
3805 {
3806 handle->debug_print("l3gd20h: iic init failed.\n"); /* iic init failed */
3807
3808 return 1; /* return error */
3809 }
3810 }
3811 else
3812 {
3813 if (handle->spi_init() != 0) /* initialize spi bus */
3814 {
3815 handle->debug_print("l3gd20h: spi init failed.\n"); /* spi init failed */
3816
3817 return 1; /* return error */
3818 }
3819 }
3820 if (a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_WHO_AM_I, (uint8_t *)&id, 1) != 0) /* read id */
3821 {
3822 handle->debug_print("l3gd20h: read id failed.\n"); /* read id failed */
3823 if (handle->iic_spi == L3GD20H_INTERFACE_IIC) /* if iic interface */
3824 {
3825 (void)handle->iic_deinit(); /* iic deinit */
3826 }
3827 else /* spi interface */
3828 {
3829 (void)handle->spi_deinit(); /* spi deinit */
3830 }
3831
3832 return 1; /* return error */
3833 }
3834 if (id != 0xD7) /* check id */
3835 {
3836 handle->debug_print("l3gd20h: id is invalid.\n"); /* id is invalid */
3837 if (handle->iic_spi == L3GD20H_INTERFACE_IIC) /* if iic interface */
3838 {
3839 (void)handle->iic_deinit(); /* iic deinit */
3840 }
3841 else
3842 {
3843 (void)handle->spi_deinit(); /* spi deinit */
3844 }
3845
3846 return 4; /* return error */
3847 }
3848
3849 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_LOW_ODR, (uint8_t *)&prev, 1); /* read config */
3850 if (res != 0) /* check result */
3851 {
3852 handle->debug_print("l3gd20h: read low odr failed.\n"); /* read low odr failed */
3853 if (handle->iic_spi == L3GD20H_INTERFACE_IIC) /* if iic interface */
3854 {
3855 (void)handle->iic_deinit(); /* iic deinit */
3856 }
3857 else
3858 {
3859 (void)handle->spi_deinit(); /* spi deinit */
3860 }
3861
3862 return 1; /* return error */
3863 }
3864 prev &= ~(1 << 2); /* clear reset bit */
3865 prev |= 1 << 2; /* set reset bit */
3866 res = a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_LOW_ODR, (uint8_t *)&prev, 1); /* write config */
3867 if (res != 0) /* check result */
3868 {
3869 handle->debug_print("l3gd20h: write low odr failed.\n"); /* write low odr failed */
3870 if (handle->iic_spi == L3GD20H_INTERFACE_IIC) /* if iic interface */
3871 {
3872 (void)handle->iic_deinit(); /* iic deinit */
3873 }
3874 else
3875 {
3876 (void)handle->spi_deinit(); /* spi deinit */
3877 }
3878
3879 return 1; /* return error */
3880 }
3881 handle->delay_ms(12); /* delay 12 ms */
3882 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_LOW_ODR, (uint8_t *)&prev, 1); /* read config */
3883 if (res != 0) /* check result */
3884 {
3885 handle->debug_print("l3gd20h: read low odr failed.\n"); /* read low odr failed */
3886 if (handle->iic_spi == L3GD20H_INTERFACE_IIC) /* if iic interface */
3887 {
3888 (void)handle->iic_deinit(); /* iic deinit */
3889 }
3890 else
3891 {
3892 (void)handle->spi_deinit(); /* spi deinit */
3893 }
3894
3895 return 1; /* return error */
3896 }
3897 if (((prev >> 2) & 0x01) != 0x0) /* check result */
3898 {
3899 handle->debug_print("l3gd20h: reset chip failed.\n"); /* reset chip failed */
3900 if (handle->iic_spi == L3GD20H_INTERFACE_IIC) /* if iic interface */
3901 {
3902 (void)handle->iic_deinit(); /* iic deinit */
3903 }
3904 else
3905 {
3906 (void)handle->spi_deinit(); /* spi deinit */
3907 }
3908
3909 return 1; /* return error */
3910 }
3911
3912 handle->inited = 1; /* flag finish initialization */
3913
3914 return 0; /* success return 0 */
3915}
3916
3928uint8_t l3gd20h_deinit(l3gd20h_handle_t *handle)
3929{
3930 uint8_t res, prev;
3931
3932 if (handle == NULL) /* check handle */
3933 {
3934 return 2; /* return error */
3935 }
3936 if (handle->inited != 1) /* check handle initialization */
3937 {
3938 return 3; /* return error */
3939 }
3940
3941 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL1, (uint8_t *)&prev, 1); /* read config */
3942 if (res != 0) /* check result */
3943 {
3944 handle->debug_print("l3gd20h: read ctrl1 failed.\n"); /* read ctrl1 failed */
3945
3946 return 4; /* return error */
3947 }
3948 prev &= ~(1 << 3); /* set power down bit */
3949 res = a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_CTRL1, (uint8_t *)&prev, 1); /* write config */
3950 if (res != 0) /* check result */
3951 {
3952 handle->debug_print("l3gd20h: write ctrl1 failed.\n"); /* write ctrl1 failed */
3953
3954 return 4; /* return error */
3955 }
3956 handle->inited = 0; /* flag close */
3957
3958 return 0; /* success return 0 */
3959}
3960
3975uint8_t l3gd20h_read(l3gd20h_handle_t *handle, int16_t (*raw)[3], float (*dps)[3], uint16_t *len)
3976{
3977 uint8_t res, prev;
3978 uint8_t mode, cnt, i;
3979 uint8_t ble, range, enable;
3980 uint8_t buf[32 * 6];
3981
3982 if (handle == NULL) /* check handle */
3983 {
3984 return 2; /* return error */
3985 }
3986 if (handle->inited != 1) /* check handle initialization */
3987 {
3988 return 3; /* return error */
3989 }
3990
3991 if ((*len) == 0) /* check length */
3992 {
3993 handle->debug_print("l3gd20h: length is zero.\n"); /* length is zero. */
3994
3995 return 4; /* return error */
3996 }
3997 if (a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_FIFO_CTRL, (uint8_t *)&prev, 1) != 0) /* read fifo ctrl */
3998 {
3999 handle->debug_print("l3gd20h: read fifo ctrl failed.\n"); /* read fifo ctrl failed */
4000
4001 return 1; /* return error */
4002 }
4003 mode = prev >> 5; /* get the mode */
4004 if (a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL5, (uint8_t *)&prev, 1) != 0) /* read ctrl5 */
4005 {
4006 handle->debug_print("l3gd20h: read ctrl5 failed.\n"); /* read ctrl5 failed */
4007
4008 return 1; /* return error */
4009 }
4010 enable = (prev & (1 << 6)) >> 6; /* get enable */
4011 if (a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL4, (uint8_t *)&prev, 1) != 0) /* get ctrl4 */
4012 {
4013 handle->debug_print("l3gd20h: read ctrl4 failed.\n"); /* read ctrl4 failed */
4014
4015 return 1; /* return error */
4016 }
4017 range = (prev & (3 << 4)) >> 4; /* get range */
4018 ble = (prev & (1 << 6)) >> 6; /* get big little endian */
4019 if ((mode && enable) != 0) /* fifo modes */
4020 {
4021 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_FIFO_SRC, (uint8_t *)&prev, 1); /* read fifo source */
4022 if (res != 0) /* check result */
4023 {
4024 handle->debug_print("l3gd20h: read fifo source failed.\n"); /* read fifo source failed */
4025
4026 return 1; /* return error */
4027 }
4028 cnt = prev & 0x1F; /* get counter */
4029 *len = ((*len) < cnt) ? (*len) : cnt; /* get the length */
4030 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_OUT_X_L, (uint8_t *)buf, 6 * (*len)); /* read all data */
4031 if (res != 0) /* check result */
4032 {
4033 handle->debug_print("l3gd20h: read data failed.\n"); /* read data failed */
4034
4035 return 1; /* return error */
4036 }
4037 for (i = 0; i < (*len); i++) /* get data */
4038 {
4039 if (ble == 0) /* little endian */
4040 {
4041 raw[i][0] = (int16_t)(((uint16_t)buf[1 + i * 6] << 8) | buf[0 + i * 6]); /* set x */
4042 raw[i][1] = (int16_t)(((uint16_t)buf[3 + i * 6] << 8) | buf[2 + i * 6]); /* set y */
4043 raw[i][2] = (int16_t)(((uint16_t)buf[5 + i * 6] << 8) | buf[4 + i * 6]); /* set z */
4044 }
4045 else /* big endian */
4046 {
4047 raw[i][0] = (int16_t)(((uint16_t)buf[0 + i * 6] << 8) | buf[1 + i * 6]); /* set x */
4048 raw[i][1] = (int16_t)(((uint16_t)buf[2 + i * 6] << 8) | buf[3 + i * 6]); /* set y */
4049 raw[i][2] = (int16_t)(((uint16_t)buf[4 + i * 6] << 8) | buf[5 + i * 6]); /* set z */
4050 }
4051 if (range == 0) /* ±245 dps */
4052 {
4053 dps[i][0] = (float)(raw[i][0]) * 8.75f / 1000.0f; /* set x */
4054 dps[i][1] = (float)(raw[i][1]) * 8.75f / 1000.0f; /* set y */
4055 dps[i][2] = (float)(raw[i][2]) * 8.75f / 1000.0f; /* set z */
4056 }
4057 else if (range == 1) /* ±500 dps */
4058 {
4059 dps[i][0] = (float)(raw[i][0]) * 17.5f / 1000.0f; /* set x */
4060 dps[i][1] = (float)(raw[i][1]) * 17.5f / 1000.0f; /* set y */
4061 dps[i][2] = (float)(raw[i][2]) * 17.5f / 1000.0f; /* set z */
4062 }
4063 else /* ±2000 dps */
4064 {
4065 dps[i][0] = (float)(raw[i][0]) * 70.0f / 1000.0f; /* set x */
4066 dps[i][1] = (float)(raw[i][1]) * 70.0f / 1000.0f; /* set y */
4067 dps[i][2] = (float)(raw[i][2]) * 70.0f / 1000.0f; /* set z */
4068 }
4069 }
4070 } /* bypass mode */
4071 else
4072 {
4073 *len = 1; /* set length */
4074 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_OUT_X_L, (uint8_t *)buf, 6); /* read data */
4075 if (res != 0) /* check result */
4076 {
4077 handle->debug_print("l3gd20h: read data failed.\n"); /* read data failed */
4078
4079 return 1; /* return error */
4080 }
4081 if (ble == 0) /* little endian */
4082 {
4083 raw[0][0] = (int16_t)(((uint16_t)buf[1] << 8) | buf[0]); /* set x */
4084 raw[0][1] = (int16_t)(((uint16_t)buf[3] << 8) | buf[2]); /* set y */
4085 raw[0][2] = (int16_t)(((uint16_t)buf[5] << 8) | buf[4]); /* set z */
4086 }
4087 else /* big endian */
4088 {
4089 raw[0][0] = (int16_t)(((uint16_t)buf[0] << 8) | buf[1]); /* set x */
4090 raw[0][1] = (int16_t)(((uint16_t)buf[2] << 8) | buf[3]); /* set y */
4091 raw[0][2] = (int16_t)(((uint16_t)buf[4] << 8) | buf[5]); /* set z */
4092 }
4093 if (range == 0) /* ±245 dps */
4094 {
4095 dps[0][0] = (float)(raw[0][0]) * 8.75f / 1000.0f; /* set x */
4096 dps[0][1] = (float)(raw[0][1]) * 8.75f / 1000.0f; /* set y */
4097 dps[0][2] = (float)(raw[0][2]) * 8.75f / 1000.0f; /* set z */
4098 }
4099 else if (range == 1) /* ±500 dps */
4100 {
4101 dps[0][0] = (float)(raw[0][0]) * 17.5f / 1000.0f; /* set x */
4102 dps[0][1] = (float)(raw[0][1]) * 17.5f / 1000.0f; /* set y */
4103 dps[0][2] = (float)(raw[0][2]) * 17.5f / 1000.0f; /* set z */
4104 }
4105 else /* ±2000 dps */
4106 {
4107 dps[0][0] = (float)(raw[0][0]) * 70.0f / 1000.0f; /* set x */
4108 dps[0][1] = (float)(raw[0][1]) * 70.0f / 1000.0f; /* set y */
4109 dps[0][2] = (float)(raw[0][2]) * 70.0f / 1000.0f; /* set z */
4110 }
4111 }
4112
4113 return 0; /* success return 0 */
4114}
4115
4129uint8_t l3gd20h_set_reg(l3gd20h_handle_t *handle, uint8_t reg, uint8_t *buf, uint16_t len)
4130{
4131 if (handle == NULL) /* check handle */
4132 {
4133 return 2; /* return error */
4134 }
4135 if (handle->inited != 1) /* check handle initialization */
4136 {
4137 return 3; /* return error */
4138 }
4139
4140 return a_l3gd20h_iic_spi_write(handle, reg, buf, len); /* write data */
4141}
4142
4156uint8_t l3gd20h_get_reg(l3gd20h_handle_t *handle, uint8_t reg, uint8_t *buf, uint16_t len)
4157{
4158 if (handle == NULL) /* check handle */
4159 {
4160 return 2; /* return error */
4161 }
4162 if (handle->inited != 1) /* check handle initialization */
4163 {
4164 return 3; /* return error */
4165 }
4166
4167 return a_l3gd20h_iic_spi_read(handle, reg, buf, len); /* read data */
4168}
4169
4178uint8_t l3gd20h_info(l3gd20h_info_t *info)
4179{
4180 if (info == NULL) /* check handle */
4181 {
4182 return 2; /* return error */
4183 }
4184
4185 memset(info, 0, sizeof(l3gd20h_info_t)); /* initialize l3gd20h info structure */
4186 strncpy(info->chip_name, CHIP_NAME, 32); /* copy chip name */
4187 strncpy(info->manufacturer_name, MANUFACTURER_NAME, 32); /* copy manufacturer name */
4188 strncpy(info->interface, "IIC SPI", 8); /* copy interface name */
4189 info->supply_voltage_min_v = SUPPLY_VOLTAGE_MIN; /* set minimal supply voltage */
4190 info->supply_voltage_max_v = SUPPLY_VOLTAGE_MAX; /* set maximum supply voltage */
4191 info->max_current_ma = MAX_CURRENT; /* set maximum current */
4192 info->temperature_max = TEMPERATURE_MAX; /* set minimal temperature */
4193 info->temperature_min = TEMPERATURE_MIN; /* set maximum temperature */
4194 info->driver_version = DRIVER_VERSION; /* set driver version */
4195
4196 return 0; /* success return 0 */
4197}
L3GD20H_REG_WHO_AM_I
#define L3GD20H_REG_WHO_AM_I
chip register definition
Definition driver_l3gd20h.c:55
L3GD20H_REG_REFERENCE
#define L3GD20H_REG_REFERENCE
Definition driver_l3gd20h.c:61
L3GD20H_REG_IG_CFG
#define L3GD20H_REG_IG_CFG
Definition driver_l3gd20h.c:72
L3GD20H_REG_CTRL4
#define L3GD20H_REG_CTRL4
Definition driver_l3gd20h.c:59
L3GD20H_REG_CTRL2
#define L3GD20H_REG_CTRL2
Definition driver_l3gd20h.c:57
L3GD20H_REG_FIFO_SRC
#define L3GD20H_REG_FIFO_SRC
Definition driver_l3gd20h.c:71
MAX_CURRENT
#define MAX_CURRENT
Definition driver_l3gd20h.c:47
L3GD20H_REG_CTRL3
#define L3GD20H_REG_CTRL3
Definition driver_l3gd20h.c:58
L3GD20H_REG_IG_THS_ZH
#define L3GD20H_REG_IG_THS_ZH
Definition driver_l3gd20h.c:78
L3GD20H_REG_IG_THS_YH
#define L3GD20H_REG_IG_THS_YH
Definition driver_l3gd20h.c:76
L3GD20H_REG_CTRL1
#define L3GD20H_REG_CTRL1
Definition driver_l3gd20h.c:56
L3GD20H_REG_FIFO_CTRL
#define L3GD20H_REG_FIFO_CTRL
Definition driver_l3gd20h.c:70
L3GD20H_REG_IG_SRC
#define L3GD20H_REG_IG_SRC
Definition driver_l3gd20h.c:73
SUPPLY_VOLTAGE_MAX
#define SUPPLY_VOLTAGE_MAX
Definition driver_l3gd20h.c:46
L3GD20H_REG_IG_THS_XH
#define L3GD20H_REG_IG_THS_XH
Definition driver_l3gd20h.c:74
TEMPERATURE_MAX
#define TEMPERATURE_MAX
Definition driver_l3gd20h.c:49
L3GD20H_REG_IG_THS_ZL
#define L3GD20H_REG_IG_THS_ZL
Definition driver_l3gd20h.c:79
MANUFACTURER_NAME
#define MANUFACTURER_NAME
Definition driver_l3gd20h.c:44
TEMPERATURE_MIN
#define TEMPERATURE_MIN
Definition driver_l3gd20h.c:48
L3GD20H_REG_OUT_X_L
#define L3GD20H_REG_OUT_X_L
Definition driver_l3gd20h.c:64
SUPPLY_VOLTAGE_MIN
#define SUPPLY_VOLTAGE_MIN
Definition driver_l3gd20h.c:45
L3GD20H_REG_OUT_TEMP
#define L3GD20H_REG_OUT_TEMP
Definition driver_l3gd20h.c:62
L3GD20H_REG_CTRL5
#define L3GD20H_REG_CTRL5
Definition driver_l3gd20h.c:60
L3GD20H_REG_IG_DURATION
#define L3GD20H_REG_IG_DURATION
Definition driver_l3gd20h.c:80
L3GD20H_REG_IG_THS_YL
#define L3GD20H_REG_IG_THS_YL
Definition driver_l3gd20h.c:77
L3GD20H_REG_IG_THS_XL
#define L3GD20H_REG_IG_THS_XL
Definition driver_l3gd20h.c:75
CHIP_NAME
#define CHIP_NAME
chip register definition
Definition driver_l3gd20h.c:43
DRIVER_VERSION
#define DRIVER_VERSION
Definition driver_l3gd20h.c:50
L3GD20H_REG_STATUS
#define L3GD20H_REG_STATUS
Definition driver_l3gd20h.c:63
L3GD20H_REG_LOW_ODR
#define L3GD20H_REG_LOW_ODR
Definition driver_l3gd20h.c:81
driver_l3gd20h.h
driver l3gd20h header file
l3gd20h_set_high_pass_filter
uint8_t l3gd20h_set_high_pass_filter(l3gd20h_handle_t *handle, l3gd20h_bool_t enable)
enable or disable high pass filter
Definition driver_l3gd20h.c:2107
l3gd20h_set_data_format
uint8_t l3gd20h_set_data_format(l3gd20h_handle_t *handle, l3gd20h_data_format_t data_format)
set the data format
Definition driver_l3gd20h.c:1515
l3gd20h_get_status
uint8_t l3gd20h_get_status(l3gd20h_handle_t *handle, uint8_t *status)
get the chip status
Definition driver_l3gd20h.c:2416
l3gd20h_info_t
struct l3gd20h_info_s l3gd20h_info_t
l3gd20h information structure definition
l3gd20h_set_block_data_update
uint8_t l3gd20h_set_block_data_update(l3gd20h_handle_t *handle, l3gd20h_bool_t enable)
enable or disable the block data update
Definition driver_l3gd20h.c:1441
l3gd20h_soft_reset
uint8_t l3gd20h_soft_reset(l3gd20h_handle_t *handle)
soft reset the device
Definition driver_l3gd20h.c:3411
l3gd20h_boot_t
l3gd20h_boot_t
l3gd20h boot enumeration definition
Definition driver_l3gd20h.h:224
l3gd20h_set_mode
uint8_t l3gd20h_set_mode(l3gd20h_handle_t *handle, l3gd20h_mode_t mode)
set the chip mode
Definition driver_l3gd20h.c:274
l3gd20h_get_boot
uint8_t l3gd20h_get_boot(l3gd20h_handle_t *handle, l3gd20h_boot_t *boot)
get the boot
Definition driver_l3gd20h.c:1922
l3gd20h_get_high_pass_filter_reference
uint8_t l3gd20h_get_high_pass_filter_reference(l3gd20h_handle_t *handle, uint8_t *value)
get the high pass filter reference
Definition driver_l3gd20h.c:2354
l3gd20h_get_axis
uint8_t l3gd20h_get_axis(l3gd20h_handle_t *handle, l3gd20h_axis_t axis, l3gd20h_bool_t *enable)
get the axis
Definition driver_l3gd20h.c:413
l3gd20h_get_mode
uint8_t l3gd20h_get_mode(l3gd20h_handle_t *handle, l3gd20h_mode_t *mode)
get the chip mode
Definition driver_l3gd20h.c:322
l3gd20h_get_out_selection
uint8_t l3gd20h_get_out_selection(l3gd20h_handle_t *handle, l3gd20h_selection_t *selection)
get the out selection
Definition driver_l3gd20h.c:2292
l3gd20h_info
uint8_t l3gd20h_info(l3gd20h_info_t *info)
get chip's information
Definition driver_l3gd20h.c:4178
l3gd20h_spi_wire_t
l3gd20h_spi_wire_t
l3gd20h spi wire enumeration definition
Definition driver_l3gd20h.h:215
l3gd20h_read_temperature
uint8_t l3gd20h_read_temperature(l3gd20h_handle_t *handle, int8_t *raw, float *temp)
read the temperature
Definition driver_l3gd20h.c:2380
l3gd20h_get_full_scale
uint8_t l3gd20h_get_full_scale(l3gd20h_handle_t *handle, l3gd20h_full_scale_t *full_scale)
get the full scale
Definition driver_l3gd20h.c:1626
l3gd20h_set_high_pass_filter_mode
uint8_t l3gd20h_set_high_pass_filter_mode(l3gd20h_handle_t *handle, l3gd20h_high_pass_filter_mode_t mode)
set the high pass filter mode
Definition driver_l3gd20h.c:701
l3gd20h_self_test_t
l3gd20h_self_test_t
l3gd20h self test type enumeration definition
Definition driver_l3gd20h.h:205
l3gd20h_set_rate_bandwidth
uint8_t l3gd20h_set_rate_bandwidth(l3gd20h_handle_t *handle, l3gd20h_lodr_odr_bw_t rate_bandwidth)
set the rate bandwidth
Definition driver_l3gd20h.c:450
l3gd20h_get_rate_bandwidth
uint8_t l3gd20h_get_rate_bandwidth(l3gd20h_handle_t *handle, l3gd20h_lodr_odr_bw_t *rate_bandwidth)
get the rate bandwidth
Definition driver_l3gd20h.c:509
l3gd20h_set_level_sensitive_latched
uint8_t l3gd20h_set_level_sensitive_latched(l3gd20h_handle_t *handle, l3gd20h_bool_t enable)
enable or disable the level sensitive latched
Definition driver_l3gd20h.c:1663
l3gd20h_read
uint8_t l3gd20h_read(l3gd20h_handle_t *handle, int16_t(*raw)[3], float(*dps)[3], uint16_t *len)
read the data
Definition driver_l3gd20h.c:3975
l3gd20h_set_out_selection
uint8_t l3gd20h_set_out_selection(l3gd20h_handle_t *handle, l3gd20h_selection_t selection)
set the out selection
Definition driver_l3gd20h.c:2255
l3gd20h_full_scale_t
l3gd20h_full_scale_t
l3gd20h full scale type enumeration definition
Definition driver_l3gd20h.h:195
l3gd20h_set_boot
uint8_t l3gd20h_set_boot(l3gd20h_handle_t *handle, l3gd20h_boot_t boot)
set the boot
Definition driver_l3gd20h.c:1885
l3gd20h_set_addr_pin
uint8_t l3gd20h_set_addr_pin(l3gd20h_handle_t *handle, l3gd20h_address_t addr_pin)
set the iic address pin
Definition driver_l3gd20h.c:230
l3gd20h_address_t
l3gd20h_address_t
l3gd20h address enumeration definition
Definition driver_l3gd20h.h:73
l3gd20h_set_interface
uint8_t l3gd20h_set_interface(l3gd20h_handle_t *handle, l3gd20h_interface_t interface)
set the chip interface
Definition driver_l3gd20h.c:188
l3gd20h_set_iic
uint8_t l3gd20h_set_iic(l3gd20h_handle_t *handle, l3gd20h_bool_t enable)
enable or disable the iic interface
Definition driver_l3gd20h.c:3338
l3gd20h_high_pass_filter_mode_t
l3gd20h_high_pass_filter_mode_t
l3gd20h high pass filter mode enumeration definition
Definition driver_l3gd20h.h:111
l3gd20h_get_level_trigger
uint8_t l3gd20h_get_level_trigger(l3gd20h_handle_t *handle, l3gd20h_bool_t *enable)
get the level trigger status
Definition driver_l3gd20h.c:664
l3gd20h_data_format_t
l3gd20h_data_format_t
l3gd20h data format enumeration definition
Definition driver_l3gd20h.h:186
l3gd20h_high_pass_filter_cut_off_frequency_t
l3gd20h_high_pass_filter_cut_off_frequency_t
l3gd20h high pass filter cut off frequency enumeration definition
Definition driver_l3gd20h.h:134
l3gd20h_set_high_pass_filter_reference
uint8_t l3gd20h_set_high_pass_filter_reference(l3gd20h_handle_t *handle, uint8_t value)
set the high pass filter reference
Definition driver_l3gd20h.c:2329
l3gd20h_deinit
uint8_t l3gd20h_deinit(l3gd20h_handle_t *handle)
close the chip
Definition driver_l3gd20h.c:3928
l3gd20h_get_addr_pin
uint8_t l3gd20h_get_addr_pin(l3gd20h_handle_t *handle, l3gd20h_address_t *addr_pin)
get the iic address pin
Definition driver_l3gd20h.c:251
l3gd20h_set_edge_trigger
uint8_t l3gd20h_set_edge_trigger(l3gd20h_handle_t *handle, l3gd20h_bool_t enable)
enable or disable the edge trigger
Definition driver_l3gd20h.c:552
l3gd20h_interface_t
l3gd20h_interface_t
l3gd20h interface enumeration definition
Definition driver_l3gd20h.h:64
l3gd20h_set_full_scale
uint8_t l3gd20h_set_full_scale(l3gd20h_handle_t *handle, l3gd20h_full_scale_t full_scale)
set the full scale
Definition driver_l3gd20h.c:1589
l3gd20h_axis_t
l3gd20h_axis_t
l3gd20h axis enumeration definition
Definition driver_l3gd20h.h:91
l3gd20h_irq_handler
uint8_t l3gd20h_irq_handler(l3gd20h_handle_t *handle, uint8_t num)
interrupt handler
Definition driver_l3gd20h.c:3544
l3gd20h_selection_t
l3gd20h_selection_t
l3gd20h selection enumeration definition
Definition driver_l3gd20h.h:233
l3gd20h_get_high_pass_filter_cut_off_frequency
uint8_t l3gd20h_get_high_pass_filter_cut_off_frequency(l3gd20h_handle_t *handle, l3gd20h_high_pass_filter_cut_off_frequency_t *frequency)
get the high pass filter cut off frequency
Definition driver_l3gd20h.c:812
l3gd20h_init
uint8_t l3gd20h_init(l3gd20h_handle_t *handle)
initialize the chip
Definition driver_l3gd20h.c:3734
l3gd20h_get_high_pass_filter
uint8_t l3gd20h_get_high_pass_filter(l3gd20h_handle_t *handle, l3gd20h_bool_t *enable)
get high pass filter status
Definition driver_l3gd20h.c:2144
l3gd20h_get_data_format
uint8_t l3gd20h_get_data_format(l3gd20h_handle_t *handle, l3gd20h_data_format_t *data_format)
get the data format
Definition driver_l3gd20h.c:1552
l3gd20h_get_interface
uint8_t l3gd20h_get_interface(l3gd20h_handle_t *handle, l3gd20h_interface_t *interface)
get the chip interface
Definition driver_l3gd20h.c:209
l3gd20h_get_high_pass_filter_mode
uint8_t l3gd20h_get_high_pass_filter_mode(l3gd20h_handle_t *handle, l3gd20h_high_pass_filter_mode_t *mode)
get the high pass filter mode
Definition driver_l3gd20h.c:738
l3gd20h_mode_t
l3gd20h_mode_t
l3gd20h mode enumeration definition
Definition driver_l3gd20h.h:101
l3gd20h_set_spi_wire
uint8_t l3gd20h_set_spi_wire(l3gd20h_handle_t *handle, l3gd20h_spi_wire_t spi_wire)
set the spi wire
Definition driver_l3gd20h.c:1811
l3gd20h_set_level_trigger
uint8_t l3gd20h_set_level_trigger(l3gd20h_handle_t *handle, l3gd20h_bool_t enable)
enable or disable the level trigger
Definition driver_l3gd20h.c:627
l3gd20h_get_block_data_update
uint8_t l3gd20h_get_block_data_update(l3gd20h_handle_t *handle, l3gd20h_bool_t *enable)
get the block data update status
Definition driver_l3gd20h.c:1478
l3gd20h_bool_t
l3gd20h_bool_t
l3gd20h bool enumeration definition
Definition driver_l3gd20h.h:82
l3gd20h_get_edge_trigger
uint8_t l3gd20h_get_edge_trigger(l3gd20h_handle_t *handle, l3gd20h_bool_t *enable)
get the edge trigger status
Definition driver_l3gd20h.c:589
l3gd20h_lodr_odr_bw_t
l3gd20h_lodr_odr_bw_t
l3gd20h low odr odr bw enumeration definition
Definition driver_l3gd20h.h:151
l3gd20h_get_spi_wire
uint8_t l3gd20h_get_spi_wire(l3gd20h_handle_t *handle, l3gd20h_spi_wire_t *spi_wire)
get the spi wire
Definition driver_l3gd20h.c:1848
l3gd20h_set_self_test
uint8_t l3gd20h_set_self_test(l3gd20h_handle_t *handle, l3gd20h_self_test_t self_test)
set the self test
Definition driver_l3gd20h.c:1737
l3gd20h_set_high_pass_filter_cut_off_frequency
uint8_t l3gd20h_set_high_pass_filter_cut_off_frequency(l3gd20h_handle_t *handle, l3gd20h_high_pass_filter_cut_off_frequency_t frequency)
set the high pass filter cut off frequency
Definition driver_l3gd20h.c:775
l3gd20h_set_axis
uint8_t l3gd20h_set_axis(l3gd20h_handle_t *handle, l3gd20h_axis_t axis, l3gd20h_bool_t enable)
set the axis
Definition driver_l3gd20h.c:375
l3gd20h_get_level_sensitive_latched
uint8_t l3gd20h_get_level_sensitive_latched(l3gd20h_handle_t *handle, l3gd20h_bool_t *enable)
get the level sensitive latched status
Definition driver_l3gd20h.c:1700
l3gd20h_get_iic
uint8_t l3gd20h_get_iic(l3gd20h_handle_t *handle, l3gd20h_bool_t *enable)
get the iic interface status
Definition driver_l3gd20h.c:3375
l3gd20h_get_self_test
uint8_t l3gd20h_get_self_test(l3gd20h_handle_t *handle, l3gd20h_self_test_t *self_test)
get the self test
Definition driver_l3gd20h.c:1774
l3gd20h_handle_t
struct l3gd20h_handle_s l3gd20h_handle_t
l3gd20h handle structure definition
L3GD20H_STATUS_XYZ_OVERRUN
@ L3GD20H_STATUS_XYZ_OVERRUN
Definition driver_l3gd20h.h:244
L3GD20H_STATUS_Y_DATA_READY
@ L3GD20H_STATUS_Y_DATA_READY
Definition driver_l3gd20h.h:250
L3GD20H_STATUS_Y_OVERRUN
@ L3GD20H_STATUS_Y_OVERRUN
Definition driver_l3gd20h.h:246
L3GD20H_STATUS_Z_OVERRUN
@ L3GD20H_STATUS_Z_OVERRUN
Definition driver_l3gd20h.h:245
L3GD20H_STATUS_X_DATA_READY
@ L3GD20H_STATUS_X_DATA_READY
Definition driver_l3gd20h.h:251
L3GD20H_STATUS_Z_DATA_READY
@ L3GD20H_STATUS_Z_DATA_READY
Definition driver_l3gd20h.h:249
L3GD20H_STATUS_XYZ_DATA_READY
@ L3GD20H_STATUS_XYZ_DATA_READY
Definition driver_l3gd20h.h:248
L3GD20H_STATUS_X_OVERRUN
@ L3GD20H_STATUS_X_OVERRUN
Definition driver_l3gd20h.h:247
L3GD20H_INTERFACE_IIC
@ L3GD20H_INTERFACE_IIC
Definition driver_l3gd20h.h:65
L3GD20H_MODE_SLEEP
@ L3GD20H_MODE_SLEEP
Definition driver_l3gd20h.h:104
l3gd20h_set_reg
uint8_t l3gd20h_set_reg(l3gd20h_handle_t *handle, uint8_t reg, uint8_t *buf, uint16_t len)
set the chip register
Definition driver_l3gd20h.c:4129
l3gd20h_get_reg
uint8_t l3gd20h_get_reg(l3gd20h_handle_t *handle, uint8_t reg, uint8_t *buf, uint16_t len)
get the chip register
Definition driver_l3gd20h.c:4156
l3gd20h_get_fifo_mode
uint8_t l3gd20h_get_fifo_mode(l3gd20h_handle_t *handle, l3gd20h_fifo_mode_t *fifo_mode)
get the fifo mode
Definition driver_l3gd20h.c:2478
l3gd20h_get_fifo_threshold
uint8_t l3gd20h_get_fifo_threshold(l3gd20h_handle_t *handle, uint8_t *threshold)
get the fifo threshold
Definition driver_l3gd20h.c:2559
l3gd20h_set_stop_on_fifo_threshold
uint8_t l3gd20h_set_stop_on_fifo_threshold(l3gd20h_handle_t *handle, l3gd20h_bool_t enable)
enable or disable stop on fifo threshold
Definition driver_l3gd20h.c:2033
l3gd20h_set_fifo_mode
uint8_t l3gd20h_set_fifo_mode(l3gd20h_handle_t *handle, l3gd20h_fifo_mode_t fifo_mode)
set the fifo mode
Definition driver_l3gd20h.c:2441
l3gd20h_get_fifo_level
uint8_t l3gd20h_get_fifo_level(l3gd20h_handle_t *handle, uint8_t *level)
get the fifo level
Definition driver_l3gd20h.c:2596
l3gd20h_set_fifo
uint8_t l3gd20h_set_fifo(l3gd20h_handle_t *handle, l3gd20h_bool_t enable)
enable or disable the fifo
Definition driver_l3gd20h.c:1959
l3gd20h_fifo_mode_t
l3gd20h_fifo_mode_t
l3gd20h fifo mode enumeration definition
Definition driver_l3gd20h.h:343
l3gd20h_set_fifo_threshold
uint8_t l3gd20h_set_fifo_threshold(l3gd20h_handle_t *handle, uint8_t threshold)
set the fifo threshold
Definition driver_l3gd20h.c:2516
l3gd20h_get_fifo
uint8_t l3gd20h_get_fifo(l3gd20h_handle_t *handle, l3gd20h_bool_t *enable)
get the fifo status
Definition driver_l3gd20h.c:1996
l3gd20h_get_stop_on_fifo_threshold
uint8_t l3gd20h_get_stop_on_fifo_threshold(l3gd20h_handle_t *handle, l3gd20h_bool_t *enable)
get stop on fifo threshold status
Definition driver_l3gd20h.c:2070
l3gd20h_set_interrupt_pin_type
uint8_t l3gd20h_set_interrupt_pin_type(l3gd20h_handle_t *handle, l3gd20h_pin_type_t pin_type)
set the interrupt pin type
Definition driver_l3gd20h.c:1071
l3gd20h_set_data_ready_on_interrupt2
uint8_t l3gd20h_set_data_ready_on_interrupt2(l3gd20h_handle_t *handle, l3gd20h_bool_t enable)
enable or disable the data ready on interrupt2
Definition driver_l3gd20h.c:1145
l3gd20h_get_interrupt_source
uint8_t l3gd20h_get_interrupt_source(l3gd20h_handle_t *handle, uint8_t *src)
get the interrupt source
Definition driver_l3gd20h.c:2709
l3gd20h_get_interrupt_active_level
uint8_t l3gd20h_get_interrupt_active_level(l3gd20h_handle_t *handle, l3gd20h_interrupt_active_level_t *level)
get the interrupt active level
Definition driver_l3gd20h.c:1034
l3gd20h_get_duration
uint8_t l3gd20h_get_duration(l3gd20h_handle_t *handle, uint8_t *duration)
get the wait duration
Definition driver_l3gd20h.c:3227
l3gd20h_get_interrupt_event
uint8_t l3gd20h_get_interrupt_event(l3gd20h_handle_t *handle, l3gd20h_interrupt_event_t interrupt_event, l3gd20h_bool_t *enable)
get the interrupt event
Definition driver_l3gd20h.c:2672
l3gd20h_get_x_interrupt_threshold
uint8_t l3gd20h_get_x_interrupt_threshold(l3gd20h_handle_t *handle, uint16_t *threshold)
get the x interrupt threshold
Definition driver_l3gd20h.c:2805
l3gd20h_get_fifo_empty_on_interrupt2
uint8_t l3gd20h_get_fifo_empty_on_interrupt2(l3gd20h_handle_t *handle, l3gd20h_bool_t *enable)
get the fifo empty on interrupt2 status
Definition driver_l3gd20h.c:1404
l3gd20h_get_interrupt_pin_type
uint8_t l3gd20h_get_interrupt_pin_type(l3gd20h_handle_t *handle, l3gd20h_pin_type_t *pin_type)
get the interrupt pin type
Definition driver_l3gd20h.c:1108
l3gd20h_get_counter_mode
uint8_t l3gd20h_get_counter_mode(l3gd20h_handle_t *handle, l3gd20h_counter_mode_t *counter_mode)
get the counter mode
Definition driver_l3gd20h.c:3074
l3gd20h_set_boot_on_interrupt1
uint8_t l3gd20h_set_boot_on_interrupt1(l3gd20h_handle_t *handle, l3gd20h_bool_t enable)
enable or disable boot on the interrupt1
Definition driver_l3gd20h.c:923
l3gd20h_set_x_interrupt_threshold
uint8_t l3gd20h_set_x_interrupt_threshold(l3gd20h_handle_t *handle, uint16_t threshold)
set the x interrupt threshold
Definition driver_l3gd20h.c:2745
l3gd20h_interrupt_event_t
l3gd20h_interrupt_event_t
l3gd20h interrupt event enumeration definition
Definition driver_l3gd20h.h:294
l3gd20h_interrupt_threshold_convert_to_data
uint8_t l3gd20h_interrupt_threshold_convert_to_data(l3gd20h_handle_t *handle, uint16_t reg, float *dps)
convert the interrupt threshold register raw data to the real data
Definition driver_l3gd20h.c:3497
l3gd20h_set_wait
uint8_t l3gd20h_set_wait(l3gd20h_handle_t *handle, l3gd20h_bool_t enable)
enable or disable the wait
Definition driver_l3gd20h.c:3111
l3gd20h_set_interrupt_event
uint8_t l3gd20h_set_interrupt_event(l3gd20h_handle_t *handle, l3gd20h_interrupt_event_t interrupt_event, l3gd20h_bool_t enable)
set the interrupt event
Definition driver_l3gd20h.c:2634
l3gd20h_counter_mode_t
l3gd20h_counter_mode_t
l3gd20h counter mode enumeration definition
Definition driver_l3gd20h.h:285
l3gd20h_set_duration
uint8_t l3gd20h_set_duration(l3gd20h_handle_t *handle, uint8_t duration)
set the wait duration
Definition driver_l3gd20h.c:3185
l3gd20h_set_fifo_threshold_on_interrupt2
uint8_t l3gd20h_set_fifo_threshold_on_interrupt2(l3gd20h_handle_t *handle, l3gd20h_bool_t enable)
enable or disable the fifo threshold on interrupt2
Definition driver_l3gd20h.c:1219
l3gd20h_get_y_interrupt_threshold
uint8_t l3gd20h_get_y_interrupt_threshold(l3gd20h_handle_t *handle, uint16_t *threshold)
get the y interrupt threshold
Definition driver_l3gd20h.c:2900
l3gd20h_get_fifo_threshold_on_interrupt2
uint8_t l3gd20h_get_fifo_threshold_on_interrupt2(l3gd20h_handle_t *handle, l3gd20h_bool_t *enable)
get the fifo threshold on interrupt2 status
Definition driver_l3gd20h.c:1256
l3gd20h_get_wait
uint8_t l3gd20h_get_wait(l3gd20h_handle_t *handle, l3gd20h_bool_t *enable)
get the wait status
Definition driver_l3gd20h.c:3148
l3gd20h_set_data_ready_active_level
uint8_t l3gd20h_set_data_ready_active_level(l3gd20h_handle_t *handle, l3gd20h_interrupt_active_level_t level)
set the data ready active level
Definition driver_l3gd20h.c:3264
l3gd20h_get_fifo_overrun_on_interrupt2
uint8_t l3gd20h_get_fifo_overrun_on_interrupt2(l3gd20h_handle_t *handle, l3gd20h_bool_t *enable)
get the fifo overrun on interrupt2 status
Definition driver_l3gd20h.c:1330
l3gd20h_set_counter_mode
uint8_t l3gd20h_set_counter_mode(l3gd20h_handle_t *handle, l3gd20h_counter_mode_t counter_mode)
set the counter mode
Definition driver_l3gd20h.c:3037
l3gd20h_get_data_ready_on_interrupt2
uint8_t l3gd20h_get_data_ready_on_interrupt2(l3gd20h_handle_t *handle, l3gd20h_bool_t *enable)
get the data ready on interrupt2 status
Definition driver_l3gd20h.c:1182
l3gd20h_get_boot_on_interrupt1
uint8_t l3gd20h_get_boot_on_interrupt1(l3gd20h_handle_t *handle, l3gd20h_bool_t *enable)
get the boot on the interrupt1 status
Definition driver_l3gd20h.c:960
l3gd20h_get_interrupt1
uint8_t l3gd20h_get_interrupt1(l3gd20h_handle_t *handle, l3gd20h_bool_t *enable)
get the interrupt1 status
Definition driver_l3gd20h.c:886
l3gd20h_set_interrupt_active_level
uint8_t l3gd20h_set_interrupt_active_level(l3gd20h_handle_t *handle, l3gd20h_interrupt_active_level_t level)
set the interrupt active level
Definition driver_l3gd20h.c:997
l3gd20h_set_fifo_overrun_on_interrupt2
uint8_t l3gd20h_set_fifo_overrun_on_interrupt2(l3gd20h_handle_t *handle, l3gd20h_bool_t enable)
enable or disable the fifo overrun on interrupt2
Definition driver_l3gd20h.c:1293
l3gd20h_interrupt_active_level_t
l3gd20h_interrupt_active_level_t
l3gd20h interrupt active level enumeration definition
Definition driver_l3gd20h.h:267
l3gd20h_interrupt_threshold_convert_to_register
uint8_t l3gd20h_interrupt_threshold_convert_to_register(l3gd20h_handle_t *handle, float dps, uint16_t *reg)
convert the interrupt threshold real data to the register raw data
Definition driver_l3gd20h.c:3449
l3gd20h_get_z_interrupt_threshold
uint8_t l3gd20h_get_z_interrupt_threshold(l3gd20h_handle_t *handle, uint16_t *threshold)
get the z interrupt threshold
Definition driver_l3gd20h.c:2995
l3gd20h_set_interrupt_selection
uint8_t l3gd20h_set_interrupt_selection(l3gd20h_handle_t *handle, l3gd20h_selection_t selection)
set the interrupt selection
Definition driver_l3gd20h.c:2181
l3gd20h_get_interrupt_selection
uint8_t l3gd20h_get_interrupt_selection(l3gd20h_handle_t *handle, l3gd20h_selection_t *selection)
get the interrupt selection
Definition driver_l3gd20h.c:2218
l3gd20h_set_fifo_empty_on_interrupt2
uint8_t l3gd20h_set_fifo_empty_on_interrupt2(l3gd20h_handle_t *handle, l3gd20h_bool_t enable)
enable or disable the fifo empty on interrupt2
Definition driver_l3gd20h.c:1367
l3gd20h_set_z_interrupt_threshold
uint8_t l3gd20h_set_z_interrupt_threshold(l3gd20h_handle_t *handle, uint16_t threshold)
set the z interrupt threshold
Definition driver_l3gd20h.c:2943
l3gd20h_get_data_ready_active_level
uint8_t l3gd20h_get_data_ready_active_level(l3gd20h_handle_t *handle, l3gd20h_interrupt_active_level_t *level)
get the data ready active level
Definition driver_l3gd20h.c:3301
l3gd20h_set_interrupt1
uint8_t l3gd20h_set_interrupt1(l3gd20h_handle_t *handle, l3gd20h_bool_t enable)
enable or disable the interrupt1
Definition driver_l3gd20h.c:849
l3gd20h_set_y_interrupt_threshold
uint8_t l3gd20h_set_y_interrupt_threshold(l3gd20h_handle_t *handle, uint16_t threshold)
set the y interrupt threshold
Definition driver_l3gd20h.c:2848
l3gd20h_pin_type_t
l3gd20h_pin_type_t
l3gd20h interrupt pin type enumeration definition
Definition driver_l3gd20h.h:276
L3GD20H_INTERRUPT1_Y_HIGH
@ L3GD20H_INTERRUPT1_Y_HIGH
Definition driver_l3gd20h.h:313
L3GD20H_INTERRUPT2_Y_DATA_READY
@ L3GD20H_INTERRUPT2_Y_DATA_READY
Definition driver_l3gd20h.h:323
L3GD20H_INTERRUPT1_X_LOW
@ L3GD20H_INTERRUPT1_X_LOW
Definition driver_l3gd20h.h:316
L3GD20H_INTERRUPT2_FIFO_EMPTY
@ L3GD20H_INTERRUPT2_FIFO_EMPTY
Definition driver_l3gd20h.h:327
L3GD20H_INTERRUPT1_X_HIGH
@ L3GD20H_INTERRUPT1_X_HIGH
Definition driver_l3gd20h.h:315
L3GD20H_INTERRUPT2_FIFO_THRESHOLD
@ L3GD20H_INTERRUPT2_FIFO_THRESHOLD
Definition driver_l3gd20h.h:325
L3GD20H_INTERRUPT1_Z_HIGH
@ L3GD20H_INTERRUPT1_Z_HIGH
Definition driver_l3gd20h.h:311
L3GD20H_INTERRUPT2_FIFO_OVERRRUN
@ L3GD20H_INTERRUPT2_FIFO_OVERRRUN
Definition driver_l3gd20h.h:326
L3GD20H_INTERRUPT2_X_OVERRUN
@ L3GD20H_INTERRUPT2_X_OVERRUN
Definition driver_l3gd20h.h:320
L3GD20H_INTERRUPT2_Y_OVERRUN
@ L3GD20H_INTERRUPT2_Y_OVERRUN
Definition driver_l3gd20h.h:319
L3GD20H_INTERRUPT2_X_DATA_READY
@ L3GD20H_INTERRUPT2_X_DATA_READY
Definition driver_l3gd20h.h:324
L3GD20H_INTERRUPT1_Y_LOW
@ L3GD20H_INTERRUPT1_Y_LOW
Definition driver_l3gd20h.h:314
L3GD20H_INTERRUPT1_INTERRUPT_ACTIVE
@ L3GD20H_INTERRUPT1_INTERRUPT_ACTIVE
Definition driver_l3gd20h.h:310
L3GD20H_INTERRUPT2_XYZ_DATA_READY
@ L3GD20H_INTERRUPT2_XYZ_DATA_READY
Definition driver_l3gd20h.h:321
L3GD20H_INTERRUPT2_Z_OVERRUN
@ L3GD20H_INTERRUPT2_Z_OVERRUN
Definition driver_l3gd20h.h:318
L3GD20H_INTERRUPT2_XYZ_OVERRUN
@ L3GD20H_INTERRUPT2_XYZ_OVERRUN
Definition driver_l3gd20h.h:317
L3GD20H_INTERRUPT2_Z_DATA_READY
@ L3GD20H_INTERRUPT2_Z_DATA_READY
Definition driver_l3gd20h.h:322
L3GD20H_INTERRUPT1_Z_LOW
@ L3GD20H_INTERRUPT1_Z_LOW
Definition driver_l3gd20h.h:312
l3gd20h_handle_s::iic_spi
uint8_t iic_spi
Definition driver_l3gd20h.h:380
l3gd20h_handle_s::inited
uint8_t inited
Definition driver_l3gd20h.h:379
l3gd20h_handle_s::spi_init
uint8_t(* spi_init)(void)
Definition driver_l3gd20h.h:372
l3gd20h_handle_s::delay_ms
void(* delay_ms)(uint32_t ms)
Definition driver_l3gd20h.h:377
l3gd20h_handle_s::spi_read
uint8_t(* spi_read)(uint8_t reg, uint8_t *buf, uint16_t len)
Definition driver_l3gd20h.h:374
l3gd20h_handle_s::receive_callback
void(* receive_callback)(uint8_t type)
Definition driver_l3gd20h.h:376
l3gd20h_handle_s::spi_write
uint8_t(* spi_write)(uint8_t reg, uint8_t *buf, uint16_t len)
Definition driver_l3gd20h.h:375
l3gd20h_handle_s::debug_print
void(* debug_print)(const char *const fmt,...)
Definition driver_l3gd20h.h:378
l3gd20h_handle_s::iic_init
uint8_t(* iic_init)(void)
Definition driver_l3gd20h.h:368
l3gd20h_handle_s::spi_deinit
uint8_t(* spi_deinit)(void)
Definition driver_l3gd20h.h:373
l3gd20h_handle_s::iic_write
uint8_t(* iic_write)(uint8_t addr, uint8_t reg, uint8_t *buf, uint16_t len)
Definition driver_l3gd20h.h:371
l3gd20h_handle_s::iic_addr
uint8_t iic_addr
Definition driver_l3gd20h.h:367
l3gd20h_handle_s::iic_read
uint8_t(* iic_read)(uint8_t addr, uint8_t reg, uint8_t *buf, uint16_t len)
Definition driver_l3gd20h.h:370
l3gd20h_handle_s::iic_deinit
uint8_t(* iic_deinit)(void)
Definition driver_l3gd20h.h:369
l3gd20h_info_s::temperature_max
float temperature_max
Definition driver_l3gd20h.h:395
l3gd20h_info_s::supply_voltage_max_v
float supply_voltage_max_v
Definition driver_l3gd20h.h:392
l3gd20h_info_s::driver_version
uint32_t driver_version
Definition driver_l3gd20h.h:396
l3gd20h_info_s::temperature_min
float temperature_min
Definition driver_l3gd20h.h:394
l3gd20h_info_s::max_current_ma
float max_current_ma
Definition driver_l3gd20h.h:393
l3gd20h_info_s::manufacturer_name
char manufacturer_name[32]
Definition driver_l3gd20h.h:389
l3gd20h_info_s::supply_voltage_min_v
float supply_voltage_min_v
Definition driver_l3gd20h.h:391
l3gd20h_info_s::interface
char interface[8]
Definition driver_l3gd20h.h:390
l3gd20h_info_s::chip_name
char chip_name[32]
Definition driver_l3gd20h.h:388