LibDriver L3GD20H
Loading...
Searching...
No Matches
driver_l3gd20h.c
Go to the documentation of this file.
1
37
38#include "driver_l3gd20h.h"
39
43#define CHIP_NAME "STMicroelectronic L3GD20H"
44#define MANUFACTURER_NAME "STMicroelectronic"
45#define SUPPLY_VOLTAGE_MIN 2.2f
46#define SUPPLY_VOLTAGE_MAX 3.6f
47#define MAX_CURRENT 5.0f
48#define TEMPERATURE_MIN -40.0f
49#define TEMPERATURE_MAX 85.0f
50#define DRIVER_VERSION 2000
51
55#define L3GD20H_REG_WHO_AM_I 0x0F
56#define L3GD20H_REG_CTRL1 0x20
57#define L3GD20H_REG_CTRL2 0x21
58#define L3GD20H_REG_CTRL3 0x22
59#define L3GD20H_REG_CTRL4 0x23
60#define L3GD20H_REG_CTRL5 0x24
61#define L3GD20H_REG_REFERENCE 0x25
62#define L3GD20H_REG_OUT_TEMP 0x26
63#define L3GD20H_REG_STATUS 0x27
64#define L3GD20H_REG_OUT_X_L 0x28
65#define L3GD20H_REG_OUT_X_H 0x29
66#define L3GD20H_REG_OUT_Y_L 0x2A
67#define L3GD20H_REG_OUT_Y_H 0x2B
68#define L3GD20H_REG_OUT_Z_L 0x2C
69#define L3GD20H_REG_OUT_Z_H 0x2D
70#define L3GD20H_REG_FIFO_CTRL 0x2E
71#define L3GD20H_REG_FIFO_SRC 0x2F
72#define L3GD20H_REG_IG_CFG 0x30
73#define L3GD20H_REG_IG_SRC 0x31
74#define L3GD20H_REG_IG_THS_XH 0x32
75#define L3GD20H_REG_IG_THS_XL 0x33
76#define L3GD20H_REG_IG_THS_YH 0x34
77#define L3GD20H_REG_IG_THS_YL 0x35
78#define L3GD20H_REG_IG_THS_ZH 0x36
79#define L3GD20H_REG_IG_THS_ZL 0x37
80#define L3GD20H_REG_IG_DURATION 0x38
81#define L3GD20H_REG_LOW_ODR 0x39
82
94static uint8_t a_l3gd20h_iic_spi_read(l3gd20h_handle_t *handle, uint8_t reg, uint8_t *buf, uint16_t len)
95{
96 if (handle->iic_spi == L3GD20H_INTERFACE_IIC) /* iic interface */
97 {
98 if (len > 1) /* len > 1 */
99 {
100 reg |= 1 << 7; /* flag bit 7 */
101 }
102
103 if (handle->iic_read(handle->iic_addr, reg, buf, len) != 0) /* read data */
104 {
105 return 1; /* return error */
106 }
107 else
108 {
109 return 0; /* success return 0 */
110 }
111 }
112 else /* spi interface */
113 {
114 if (len > 1) /* len > 1*/
115 {
116 reg |= 1 << 6; /* flag address increment */
117 }
118 reg |= 1 << 7; /* set read bit */
119
120 if (handle->spi_read(reg, buf, len) != 0) /* read data */
121 {
122 return 1; /* return error */
123 }
124 else
125 {
126 return 0; /* success return 0 */
127 }
128 }
129}
130
142static uint8_t a_l3gd20h_iic_spi_write(l3gd20h_handle_t *handle, uint8_t reg, uint8_t *buf, uint16_t len)
143{
144 if (handle->iic_spi == L3GD20H_INTERFACE_IIC) /* iic interface */
145 {
146 if (handle->iic_write(handle->iic_addr, reg, buf, len) != 0) /* write data */
147 {
148 return 1; /* return error */
149 }
150 else
151 {
152 return 0; /* success return 0 */
153 }
154 }
155 else /* spi interface */
156 {
157 if (len > 1) /* len > 1 */
158 {
159 reg |= 1 << 6; /* flag address increment */
160 }
161 reg &= ~(1 << 7); /* set write bit */
162
163 if (handle->spi_write(reg, buf, len) != 0) /* write data */
164 {
165 return 1; /* return error */
166 }
167 else
168 {
169 return 0; /* success return 0 */
170 }
171 }
172}
173
183uint8_t l3gd20h_set_interface(l3gd20h_handle_t *handle, l3gd20h_interface_t interface)
184{
185 if (handle == NULL) /* check handle */
186 {
187 return 2; /* return error */
188 }
189
190 handle->iic_spi = (uint8_t)interface; /* set the interface */
191
192 return 0; /* success return 0 */
193}
194
204uint8_t l3gd20h_get_interface(l3gd20h_handle_t *handle, l3gd20h_interface_t *interface)
205{
206 if (handle == NULL) /* check handle */
207 {
208 return 2; /* return error */
209 }
210
211 *interface = (l3gd20h_interface_t)(handle->iic_spi); /* get the interface */
212
213 return 0; /* success return 0 */
214}
215
225uint8_t l3gd20h_set_addr_pin(l3gd20h_handle_t *handle, l3gd20h_address_t addr_pin)
226{
227 if (handle == NULL) /* check handle */
228 {
229 return 2; /* return error */
230 }
231
232 handle->iic_addr = (uint8_t)addr_pin; /* set the iic address */
233
234 return 0; /* success return 0 */
235}
236
246uint8_t l3gd20h_get_addr_pin(l3gd20h_handle_t *handle, l3gd20h_address_t *addr_pin)
247{
248 if (handle == NULL) /* check handle */
249 {
250 return 2; /* return error */
251 }
252
253 *addr_pin = (l3gd20h_address_t)(handle->iic_addr); /* get the iic address */
254
255 return 0; /* success return 0 */
256}
257
269uint8_t l3gd20h_set_mode(l3gd20h_handle_t *handle, l3gd20h_mode_t mode)
270{
271 uint8_t res, prev;
272
273 if (handle == NULL) /* check handle */
274 {
275 return 2; /* return error */
276 }
277 if (handle->inited != 1) /* check handle initialization */
278 {
279 return 3; /* return error */
280 }
281
282 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL1, (uint8_t *)&prev, 1); /* read config */
283 if (res != 0) /* check result */
284 {
285 handle->debug_print("l3gd20h: read ctrl1 failed.\n"); /* read ctrl1 failed */
286
287 return 1; /* return error */
288 }
289 if (mode == L3GD20H_MODE_SLEEP) /* if sleep mode */
290 {
291 prev |= (1 << 3); /* set pd */
292 prev &= ~(0x07); /* clear config */
293
294 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_CTRL1, (uint8_t *)&prev, 1); /* write config */
295 }
296 else
297 {
298 prev &= ~(1 << 3); /* clear pd */
299 prev |= (mode << 3); /* set mode */
300 prev |= 0x07; /* set x,y,z enable */
301
302 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_CTRL1, (uint8_t *)&prev, 1); /* write config */
303 }
304}
305
317uint8_t l3gd20h_get_mode(l3gd20h_handle_t *handle, l3gd20h_mode_t *mode)
318{
319 uint8_t res, prev;
320
321 if (handle == NULL) /* check handle */
322 {
323 return 2; /* return error */
324 }
325 if (handle->inited != 1) /* check handle initialization */
326 {
327 return 3; /* return error */
328 }
329
330 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL1, (uint8_t *)&prev, 1); /* read config */
331 if (res != 0) /* check result */
332 {
333 handle->debug_print("l3gd20h: read ctrl1 failed.\n"); /* read ctrl1 failed */
334
335 return 1; /* return error */
336 }
337 if ((prev & 0x07) != 0) /* if x,y,z valid */
338 {
339 prev &= 1 << 3; /* set pd */
340 *mode = (l3gd20h_mode_t)((prev >> 3) & 0x01); /* normal or power down mode */
341 }
342 else
343 {
344 if ((prev & (1 << 3)) != 0) /* if pd == 1 */
345 {
346 *mode = L3GD20H_MODE_SLEEP; /* sleep mode*/
347 }
348 else
349 {
350 prev &= 1 << 3; /* set pd */
351 *mode = (l3gd20h_mode_t)((prev >> 3) & 0x01); /* set power down mode */
352 }
353 }
354
355 return 0; /* success return 0 */
356}
357
370uint8_t l3gd20h_set_axis(l3gd20h_handle_t *handle, l3gd20h_axis_t axis, l3gd20h_bool_t enable)
371{
372 uint8_t res, prev;
373
374 if (handle == NULL) /* check handle */
375 {
376 return 2; /* return error */
377 }
378 if (handle->inited != 1) /* check handle initialization */
379 {
380 return 3; /* return error */
381 }
382
383 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL1, (uint8_t *)&prev, 1); /* read config */
384 if (res != 0) /* check result */
385 {
386 handle->debug_print("l3gd20h: read ctrl1 failed.\n"); /* read ctrl1 failed */
387
388 return 1; /* return error */
389 }
390 prev &= ~(1 << axis); /* clear enable bit */
391 prev |= enable << axis; /* set enable */
392
393 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_CTRL1, (uint8_t *)&prev, 1); /* write config */
394}
395
408uint8_t l3gd20h_get_axis(l3gd20h_handle_t *handle, l3gd20h_axis_t axis, l3gd20h_bool_t *enable)
409{
410 uint8_t res, prev;
411
412 if (handle == NULL) /* check handle */
413 {
414 return 2; /* return error */
415 }
416 if (handle->inited != 1) /* check handle initialization */
417 {
418 return 3; /* return error */
419 }
420
421 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL1, (uint8_t *)&prev, 1); /* read config */
422 if (res != 0) /* check result */
423 {
424 handle->debug_print("l3gd20h: read ctrl1 failed.\n"); /* read ctrl1 failed */
425
426 return 1; /* return error */
427 }
428 prev &= (1 << axis); /* get enable bit */
429 *enable = (l3gd20h_bool_t)(prev >> axis); /* get bool */
430
431 return 0; /* success return 0 */
432}
433
445uint8_t l3gd20h_set_rate_bandwidth(l3gd20h_handle_t *handle, l3gd20h_lodr_odr_bw_t rate_bandwidth)
446{
447 uint8_t res, prev;
448
449 if (handle == NULL) /* check handle */
450 {
451 return 2; /* return error */
452 }
453 if (handle->inited != 1) /* check handle initialization */
454 {
455 return 3; /* return error */
456 }
457
458 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL1, (uint8_t *)&prev, 1); /* read config */
459 if (res != 0) /* check result */
460 {
461 handle->debug_print("l3gd20h: read ctrl1 failed.\n"); /* read ctrl1 failed */
462
463 return 1; /* return error */
464 }
465 prev &= ~(0xF << 4); /* clear rate and bandwidth bits */
466 prev |= (rate_bandwidth & 0xF) << 4; /* set rate and bandwidth */
467 if (a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_CTRL1, (uint8_t *)&prev, 1) != 0) /* write config */
468 {
469 handle->debug_print("l3gd20h: write ctrl1 failed.\n"); /* write ctrl1 failed */
470
471 return 1; /* return error */
472 }
473
474 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_LOW_ODR, (uint8_t *)&prev, 1); /* read low odr */
475 if (res != 0) /* check result */
476 {
477 handle->debug_print("l3gd20h: read low odr failed.\n"); /* read low odr failed */
478
479 return 1; /* return error */
480 }
481 prev &= ~(1 << 0); /* clear odr bit */
482 prev |= ((rate_bandwidth & 0x10) >> 4) & 0x01; /* set odr */
483 if (a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_LOW_ODR, (uint8_t *)&prev, 1) != 0) /* write config */
484 {
485 handle->debug_print("l3gd20h: write low odr failed.\n"); /* write low odr failed */
486
487 return 1; /* return error */
488 }
489
490 return 0; /* success return 0 */
491}
492
504uint8_t l3gd20h_get_rate_bandwidth(l3gd20h_handle_t *handle, l3gd20h_lodr_odr_bw_t *rate_bandwidth)
505{
506 uint8_t res, prev1, prev2;
507
508 if (handle == NULL) /* check handle */
509 {
510 return 2; /* return error */
511 }
512 if (handle->inited != 1) /* check handle initialization */
513 {
514 return 3; /* return error */
515 }
516
517 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL1, (uint8_t *)&prev1, 1); /* read config */
518 if (res != 0) /* check result */
519 {
520 handle->debug_print("l3gd20h: read ctrl1 failed.\n"); /* read ctrl1 failed */
521
522 return 1; /* return error */
523 }
524 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_LOW_ODR, (uint8_t *)&prev2, 1); /* read low odr */
525 if (res != 0) /* check result */
526 {
527 handle->debug_print("l3gd20h: read low odr failed.\n"); /* read low odr failed */
528
529 return 1; /* return error */
530 }
531 *rate_bandwidth = (l3gd20h_lodr_odr_bw_t)(((prev2 & 0x01) << 4) | (prev1 >> 4)); /* get rate and bandwidth */
532
533 return 0; /* success return 0 */
534}
535
547uint8_t l3gd20h_set_edge_trigger(l3gd20h_handle_t *handle, l3gd20h_bool_t enable)
548{
549 uint8_t res, prev;
550
551 if (handle == NULL) /* check handle */
552 {
553 return 2; /* return error */
554 }
555 if (handle->inited != 1) /* check handle initialization */
556 {
557 return 3; /* return error */
558 }
559
560 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL2, (uint8_t *)&prev, 1); /* read config */
561 if (res != 0) /* check result */
562 {
563 handle->debug_print("l3gd20h: read ctrl2 failed.\n"); /* read ctrl2 failed */
564
565 return 1; /* return error */
566 }
567 prev &= ~(1 << 7); /* clear enable bit */
568 prev |= enable << 7; /* set enable */
569
570 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_CTRL2, (uint8_t *)&prev, 1); /* write config */
571}
572
584uint8_t l3gd20h_get_edge_trigger(l3gd20h_handle_t *handle, l3gd20h_bool_t *enable)
585{
586 uint8_t res, prev;
587
588 if (handle == NULL) /* check handle */
589 {
590 return 2; /* return error */
591 }
592 if (handle->inited != 1) /* check handle initialization */
593 {
594 return 3; /* return error */
595 }
596
597 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL2, (uint8_t *)&prev, 1); /* read config */
598 if (res != 0) /* check result */
599 {
600 handle->debug_print("l3gd20h: read ctrl2 failed.\n"); /* read ctrl2 failed */
601
602 return 1; /* return error */
603 }
604
605 prev &= (1 << 7); /* get enable bit */
606 *enable = (l3gd20h_bool_t)(prev >> 7); /* get bool */
607
608 return 0; /* success return 0 */
609}
610
622uint8_t l3gd20h_set_level_trigger(l3gd20h_handle_t *handle, l3gd20h_bool_t enable)
623{
624 uint8_t res, prev;
625
626 if (handle == NULL) /* check handle */
627 {
628 return 2; /* return error */
629 }
630 if (handle->inited != 1) /* check handle initialization */
631 {
632 return 3; /* return error */
633 }
634
635 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL2, (uint8_t *)&prev, 1); /* read config */
636 if (res != 0) /* check result */
637 {
638 handle->debug_print("l3gd20h: read ctrl2 failed.\n"); /* read ctrl2 failed */
639
640 return 1; /* return error */
641 }
642 prev &= ~(1 << 6); /* get bool */
643 prev |= enable << 6; /* set enable */
644
645 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_CTRL2, (uint8_t *)&prev, 1); /* write config */
646}
647
659uint8_t l3gd20h_get_level_trigger(l3gd20h_handle_t *handle, l3gd20h_bool_t *enable)
660{
661 uint8_t res, prev;
662
663 if (handle == NULL) /* check handle */
664 {
665 return 2; /* return error */
666 }
667 if (handle->inited != 1) /* check handle initialization */
668 {
669 return 3; /* return error */
670 }
671
672 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL2, (uint8_t *)&prev, 1); /* read config */
673 if (res != 0) /* check result */
674 {
675 handle->debug_print("l3gd20h: read ctrl2 failed.\n"); /* read ctrl2 failed */
676
677 return 1; /* return error */
678 }
679 prev &= (1 << 6); /* get enable */
680 *enable = (l3gd20h_bool_t)(prev >> 6); /* get bool */
681
682 return 0; /* success return 0 */
683}
684
696uint8_t l3gd20h_set_high_pass_filter_mode(l3gd20h_handle_t *handle, l3gd20h_high_pass_filter_mode_t mode)
697{
698 uint8_t res, prev;
699
700 if (handle == NULL) /* check handle */
701 {
702 return 2; /* return error */
703 }
704 if (handle->inited != 1) /* check handle initialization */
705 {
706 return 3; /* return error */
707 }
708
709 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL2, (uint8_t *)&prev, 1); /* read config */
710 if (res != 0) /* check result */
711 {
712 handle->debug_print("l3gd20h: read ctrl2 failed.\n"); /* read ctrl2 failed */
713
714 return 1; /* return error */
715 }
716 prev &= ~(3 << 4); /* clear the mode */
717 prev |= mode << 4; /* set the mode */
718
719 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_CTRL2, (uint8_t *)&prev, 1); /* write config */
720}
721
733uint8_t l3gd20h_get_high_pass_filter_mode(l3gd20h_handle_t *handle, l3gd20h_high_pass_filter_mode_t *mode)
734{
735 uint8_t res, prev;
736
737 if (handle == NULL) /* check handle */
738 {
739 return 2; /* return error */
740 }
741 if (handle->inited != 1) /* check handle initialization */
742 {
743 return 3; /* return error */
744 }
745
746 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL2, (uint8_t *)&prev, 1); /* read config */
747 if (res != 0) /* check result */
748 {
749 handle->debug_print("l3gd20h: read ctrl2 failed.\n"); /* read ctrl2 failed */
750
751 return 1; /* return error */
752 }
753 prev &= (3 << 4); /* get the mode bits */
754 *mode = (l3gd20h_high_pass_filter_mode_t)(prev >> 4); /* get the mode */
755
756 return 0; /* success return 0 */
757}
758
770uint8_t l3gd20h_set_high_pass_filter_cut_off_frequency(l3gd20h_handle_t *handle, l3gd20h_high_pass_filter_cut_off_frequency_t frequency)
771{
772 uint8_t res, prev;
773
774 if (handle == NULL) /* check handle */
775 {
776 return 2; /* return error */
777 }
778 if (handle->inited != 1) /* check handle initialization */
779 {
780 return 3; /* return error */
781 }
782
783 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL2, (uint8_t *)&prev, 1); /* read config */
784 if (res != 0) /* check result */
785 {
786 handle->debug_print("l3gd20h: read ctrl2 failed.\n"); /* read ctrl2 failed */
787
788 return 1; /* return error */
789 }
790 prev &= ~(0x0F); /* clear the cut-off frequency */
791 prev |= frequency; /* set the frequency */
792
793 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_CTRL2, (uint8_t *)&prev, 1); /* write config */
794}
795
807uint8_t l3gd20h_get_high_pass_filter_cut_off_frequency(l3gd20h_handle_t *handle, l3gd20h_high_pass_filter_cut_off_frequency_t *frequency)
808{
809 uint8_t res, prev;
810
811 if (handle == NULL) /* check handle */
812 {
813 return 2; /* return error */
814 }
815 if (handle->inited != 1) /* check handle initialization */
816 {
817 return 3; /* return error */
818 }
819
820 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL2, (uint8_t *)&prev, 1); /* read config */
821 if (res != 0) /* check result */
822 {
823 handle->debug_print("l3gd20h: read ctrl2 failed.\n"); /* read ctrl2 failed */
824
825 return 1; /* return error */
826 }
827 prev &= 0x0F; /* get the cut-off frequency */
828 *frequency = (l3gd20h_high_pass_filter_cut_off_frequency_t)(prev >> 0); /* get the frequency */
829
830 return 0; /* success return 0 */
831}
832
844uint8_t l3gd20h_set_interrupt1(l3gd20h_handle_t *handle, l3gd20h_bool_t enable)
845{
846 uint8_t res, prev;
847
848 if (handle == NULL) /* check handle */
849 {
850 return 2; /* return error */
851 }
852 if (handle->inited != 1) /* check handle initialization */
853 {
854 return 3; /* return error */
855 }
856
857 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL3, (uint8_t *)&prev, 1); /* read config */
858 if (res != 0) /* check result */
859 {
860 handle->debug_print("l3gd20h: read ctrl3 failed.\n"); /* read ctrl3 failed */
861
862 return 1; /* return error */
863 }
864 prev &= ~(1 << 7); /* clear enable */
865 prev |= enable << 7; /* set enable */
866
867 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_CTRL3, (uint8_t *)&prev, 1); /* write config */
868}
869
881uint8_t l3gd20h_get_interrupt1(l3gd20h_handle_t *handle, l3gd20h_bool_t *enable)
882{
883 uint8_t res, prev;
884
885 if (handle == NULL) /* check handle */
886 {
887 return 2; /* return error */
888 }
889 if (handle->inited != 1) /* check handle initialization */
890 {
891 return 3; /* return error */
892 }
893
894 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL3, (uint8_t *)&prev, 1); /* read config */
895 if (res != 0) /* check result */
896 {
897 handle->debug_print("l3gd20h: read ctrl3 failed.\n"); /* read ctrl3 failed */
898
899 return 1; /* return error */
900 }
901 prev &= (1 << 7); /* get enable bit */
902 *enable = (l3gd20h_bool_t)(prev >> 7); /* get bool */
903
904 return 0; /* success return 0 */
905}
906
918uint8_t l3gd20h_set_boot_on_interrupt1(l3gd20h_handle_t *handle, l3gd20h_bool_t enable)
919{
920 uint8_t res, prev;
921
922 if (handle == NULL) /* check handle */
923 {
924 return 2; /* return error */
925 }
926 if (handle->inited != 1) /* check handle initialization */
927 {
928 return 3; /* return error */
929 }
930
931 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL3, (uint8_t *)&prev, 1); /* read config */
932 if (res != 0) /* check result */
933 {
934 handle->debug_print("l3gd20h: read ctrl3 failed.\n"); /* read ctrl3 failed */
935
936 return 1; /* return error */
937 }
938 prev &= ~(1 << 6); /* clear enable bit */
939 prev |= enable << 6; /* set enable */
940
941 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_CTRL3, (uint8_t *)&prev, 1); /* write config */
942}
943
955uint8_t l3gd20h_get_boot_on_interrupt1(l3gd20h_handle_t *handle, l3gd20h_bool_t *enable)
956{
957 uint8_t res, prev;
958
959 if (handle == NULL) /* check handle */
960 {
961 return 2; /* return error */
962 }
963 if (handle->inited != 1) /* check handle initialization */
964 {
965 return 3; /* return error */
966 }
967
968 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL3, (uint8_t *)&prev, 1); /* read config */
969 if (res != 0) /* check result */
970 {
971 handle->debug_print("l3gd20h: read ctrl3 failed.\n"); /* read ctrl3 failed */
972
973 return 1; /* return error */
974 }
975 prev &= (1 << 6); /* get enable bit */
976 *enable = (l3gd20h_bool_t)(prev >> 6); /* get bool */
977
978 return 0; /* success return 0 */
979}
980
992uint8_t l3gd20h_set_interrupt_active_level(l3gd20h_handle_t *handle, l3gd20h_interrupt_active_level_t level)
993{
994 uint8_t res, prev;
995
996 if (handle == NULL) /* check handle */
997 {
998 return 2; /* return error */
999 }
1000 if (handle->inited != 1) /* check handle initialization */
1001 {
1002 return 3; /* return error */
1003 }
1004
1005 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL3, (uint8_t *)&prev, 1); /* read config */
1006 if (res != 0) /* check result */
1007 {
1008 handle->debug_print("l3gd20h: read ctrl3 failed.\n"); /* read ctrl3 failed */
1009
1010 return 1; /* return error */
1011 }
1012 prev &= ~(1 << 5); /* clear level bit */
1013 prev |= level << 5; /* set level bit */
1014
1015 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_CTRL3, (uint8_t *)&prev, 1); /* write config */
1016}
1017
1029uint8_t l3gd20h_get_interrupt_active_level(l3gd20h_handle_t *handle, l3gd20h_interrupt_active_level_t *level)
1030{
1031 uint8_t res, prev;
1032
1033 if (handle == NULL) /* check handle */
1034 {
1035 return 2; /* return error */
1036 }
1037 if (handle->inited != 1) /* check handle initialization */
1038 {
1039 return 3; /* return error */
1040 }
1041
1042 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL3, (uint8_t *)&prev, 1); /* read config */
1043 if (res != 0) /* check result */
1044 {
1045 handle->debug_print("l3gd20h: read ctrl3 failed.\n"); /* read ctrl3 failed */
1046
1047 return 1; /* return error */
1048 }
1049 prev &= (1 << 5); /* get the level bit */
1050 *level = (l3gd20h_interrupt_active_level_t)(prev >> 5); /* get the level */
1051
1052 return 0; /* success return 0 */
1053}
1054
1066uint8_t l3gd20h_set_interrupt_pin_type(l3gd20h_handle_t *handle, l3gd20h_pin_type_t pin_type)
1067{
1068 uint8_t res, prev;
1069
1070 if (handle == NULL) /* check handle */
1071 {
1072 return 2; /* return error */
1073 }
1074 if (handle->inited != 1) /* check handle initialization */
1075 {
1076 return 3; /* return error */
1077 }
1078
1079 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL3, (uint8_t *)&prev, 1); /* read config */
1080 if (res != 0) /* check result */
1081 {
1082 handle->debug_print("l3gd20h: read ctrl3 failed.\n"); /* read ctrl3 failed */
1083
1084 return 1; /* return error */
1085 }
1086 prev &= ~(1 << 4); /* clear pin type bit */
1087 prev |= pin_type << 4; /* set pin type */
1088
1089 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_CTRL3, (uint8_t *)&prev, 1); /* write config */
1090}
1091
1103uint8_t l3gd20h_get_interrupt_pin_type(l3gd20h_handle_t *handle, l3gd20h_pin_type_t *pin_type)
1104{
1105 uint8_t res, prev;
1106
1107 if (handle == NULL) /* check handle */
1108 {
1109 return 2; /* return error */
1110 }
1111 if (handle->inited != 1) /* check handle initialization */
1112 {
1113 return 3; /* return error */
1114 }
1115
1116 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL3, (uint8_t *)&prev, 1); /* read config */
1117 if (res != 0) /* check result */
1118 {
1119 handle->debug_print("l3gd20h: read ctrl3 failed.\n"); /* read ctrl3 failed */
1120
1121 return 1; /* return error */
1122 }
1123 prev &= (1 << 4); /* get pin type bit */
1124 *pin_type = (l3gd20h_pin_type_t)(prev >> 4); /* get pin type */
1125
1126 return 0; /* success return 0 */
1127}
1128
1140uint8_t l3gd20h_set_data_ready_on_interrupt2(l3gd20h_handle_t *handle, l3gd20h_bool_t enable)
1141{
1142 uint8_t res, prev;
1143
1144 if (handle == NULL) /* check handle */
1145 {
1146 return 2; /* return error */
1147 }
1148 if (handle->inited != 1) /* check handle initialization */
1149 {
1150 return 3; /* return error */
1151 }
1152
1153 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL3, (uint8_t *)&prev, 1); /* read config */
1154 if (res != 0) /* check result */
1155 {
1156 handle->debug_print("l3gd20h: read ctrl3 failed.\n"); /* read ctrl3 failed */
1157
1158 return 1; /* return error */
1159 }
1160 prev &= ~(1 << 3); /* set data ready bit */
1161 prev |= enable << 3; /* set data ready */
1162
1163 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_CTRL3, (uint8_t *)&prev, 1); /* write config */
1164}
1165
1177uint8_t l3gd20h_get_data_ready_on_interrupt2(l3gd20h_handle_t *handle, l3gd20h_bool_t *enable)
1178{
1179 uint8_t res, prev;
1180
1181 if (handle == NULL) /* check handle */
1182 {
1183 return 2; /* return error */
1184 }
1185 if (handle->inited != 1) /* check handle initialization */
1186 {
1187 return 3; /* return error */
1188 }
1189
1190 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL3, (uint8_t *)&prev, 1); /* read config */
1191 if (res != 0) /* check result */
1192 {
1193 handle->debug_print("l3gd20h: read ctrl3 failed.\n"); /* read ctrl3 failed */
1194
1195 return 1; /* return error */
1196 }
1197 prev &= (1 << 3); /* get enable bit */
1198 *enable = (l3gd20h_bool_t)(prev >> 3); /* get bool */
1199
1200 return 0; /* success return 0 */
1201}
1202
1214uint8_t l3gd20h_set_fifo_threshold_on_interrupt2(l3gd20h_handle_t *handle, l3gd20h_bool_t enable)
1215{
1216 uint8_t res, prev;
1217
1218 if (handle == NULL) /* check handle */
1219 {
1220 return 2; /* return error */
1221 }
1222 if (handle->inited != 1) /* check handle initialization */
1223 {
1224 return 3; /* return error */
1225 }
1226
1227 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL3, (uint8_t *)&prev, 1); /* read config */
1228 if (res != 0) /* check result */
1229 {
1230 handle->debug_print("l3gd20h: read ctrl3 failed.\n"); /* read ctrl3 failed */
1231
1232 return 1; /* return error */
1233 }
1234 prev &= ~(1 << 2); /* clear enable bit */
1235 prev |= enable << 2; /* set enable */
1236
1237 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_CTRL3, (uint8_t *)&prev, 1); /* write config */
1238}
1239
1251uint8_t l3gd20h_get_fifo_threshold_on_interrupt2(l3gd20h_handle_t *handle, l3gd20h_bool_t *enable)
1252{
1253 uint8_t res, prev;
1254
1255 if (handle == NULL) /* check handle */
1256 {
1257 return 2; /* return error */
1258 }
1259 if (handle->inited != 1) /* check handle initialization */
1260 {
1261 return 3; /* return error */
1262 }
1263
1264 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL3, (uint8_t *)&prev, 1); /* read config */
1265 if (res != 0) /* check result */
1266 {
1267 handle->debug_print("l3gd20h: read ctrl3 failed.\n"); /* read ctrl3 failed */
1268
1269 return 1; /* return error */
1270 }
1271 prev &= (1 << 2); /* get enable bit */
1272 *enable = (l3gd20h_bool_t)(prev >> 2); /* get bool */
1273
1274 return 0; /* success return 0 */
1275}
1276
1288uint8_t l3gd20h_set_fifo_overrun_on_interrupt2(l3gd20h_handle_t *handle, l3gd20h_bool_t enable)
1289{
1290 uint8_t res, prev;
1291
1292 if (handle == NULL) /* check handle */
1293 {
1294 return 2; /* return error */
1295 }
1296 if (handle->inited != 1) /* check handle initialization */
1297 {
1298 return 3; /* return error */
1299 }
1300
1301 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL3, (uint8_t *)&prev, 1); /* read config */
1302 if (res != 0) /* check result */
1303 {
1304 handle->debug_print("l3gd20h: read ctrl3 failed.\n"); /* read ctrl3 failed */
1305
1306 return 1; /* return error */
1307 }
1308 prev &= ~(1 << 1); /* clear enable bit */
1309 prev |= enable << 1; /* set enable */
1310
1311 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_CTRL3, (uint8_t *)&prev, 1); /* write config */
1312}
1313
1325uint8_t l3gd20h_get_fifo_overrun_on_interrupt2(l3gd20h_handle_t *handle, l3gd20h_bool_t *enable)
1326{
1327 uint8_t res, prev;
1328
1329 if (handle == NULL) /* check handle */
1330 {
1331 return 2; /* return error */
1332 }
1333 if (handle->inited != 1) /* check handle initialization */
1334 {
1335 return 3; /* return error */
1336 }
1337
1338 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL3, (uint8_t *)&prev, 1); /* read config */
1339 if (res != 0) /* check result */
1340 {
1341 handle->debug_print("l3gd20h: read ctrl3 failed.\n"); /* read ctrl3 failed */
1342
1343 return 1; /* return error */
1344 }
1345 prev &= (1 << 1); /* get enable bit */
1346 *enable = (l3gd20h_bool_t)(prev >> 1); /* get bool */
1347
1348 return 0; /* success return 0 */
1349}
1350
1362uint8_t l3gd20h_set_fifo_empty_on_interrupt2(l3gd20h_handle_t *handle, l3gd20h_bool_t enable)
1363{
1364 uint8_t res, prev;
1365
1366 if (handle == NULL) /* check handle */
1367 {
1368 return 2; /* return error */
1369 }
1370 if (handle->inited != 1) /* check handle initialization */
1371 {
1372 return 3; /* return error */
1373 }
1374
1375 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL3, (uint8_t *)&prev, 1); /* read config */
1376 if (res != 0) /* check result */
1377 {
1378 handle->debug_print("l3gd20h: read ctrl3 failed.\n"); /* read ctrl3 failed */
1379
1380 return 1; /* return error */
1381 }
1382 prev &= ~(1 << 0); /* clear enable bit */
1383 prev |= enable << 0; /* set enable */
1384
1385 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_CTRL3, (uint8_t *)&prev, 1); /* write config */
1386}
1387
1399uint8_t l3gd20h_get_fifo_empty_on_interrupt2(l3gd20h_handle_t *handle, l3gd20h_bool_t *enable)
1400{
1401 uint8_t res, prev;
1402
1403 if (handle == NULL) /* check handle */
1404 {
1405 return 2; /* return error */
1406 }
1407 if (handle->inited != 1) /* check handle initialization */
1408 {
1409 return 3; /* return error */
1410 }
1411
1412 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL3, (uint8_t *)&prev, 1); /* read config */
1413 if (res != 0) /* check result */
1414 {
1415 handle->debug_print("l3gd20h: read ctrl3 failed.\n"); /* read ctrl3 failed */
1416
1417 return 1; /* return error */
1418 }
1419 prev &= (1 << 0); /* get enable bit */
1420 *enable = (l3gd20h_bool_t)(prev >> 0); /* get bool */
1421
1422 return 0; /* success return 0 */
1423}
1424
1436uint8_t l3gd20h_set_block_data_update(l3gd20h_handle_t *handle, l3gd20h_bool_t enable)
1437{
1438 uint8_t res, prev;
1439
1440 if (handle == NULL) /* check handle */
1441 {
1442 return 2; /* return error */
1443 }
1444 if (handle->inited != 1) /* check handle initialization */
1445 {
1446 return 3; /* return error */
1447 }
1448
1449 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL4, (uint8_t *)&prev, 1); /* read config */
1450 if (res != 0) /* check result */
1451 {
1452 handle->debug_print("l3gd20h: read ctrl4 failed.\n"); /* read ctrl4 failed */
1453
1454 return 1; /* return error */
1455 }
1456 prev &= ~(1 << 7); /* clear enable bit */
1457 prev |= enable << 7; /* set enable */
1458
1459 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_CTRL4, (uint8_t *)&prev, 1); /* write config */
1460}
1461
1473uint8_t l3gd20h_get_block_data_update(l3gd20h_handle_t *handle, l3gd20h_bool_t *enable)
1474{
1475 uint8_t res, prev;
1476
1477 if (handle == NULL) /* check handle */
1478 {
1479 return 2; /* return error */
1480 }
1481 if (handle->inited != 1) /* check handle initialization */
1482 {
1483 return 3; /* return error */
1484 }
1485
1486 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL4, (uint8_t *)&prev, 1); /* read config */
1487 if (res != 0) /* check result */
1488 {
1489 handle->debug_print("l3gd20h: read ctrl4 failed.\n"); /* read ctrl4 failed */
1490
1491 return 1; /* return error */
1492 }
1493 prev &= (1 << 7); /* get enable bit */
1494 *enable = (l3gd20h_bool_t)(prev >> 7); /* get bool */
1495
1496 return 0; /* success return 0 */
1497}
1498
1510uint8_t l3gd20h_set_data_format(l3gd20h_handle_t *handle, l3gd20h_data_format_t data_format)
1511{
1512 uint8_t res, prev;
1513
1514 if (handle == NULL) /* check handle */
1515 {
1516 return 2; /* return error */
1517 }
1518 if (handle->inited != 1) /* check handle initialization */
1519 {
1520 return 3; /* return error */
1521 }
1522
1523 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL4, (uint8_t *)&prev, 1); /* read config */
1524 if (res != 0) /* check result */
1525 {
1526 handle->debug_print("l3gd20h: read ctrl4 failed.\n"); /* read ctrl4 failed */
1527
1528 return 1; /* return error */
1529 }
1530 prev &= ~(1 << 6); /* clear enable bit */
1531 prev |= data_format << 6; /* set enable */
1532
1533 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_CTRL4, (uint8_t *)&prev, 1); /* write config */
1534}
1535
1547uint8_t l3gd20h_get_data_format(l3gd20h_handle_t *handle, l3gd20h_data_format_t *data_format)
1548{
1549 uint8_t res, prev;
1550
1551 if (handle == NULL) /* check handle */
1552 {
1553 return 2; /* return error */
1554 }
1555 if (handle->inited != 1) /* check handle initialization */
1556 {
1557 return 3; /* return error */
1558 }
1559
1560 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL4, (uint8_t *)&prev, 1); /* read config */
1561 if (res != 0) /* check result */
1562 {
1563 handle->debug_print("l3gd20h: read ctrl4 failed.\n"); /* read ctrl4 failed */
1564
1565 return 1; /* return error */
1566 }
1567 prev &= (1 << 6); /* get enable bit */
1568 *data_format = (l3gd20h_data_format_t)(prev >> 6); /* set enable */
1569
1570 return 0; /* success return 0 */
1571}
1572
1584uint8_t l3gd20h_set_full_scale(l3gd20h_handle_t *handle, l3gd20h_full_scale_t full_scale)
1585{
1586 uint8_t res, prev;
1587
1588 if (handle == NULL) /* check handle */
1589 {
1590 return 2; /* return error */
1591 }
1592 if (handle->inited != 1) /* check handle initialization */
1593 {
1594 return 3; /* return error */
1595 }
1596
1597 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL4, (uint8_t *)&prev, 1); /* read config */
1598 if (res != 0) /* check result */
1599 {
1600 handle->debug_print("l3gd20h: read ctrl4 failed.\n"); /* read ctrl4 failed */
1601
1602 return 1; /* return error */
1603 }
1604 prev &= ~(3 << 4); /* clear the scale bits */
1605 prev |= full_scale << 4; /* set scale */
1606
1607 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_CTRL4, (uint8_t *)&prev, 1); /* write config */
1608}
1609
1621uint8_t l3gd20h_get_full_scale(l3gd20h_handle_t *handle, l3gd20h_full_scale_t *full_scale)
1622{
1623 uint8_t res, prev;
1624
1625 if (handle == NULL) /* check handle */
1626 {
1627 return 2; /* return error */
1628 }
1629 if (handle->inited != 1) /* check handle initialization */
1630 {
1631 return 3; /* return error */
1632 }
1633
1634 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL4, (uint8_t *)&prev, 1); /* read config */
1635 if (res != 0) /* check result */
1636 {
1637 handle->debug_print("l3gd20h: read ctrl4 failed.\n"); /* read ctrl4 failed */
1638
1639 return 1; /* return error */
1640 }
1641 prev &= (3 << 4); /* get scale bits */
1642 *full_scale = (l3gd20h_full_scale_t)(prev >> 4); /* get scale */
1643
1644 return 0; /* success return 0 */
1645}
1646
1658uint8_t l3gd20h_set_level_sensitive_latched(l3gd20h_handle_t *handle, l3gd20h_bool_t enable)
1659{
1660 uint8_t res, prev;
1661
1662 if (handle == NULL) /* check handle */
1663 {
1664 return 2; /* return error */
1665 }
1666 if (handle->inited != 1) /* check handle initialization */
1667 {
1668 return 3; /* return error */
1669 }
1670
1671 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL4, (uint8_t *)&prev, 1); /* read config */
1672 if (res != 0) /* check result */
1673 {
1674 handle->debug_print("l3gd20h: read ctrl4 failed.\n"); /* read ctrl4 failed */
1675
1676 return 1; /* return error */
1677 }
1678 prev &= ~(1 << 3); /* clear enable bit */
1679 prev |= enable << 3; /* set enable */
1680
1681 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_CTRL4, (uint8_t *)&prev, 1); /* write config */
1682}
1683
1695uint8_t l3gd20h_get_level_sensitive_latched(l3gd20h_handle_t *handle, l3gd20h_bool_t *enable)
1696{
1697 uint8_t res, prev;
1698
1699 if (handle == NULL) /* check handle */
1700 {
1701 return 2; /* return error */
1702 }
1703 if (handle->inited != 1) /* check handle initialization */
1704 {
1705 return 3; /* return error */
1706 }
1707
1708 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL4, (uint8_t *)&prev, 1); /* read config */
1709 if (res != 0) /* check result */
1710 {
1711 handle->debug_print("l3gd20h: read ctrl4 failed.\n"); /* read ctrl4 failed */
1712
1713 return 1; /* return error */
1714 }
1715 prev &= (1 << 3); /* get enable bit */
1716 *enable = (l3gd20h_bool_t)(prev >> 3); /* get bool */
1717
1718 return 0; /* success return 0 */
1719}
1720
1732uint8_t l3gd20h_set_self_test(l3gd20h_handle_t *handle, l3gd20h_self_test_t self_test)
1733{
1734 uint8_t res, prev;
1735
1736 if (handle == NULL) /* check handle */
1737 {
1738 return 2; /* return error */
1739 }
1740 if (handle->inited != 1) /* check handle initialization */
1741 {
1742 return 3; /* return error */
1743 }
1744
1745 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL4, (uint8_t *)&prev, 1); /* read config */
1746 if (res != 0) /* check result */
1747 {
1748 handle->debug_print("l3gd20h: read ctrl4 failed.\n"); /* read ctrl4 failed */
1749
1750 return 1; /* return error */
1751 }
1752 prev &= ~(3 << 1); /* clear self test bits */
1753 prev |= self_test << 1; /* set self test */
1754
1755 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_CTRL4, (uint8_t *)&prev, 1); /* write config */
1756}
1757
1769uint8_t l3gd20h_get_self_test(l3gd20h_handle_t *handle, l3gd20h_self_test_t *self_test)
1770{
1771 uint8_t res, prev;
1772
1773 if (handle == NULL) /* check handle */
1774 {
1775 return 2; /* return error */
1776 }
1777 if (handle->inited != 1) /* check handle initialization */
1778 {
1779 return 3; /* return error */
1780 }
1781
1782 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL4, (uint8_t *)&prev, 1); /* read config */
1783 if (res != 0) /* check result */
1784 {
1785 handle->debug_print("l3gd20h: read ctrl4 failed.\n"); /* read ctrl4 failed */
1786
1787 return 1; /* return error */
1788 }
1789 prev &= (3 << 1); /* get self test bits */
1790 *self_test = (l3gd20h_self_test_t)(prev >> 1); /* get self test */
1791
1792 return 0; /* success return 0 */
1793}
1794
1806uint8_t l3gd20h_set_spi_wire(l3gd20h_handle_t *handle, l3gd20h_spi_wire_t spi_wire)
1807{
1808 uint8_t res, prev;
1809
1810 if (handle == NULL) /* check handle */
1811 {
1812 return 2; /* return error */
1813 }
1814 if (handle->inited != 1) /* check handle initialization */
1815 {
1816 return 3; /* return error */
1817 }
1818
1819 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL4, (uint8_t *)&prev, 1); /* read config */
1820 if (res != 0) /* check result */
1821 {
1822 handle->debug_print("l3gd20h: read ctrl4 failed.\n"); /* read ctrl4 failed */
1823
1824 return 1; /* return error */
1825 }
1826 prev &= ~(1 << 0); /* clear spi wire bit */
1827 prev |= spi_wire << 0; /* set spi wire */
1828
1829 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_CTRL4, (uint8_t *)&prev, 1); /* write config */
1830}
1831
1843uint8_t l3gd20h_get_spi_wire(l3gd20h_handle_t *handle, l3gd20h_spi_wire_t *spi_wire)
1844{
1845 uint8_t res, prev;
1846
1847 if (handle == NULL) /* check handle */
1848 {
1849 return 2; /* return error */
1850 }
1851 if (handle->inited != 1) /* check handle initialization */
1852 {
1853 return 3; /* return error */
1854 }
1855
1856 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL4, (uint8_t *)&prev, 1); /* read config */
1857 if (res != 0) /* check result */
1858 {
1859 handle->debug_print("l3gd20h: read ctrl4 failed.\n"); /* read ctrl4 failed */
1860
1861 return 1; /* return error */
1862 }
1863 prev &= (1 << 0); /* get spi wire bit */
1864 *spi_wire = (l3gd20h_spi_wire_t)(prev >> 0); /* get spi wire */
1865
1866 return 0; /* success return 0 */
1867}
1868
1880uint8_t l3gd20h_set_boot(l3gd20h_handle_t *handle, l3gd20h_boot_t boot)
1881{
1882 uint8_t res, prev;
1883
1884 if (handle == NULL) /* check handle */
1885 {
1886 return 2; /* return error */
1887 }
1888 if (handle->inited != 1) /* check handle initialization */
1889 {
1890 return 3; /* return error */
1891 }
1892
1893 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL5, (uint8_t *)&prev, 1); /* read config */
1894 if (res != 0) /* check result */
1895 {
1896 handle->debug_print("l3gd20h: read ctrl5 failed.\n"); /* read ctrl5 failed */
1897
1898 return 1; /* return error */
1899 }
1900 prev &= ~(1 << 7); /* clear boot */
1901 prev |= boot << 7; /* set boot */
1902
1903 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_CTRL5, (uint8_t *)&prev, 1); /* write config */
1904}
1905
1917uint8_t l3gd20h_get_boot(l3gd20h_handle_t *handle, l3gd20h_boot_t *boot)
1918{
1919 uint8_t res, prev;
1920
1921 if (handle == NULL) /* check handle */
1922 {
1923 return 2; /* return error */
1924 }
1925 if (handle->inited != 1) /* check handle initialization */
1926 {
1927 return 3; /* return error */
1928 }
1929
1930 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL5, (uint8_t *)&prev, 1); /* read config */
1931 if (res != 0) /* check result */
1932 {
1933 handle->debug_print("l3gd20h: read ctrl5 failed.\n"); /* read ctrl5 failed */
1934
1935 return 1; /* return error */
1936 }
1937 prev &= (1 << 7); /* get enable bit */
1938 *boot = (l3gd20h_boot_t)(prev >> 7); /* get bool */
1939
1940 return 0; /* success return 0 */
1941}
1942
1954uint8_t l3gd20h_set_fifo(l3gd20h_handle_t *handle, l3gd20h_bool_t enable)
1955{
1956 uint8_t res, prev;
1957
1958 if (handle == NULL) /* check handle */
1959 {
1960 return 2; /* return error */
1961 }
1962 if (handle->inited != 1) /* check handle initialization */
1963 {
1964 return 3; /* return error */
1965 }
1966
1967 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL5, (uint8_t *)&prev, 1); /* read config */
1968 if (res != 0) /* check result */
1969 {
1970 handle->debug_print("l3gd20h: read ctrl5 failed.\n"); /* read ctrl5 failed */
1971
1972 return 1; /* return error */
1973 }
1974 prev &= ~(1 << 6); /* clear enable bit */
1975 prev |= enable << 6; /* set enable */
1976
1977 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_CTRL5, (uint8_t *)&prev, 1); /* write config */
1978}
1979
1991uint8_t l3gd20h_get_fifo(l3gd20h_handle_t *handle, l3gd20h_bool_t *enable)
1992{
1993 uint8_t res, prev;
1994
1995 if (handle == NULL) /* check handle */
1996 {
1997 return 2; /* return error */
1998 }
1999 if (handle->inited != 1) /* check handle initialization */
2000 {
2001 return 3; /* return error */
2002 }
2003
2004 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL5, (uint8_t *)&prev, 1); /* read config */
2005 if (res != 0) /* check result */
2006 {
2007 handle->debug_print("l3gd20h: read ctrl5 failed.\n"); /* read ctrl5 failed */
2008
2009 return 1; /* return error */
2010 }
2011 prev &= (1 << 6); /* get enable bit */
2012 *enable = (l3gd20h_bool_t)(prev >> 6); /* get bool */
2013
2014 return 0; /* success return 0 */
2015}
2016
2028uint8_t l3gd20h_set_stop_on_fifo_threshold(l3gd20h_handle_t *handle, l3gd20h_bool_t enable)
2029{
2030 uint8_t res, prev;
2031
2032 if (handle == NULL) /* check handle */
2033 {
2034 return 2; /* return error */
2035 }
2036 if (handle->inited != 1) /* check handle initialization */
2037 {
2038 return 3; /* return error */
2039 }
2040
2041 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL5, (uint8_t *)&prev, 1); /* read config */
2042 if (res != 0) /* check result */
2043 {
2044 handle->debug_print("l3gd20h: read ctrl5 failed.\n"); /* read ctrl5 failed */
2045
2046 return 1; /* return error */
2047 }
2048 prev &= ~(1 << 5); /* clear fifo enable bit */
2049 prev |= enable << 5; /* set enable */
2050
2051 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_CTRL5, (uint8_t *)&prev, 1); /* write config */
2052}
2053
2065uint8_t l3gd20h_get_stop_on_fifo_threshold(l3gd20h_handle_t *handle, l3gd20h_bool_t *enable)
2066{
2067 uint8_t res, prev;
2068
2069 if (handle == NULL) /* check handle */
2070 {
2071 return 2; /* return error */
2072 }
2073 if (handle->inited != 1) /* check handle initialization */
2074 {
2075 return 3; /* return error */
2076 }
2077
2078 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL5, (uint8_t *)&prev, 1); /* read config */
2079 if (res != 0) /* check result */
2080 {
2081 handle->debug_print("l3gd20h: read ctrl5 failed.\n"); /* read ctrl5 failed */
2082
2083 return 1; /* return error */
2084 }
2085 prev &= (1 << 5); /* get enable bit */
2086 *enable = (l3gd20h_bool_t)(prev >> 5); /* get bool */
2087
2088 return 0; /* success return 0 */
2089}
2090
2102uint8_t l3gd20h_set_high_pass_filter(l3gd20h_handle_t *handle, l3gd20h_bool_t enable)
2103{
2104 uint8_t res, prev;
2105
2106 if (handle == NULL) /* check handle */
2107 {
2108 return 2; /* return error */
2109 }
2110 if (handle->inited != 1) /* check handle initialization */
2111 {
2112 return 3; /* return error */
2113 }
2114
2115 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL5, (uint8_t *)&prev, 1); /* read config */
2116 if (res != 0) /* check result */
2117 {
2118 handle->debug_print("l3gd20h: read ctrl5 failed.\n"); /* read ctrl5 failed */
2119
2120 return 1; /* return error */
2121 }
2122 prev &= ~(1 << 4); /* clear enable bit */
2123 prev |= enable << 4; /* set enable */
2124
2125 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_CTRL5, (uint8_t *)&prev, 1); /* write config */
2126}
2127
2139uint8_t l3gd20h_get_high_pass_filter(l3gd20h_handle_t *handle, l3gd20h_bool_t *enable)
2140{
2141 uint8_t res, prev;
2142
2143 if (handle == NULL) /* check handle */
2144 {
2145 return 2; /* return error */
2146 }
2147 if (handle->inited != 1) /* check handle initialization */
2148 {
2149 return 3; /* return error */
2150 }
2151
2152 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL5, (uint8_t *)&prev, 1); /* read config */
2153 if (res != 0) /* check result */
2154 {
2155 handle->debug_print("l3gd20h: read ctrl5 failed.\n"); /* read ctrl5 failed */
2156
2157 return 1; /* return error */
2158 }
2159 prev &= (1 << 4); /* get enable bit */
2160 *enable = (l3gd20h_bool_t)(prev >> 4); /* get bool */
2161
2162 return 0; /* success return 0 */
2163}
2164
2176uint8_t l3gd20h_set_interrupt_selection(l3gd20h_handle_t *handle, l3gd20h_selection_t selection)
2177{
2178 uint8_t res, prev;
2179
2180 if (handle == NULL) /* check handle */
2181 {
2182 return 2; /* return error */
2183 }
2184 if (handle->inited != 1) /* check handle initialization */
2185 {
2186 return 3; /* return error */
2187 }
2188
2189 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL5, (uint8_t *)&prev, 1); /* read config */
2190 if (res != 0) /* check result */
2191 {
2192 handle->debug_print("l3gd20h: read ctrl5 failed.\n"); /* read ctrl5 failed */
2193
2194 return 1; /* return error */
2195 }
2196 prev &= ~(3 << 2); /* clear selection */
2197 prev |= selection << 2; /* set selection */
2198
2199 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_CTRL5, (uint8_t *)&prev, 1); /* write config */
2200}
2201
2213uint8_t l3gd20h_get_interrupt_selection(l3gd20h_handle_t *handle, l3gd20h_selection_t *selection)
2214{
2215 uint8_t res, prev;
2216
2217 if (handle == NULL) /* check handle */
2218 {
2219 return 2; /* return error */
2220 }
2221 if (handle->inited != 1) /* check handle initialization */
2222 {
2223 return 3; /* return error */
2224 }
2225
2226 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL5, (uint8_t *)&prev, 1); /* read config */
2227 if (res != 0) /* check result */
2228 {
2229 handle->debug_print("l3gd20h: read ctrl5 failed.\n"); /* read ctrl5 failed */
2230
2231 return 1; /* return error */
2232 }
2233 prev &= (3 << 2); /* get the selection bits */
2234 *selection = (l3gd20h_selection_t)(prev >> 2); /* get the selection */
2235
2236 return 0; /* success return 0 */
2237}
2238
2250uint8_t l3gd20h_set_out_selection(l3gd20h_handle_t *handle, l3gd20h_selection_t selection)
2251{
2252 uint8_t res, prev;
2253
2254 if (handle == NULL) /* check handle */
2255 {
2256 return 2; /* return error */
2257 }
2258 if (handle->inited != 1) /* check handle initialization */
2259 {
2260 return 3; /* return error */
2261 }
2262
2263 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL5, (uint8_t *)&prev, 1); /* read config */
2264 if (res != 0) /* check result */
2265 {
2266 handle->debug_print("l3gd20h: read ctrl5 failed.\n"); /* read ctrl5 failed */
2267
2268 return 1; /* return error */
2269 }
2270 prev &= ~(3 << 0); /* clear the selection bits */
2271 prev |= selection << 0; /* get the selection */
2272
2273 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_CTRL5, (uint8_t *)&prev, 1); /* write config */
2274}
2275
2287uint8_t l3gd20h_get_out_selection(l3gd20h_handle_t *handle, l3gd20h_selection_t *selection)
2288{
2289 uint8_t res, prev;
2290
2291 if (handle == NULL) /* check handle */
2292 {
2293 return 2; /* return error */
2294 }
2295 if (handle->inited != 1) /* check handle initialization */
2296 {
2297 return 3; /* return error */
2298 }
2299
2300 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL5, (uint8_t *)&prev, 1); /* read config */
2301 if (res != 0) /* check result */
2302 {
2303 handle->debug_print("l3gd20h: read ctrl5 failed.\n"); /* read ctrl5 failed */
2304
2305 return 1; /* return error */
2306 }
2307 prev &= (3 << 0); /* get the selection bits */
2308 *selection = (l3gd20h_selection_t)(prev >> 0); /* get the selection */
2309
2310 return 0; /* success return 0 */
2311}
2312
2324uint8_t l3gd20h_set_high_pass_filter_reference(l3gd20h_handle_t *handle, uint8_t value)
2325{
2326 if (handle == NULL) /* check handle */
2327 {
2328 return 2; /* return error */
2329 }
2330 if (handle->inited != 1) /* check handle initialization */
2331 {
2332 return 3; /* return error */
2333 }
2334
2335 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_REFERENCE, (uint8_t *)&value, 1); /* write config */
2336}
2337
2349uint8_t l3gd20h_get_high_pass_filter_reference(l3gd20h_handle_t *handle, uint8_t *value)
2350{
2351 if (handle == NULL) /* check handle */
2352 {
2353 return 2; /* return error */
2354 }
2355 if (handle->inited != 1) /* check handle initialization */
2356 {
2357 return 3; /* return error */
2358 }
2359
2360 return a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_REFERENCE, (uint8_t *)value, 1); /* read config */
2361}
2362
2375uint8_t l3gd20h_read_temperature(l3gd20h_handle_t *handle, int8_t *raw, float *temp)
2376{
2377 uint8_t res;
2378
2379 if (handle == NULL) /* check handle */
2380 {
2381 return 2; /* return error */
2382 }
2383 if (handle->inited != 1) /* check handle initialization */
2384 {
2385 return 3; /* return error */
2386 }
2387
2388 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_OUT_TEMP, (uint8_t *)raw, 1); /* read data */
2389 if (res != 0) /* check result */
2390 {
2391 handle->debug_print("l3gd20h: read temperature failed.\n"); /* read temperature failed */
2392
2393 return 1; /* return error */
2394 }
2395 *temp = (float)(*raw) * (-1.0f) + 25.0f; /* convert the raw data */
2396
2397 return 0; /* success return 0 */
2398}
2399
2411uint8_t l3gd20h_get_status(l3gd20h_handle_t *handle, uint8_t *status)
2412{
2413 if (handle == NULL) /* check handle */
2414 {
2415 return 2; /* return error */
2416 }
2417 if (handle->inited != 1) /* check handle initialization */
2418 {
2419 return 3; /* return error */
2420 }
2421
2422 return a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_STATUS, (uint8_t *)status, 1); /* read config */
2423}
2424
2436uint8_t l3gd20h_set_fifo_mode(l3gd20h_handle_t *handle, l3gd20h_fifo_mode_t fifo_mode)
2437{
2438 uint8_t res, prev;
2439
2440 if (handle == NULL) /* check handle */
2441 {
2442 return 2; /* return error */
2443 }
2444 if (handle->inited != 1) /* check handle initialization */
2445 {
2446 return 3; /* return error */
2447 }
2448
2449 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_FIFO_CTRL, (uint8_t *)&prev, 1); /* read config */
2450 if (res != 0) /* check result */
2451 {
2452 handle->debug_print("l3gd20h: read fifo ctrl failed.\n"); /* read fifo ctrl failed */
2453
2454 return 1; /* return error */
2455 }
2456 prev &= ~(7 << 5);
2457 prev |= fifo_mode << 5; /* clear fifo mode bits */
2458 /* set fifo mode */
2459 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_FIFO_CTRL, (uint8_t *)&prev, 1); /* write config */
2460}
2461
2473uint8_t l3gd20h_get_fifo_mode(l3gd20h_handle_t *handle, l3gd20h_fifo_mode_t *fifo_mode)
2474{
2475 uint8_t res, prev;
2476
2477 if (handle == NULL) /* check handle */
2478 {
2479 return 2; /* return error */
2480 }
2481 if (handle->inited != 1) /* check handle initialization */
2482 {
2483 return 3; /* return error */
2484 }
2485
2486 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_FIFO_CTRL, (uint8_t *)&prev, 1); /* read config */
2487 if (res != 0) /* check result */
2488 {
2489 handle->debug_print("l3gd20h: read fifo ctrl failed.\n"); /* read fifo ctrl failed */
2490
2491 return 1; /* return error */
2492 }
2493 prev &= (7 << 5); /* get fifo mode bits */
2494 *fifo_mode = (l3gd20h_fifo_mode_t)(prev >> 5); /* get fifo mode */
2495
2496 return 0; /* success return 0 */
2497}
2498
2511uint8_t l3gd20h_set_fifo_threshold(l3gd20h_handle_t *handle, uint8_t threshold)
2512{
2513 uint8_t res, prev;
2514
2515 if (handle == NULL) /* check handle */
2516 {
2517 return 2; /* return error */
2518 }
2519 if (handle->inited != 1) /* check handle initialization */
2520 {
2521 return 3; /* return error */
2522 }
2523
2524 if (threshold > 31) /* check the threshold */
2525 {
2526 handle->debug_print("l3gd20h: threshold is invalid.\n"); /* threshold is invalid */
2527
2528 return 4; /* return error */
2529 }
2530 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_FIFO_CTRL, (uint8_t *)&prev, 1); /* read config */
2531 if (res != 0) /* check result */
2532 {
2533 handle->debug_print("l3gd20h: read fifo ctrl failed.\n"); /* read fifo ctrl failed */
2534
2535 return 1; /* return error */
2536 }
2537 prev &= ~(0x1F); /* clear the threshold bits */
2538 prev |= threshold; /* set the threshold */
2539
2540 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_FIFO_CTRL, (uint8_t *)&prev, 1); /* write config */
2541}
2542
2554uint8_t l3gd20h_get_fifo_threshold(l3gd20h_handle_t *handle, uint8_t *threshold)
2555{
2556 uint8_t res, prev;
2557
2558 if (handle == NULL) /* check handle */
2559 {
2560 return 2; /* return error */
2561 }
2562 if (handle->inited != 1) /* check handle initialization */
2563 {
2564 return 3; /* return error */
2565 }
2566
2567 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_FIFO_CTRL, (uint8_t *)&prev, 1); /* read config */
2568 if (res != 0) /* check result */
2569 {
2570 handle->debug_print("l3gd20h: read fifo ctrl failed.\n"); /* read fifo ctrl failed */
2571
2572 return 1; /* return error */
2573 }
2574 prev &= (0x1F); /* get threshold bits */
2575 *threshold = prev; /* set threshold */
2576
2577 return 0; /* success return 0 */
2578}
2579
2591uint8_t l3gd20h_get_fifo_level(l3gd20h_handle_t *handle, uint8_t *level)
2592{
2593 uint8_t res, prev;
2594
2595 if (handle == NULL) /* check handle */
2596 {
2597 return 2; /* return error */
2598 }
2599 if (handle->inited != 1) /* check handle initialization */
2600 {
2601 return 3; /* return error */
2602 }
2603
2604 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_FIFO_SRC, (uint8_t *)&prev, 1); /* read config */
2605 if (res != 0) /* check result */
2606 {
2607 handle->debug_print("l3gd20h: read fifo src failed.\n"); /* read fifo src failed */
2608
2609 return 1; /* return error */
2610 }
2611 prev &= (0x1F); /* get level bits */
2612 *level = prev; /* get level */
2613
2614 return 0; /* success return 0 */
2615}
2616
2629uint8_t l3gd20h_set_interrupt_event(l3gd20h_handle_t *handle, l3gd20h_interrupt_event_t interrupt_event, l3gd20h_bool_t enable)
2630{
2631 uint8_t res, prev;
2632
2633 if (handle == NULL) /* check handle */
2634 {
2635 return 2; /* return error */
2636 }
2637 if (handle->inited != 1) /* check handle initialization */
2638 {
2639 return 3; /* return error */
2640 }
2641
2642 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_IG_CFG, (uint8_t *)&prev, 1); /* read config */
2643 if (res != 0) /* check result */
2644 {
2645 handle->debug_print("l3gd20h: read interrupt cfg failed.\n"); /* read interrupt cfg failed */
2646
2647 return 1; /* return error */
2648 }
2649 prev &= ~(1 << interrupt_event); /* clear event bit */
2650 prev |= enable << interrupt_event; /* set event bit */
2651
2652 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_IG_CFG, (uint8_t *)&prev, 1); /* write config */
2653}
2654
2667uint8_t l3gd20h_get_interrupt_event(l3gd20h_handle_t *handle, l3gd20h_interrupt_event_t interrupt_event, l3gd20h_bool_t *enable)
2668{
2669 uint8_t res, prev;
2670
2671 if (handle == NULL) /* check handle */
2672 {
2673 return 2; /* return error */
2674 }
2675 if (handle->inited != 1) /* check handle initialization */
2676 {
2677 return 3; /* return error */
2678 }
2679
2680 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_IG_CFG, (uint8_t *)&prev, 1); /* read config */
2681 if (res != 0) /* check result */
2682 {
2683 handle->debug_print("l3gd20h: read interrupt cfg failed.\n"); /* read interrupt cfg failed */
2684
2685 return 1; /* return error */
2686 }
2687 prev &= (1 << interrupt_event); /* get interrupt bit */
2688 *enable = (l3gd20h_bool_t)(prev >> interrupt_event); /* get interrupt */
2689
2690 return 0; /* success return 0 */
2691}
2692
2704uint8_t l3gd20h_get_interrupt_source(l3gd20h_handle_t *handle, uint8_t *src)
2705{
2706 uint8_t res;
2707
2708 if (handle == NULL) /* check handle */
2709 {
2710 return 2; /* return error */
2711 }
2712 if (handle->inited != 1) /* check handle initialization */
2713 {
2714 return 3; /* return error */
2715 }
2716
2717 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_IG_SRC, (uint8_t *)src, 1); /* read config */
2718 if (res != 0) /* check result */
2719 {
2720 handle->debug_print("l3gd20h: read interrupt source failed.\n"); /* read interrupt source failed */
2721
2722 return 1; /* return error */
2723 }
2724
2725 return 0; /* success return 0 */
2726}
2727
2740uint8_t l3gd20h_set_x_interrupt_threshold(l3gd20h_handle_t *handle, uint16_t threshold)
2741{
2742 uint8_t res;
2743 uint8_t buf[2];
2744
2745 if (handle == NULL) /* check handle */
2746 {
2747 return 2; /* return error */
2748 }
2749 if (handle->inited != 1) /* check handle initialization */
2750 {
2751 return 3; /* return error */
2752 }
2753 if (threshold > 0x8000U) /* check the threshold */
2754 {
2755 handle->debug_print("l3gd20h: threshold is invalid.\n"); /* threshold is invalid */
2756
2757 return 4; /* return error */
2758 }
2759
2760 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_IG_THS_XH, (uint8_t *)buf, 1); /* read x interrupt threshold */
2761 if (res != 0) /* check result */
2762 {
2763 handle->debug_print("l3gd20h: read x interrupt threshold failed.\n"); /* read x interrupt threshold failed */
2764
2765 return 1; /* return error */
2766 }
2767 buf[0] = buf[0] | ((threshold >> 8) & 0x7F); /* set threshold high */
2768 buf[1] = (threshold) & 0xFF; /* set threshold low*/
2769
2770 res = a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_IG_THS_XH, (uint8_t *)&buf[0], 1); /* write config */
2771 if (res != 0) /* check result */
2772 {
2773 handle->debug_print("l3gd20h: write x interrupt high threshold failed.\n"); /* write x interrupt high threshold failed */
2774
2775 return 1; /* return error */
2776 }
2777
2778 res = a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_IG_THS_XL, (uint8_t *)&buf[1], 1); /* write config */
2779 if (res != 0) /* check result */
2780 {
2781 handle->debug_print("l3gd20h: write x interrupt low threshold failed.\n"); /* write x interrupt low threshold failed */
2782
2783 return 1; /* return error */
2784 }
2785
2786 return 0; /* success return 0 */
2787}
2788
2800uint8_t l3gd20h_get_x_interrupt_threshold(l3gd20h_handle_t *handle, uint16_t *threshold)
2801{
2802 uint8_t buf[2];
2803
2804 if (handle == NULL) /* check handle */
2805 {
2806 return 2; /* return error */
2807 }
2808 if (handle->inited != 1) /* check handle initialization */
2809 {
2810 return 3; /* return error */
2811 }
2812
2813 if (a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_IG_THS_XH, (uint8_t *)&buf[0], 1) != 0) /* read x interrupt high threshold */
2814 {
2815 handle->debug_print("l3gd20h: read x interrupt high threshold failed.\n"); /* read x interrupt high threshold failed */
2816
2817 return 1; /* return error */
2818 }
2819 if (a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_IG_THS_XL, (uint8_t *)&buf[1], 1) != 0) /* read x interrupt low threshold */
2820 {
2821 handle->debug_print("l3gd20h: read x interrupt low threshold failed.\n"); /* read x interrupt low threshold failed */
2822
2823 return 1; /* return error */
2824 }
2825 *threshold = (uint16_t)((uint16_t)buf[0] << 8) | buf[1]; /* get the threshold */
2826 *threshold &= ~(1 << 15); /* clear the 15th bit */
2827
2828 return 0; /* success return 0 */
2829}
2830
2843uint8_t l3gd20h_set_y_interrupt_threshold(l3gd20h_handle_t *handle, uint16_t threshold)
2844{
2845 uint8_t res;
2846 uint8_t buf[2];
2847
2848 if (handle == NULL) /* check handle */
2849 {
2850 return 2; /* return error */
2851 }
2852 if (handle->inited != 1) /* check handle initialization */
2853 {
2854 return 3; /* return error */
2855 }
2856 if (threshold > 0x8000U) /* check the threshold */
2857 {
2858 handle->debug_print("l3gd20h: threshold is invalid.\n"); /* threshold is invalid */
2859
2860 return 4; /* return error */
2861 }
2862
2863 buf[0] = (threshold >> 8) & 0xFF; /* set the high threshold */
2864 buf[1] = (threshold) & 0xFF; /* set the low threshold */
2865
2866 res = a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_IG_THS_YH, (uint8_t *)&buf[0], 1); /* write the config */
2867 if (res != 0) /* check result */
2868 {
2869 handle->debug_print("l3gd20h: write y interrupt high threshold failed.\n"); /* write y interrupt high threshold failed */
2870
2871 return 1; /* return error */
2872 }
2873 res = a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_IG_THS_YL, (uint8_t *)&buf[1], 1); /* write the config */
2874 if (res != 0) /* check result */
2875 {
2876 handle->debug_print("l3gd20h: write y interrupt low threshold failed.\n"); /* write y interrupt low threshold failed */
2877
2878 return 1; /* return error */
2879 }
2880
2881 return 0; /* success return 0 */
2882}
2883
2895uint8_t l3gd20h_get_y_interrupt_threshold(l3gd20h_handle_t *handle, uint16_t *threshold)
2896{
2897 uint8_t buf[2];
2898
2899 if (handle == NULL) /* check handle */
2900 {
2901 return 2; /* return error */
2902 }
2903 if (handle->inited != 1) /* check handle initialization */
2904 {
2905 return 3; /* return error */
2906 }
2907
2908 if (a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_IG_THS_YH, (uint8_t *)&buf[0], 1) != 0) /* read y interrupt high threshold */
2909 {
2910 handle->debug_print("l3gd20h: read y interrupt high threshold failed.\n"); /* read y interrupt high threshold failed */
2911
2912 return 1; /* return error */
2913 }
2914 if (a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_IG_THS_YL, (uint8_t *)&buf[1], 1) != 0) /* read y interrupt low threshold */
2915 {
2916 handle->debug_print("l3gd20h: read y interrupt low threshold failed.\n"); /* read y interrupt low threshold failed */
2917
2918 return 1; /* return error */
2919 }
2920 *threshold = (uint16_t)(buf[0] << 8) | buf[1]; /* get the threshold */
2921 *threshold &= ~(1 << 15); /* clear the 15th bit */
2922
2923 return 0; /* success return 0 */
2924}
2925
2938uint8_t l3gd20h_set_z_interrupt_threshold(l3gd20h_handle_t *handle, uint16_t threshold)
2939{
2940 uint8_t res;
2941 uint8_t buf[2];
2942
2943 if (handle == NULL) /* check handle */
2944 {
2945 return 2; /* return error */
2946 }
2947 if (handle->inited != 1) /* check handle initialization */
2948 {
2949 return 3; /* return error */
2950 }
2951 if (threshold > 0x8000U) /* check the threshold */
2952 {
2953 handle->debug_print("l3gd20h: threshold is invalid.\n"); /* threshold is invalid */
2954
2955 return 4; /* return error */
2956 }
2957
2958 buf[0] = (threshold >> 8) & 0xFF; /* set the high threshold */
2959 buf[1] = (threshold) & 0xFF; /* set the low threshold */
2960
2961 res = a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_IG_THS_ZH, (uint8_t *)&buf[0], 1); /* write config */
2962 if (res != 0) /* check result */
2963 {
2964 handle->debug_print("l3gd20h: write z interrupt high threshold failed.\n"); /* write z interrupt high threshold failed */
2965
2966 return 1; /* return error */
2967 }
2968 res = a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_IG_THS_ZL, (uint8_t *)&buf[1], 1); /* write config */
2969 if (res != 0) /* check result */
2970 {
2971 handle->debug_print("l3gd20h: write z interrupt low threshold failed.\n"); /* write z interrupt low threshold failed */
2972
2973 return 1; /* return error */
2974 }
2975
2976 return 0; /* success return 0 */
2977}
2978
2990uint8_t l3gd20h_get_z_interrupt_threshold(l3gd20h_handle_t *handle, uint16_t *threshold)
2991{
2992 uint8_t buf[2];
2993
2994 if (handle == NULL) /* check handle */
2995 {
2996 return 2; /* return error */
2997 }
2998 if (handle->inited != 1) /* check handle initialization */
2999 {
3000 return 3; /* return error */
3001 }
3002
3003 if (a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_IG_THS_ZH, (uint8_t *)&buf[0], 1) != 0) /* read the config */
3004 {
3005 handle->debug_print("l3gd20h: read z interrupt high threshold failed.\n"); /* read z interrupt high threshold failed */
3006
3007 return 1; /* return error */
3008 }
3009 if (a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_IG_THS_ZL, (uint8_t *)&buf[1], 1) != 0) /* read the config */
3010 {
3011 handle->debug_print("l3gd20h: read z interrupt low threshold failed.\n"); /* read z interrupt low threshold failed */
3012
3013 return 1; /* return error */
3014 }
3015 *threshold = (uint16_t)((uint16_t)buf[0] << 8) | buf[1]; /* get the threshold */
3016 *threshold &= ~(1 << 15); /* clear the 15th bit */
3017
3018 return 0; /* success return 0 */
3019}
3020
3032uint8_t l3gd20h_set_counter_mode(l3gd20h_handle_t *handle, l3gd20h_counter_mode_t counter_mode)
3033{
3034 uint8_t res, prev;
3035
3036 if (handle == NULL) /* check handle */
3037 {
3038 return 2; /* return error */
3039 }
3040 if (handle->inited != 1) /* check handle initialization */
3041 {
3042 return 3; /* return error */
3043 }
3044
3045 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_IG_THS_XH, (uint8_t *)&prev, 1); /* read config */
3046 if (res != 0) /* check result */
3047 {
3048 handle->debug_print("l3gd20h: read x interrupt threshold failed.\n"); /* read x interrupt threshold failed */
3049
3050 return 1; /* return error */
3051 }
3052 prev &= ~(1 << 7); /* clear the counter mode bit */
3053 prev |= counter_mode << 7; /* set the counter mode */
3054
3055 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_IG_THS_XH, (uint8_t *)&prev, 1); /* write config */
3056}
3057
3069uint8_t l3gd20h_get_counter_mode(l3gd20h_handle_t *handle, l3gd20h_counter_mode_t *counter_mode)
3070{
3071 uint8_t res, prev;
3072
3073 if (handle == NULL) /* check handle */
3074 {
3075 return 2; /* return error */
3076 }
3077 if (handle->inited != 1) /* check handle initialization */
3078 {
3079 return 3; /* return error */
3080 }
3081
3082 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_IG_THS_XH, (uint8_t *)&prev, 1); /* read config */
3083 if (res != 0) /* check result */
3084 {
3085 handle->debug_print("l3gd20h: read x interrupt threshold failed.\n"); /* read x interrupt threshold failed */
3086
3087 return 1; /* return error */
3088 }
3089 prev &= (1 << 7); /* get the counter mode bit */
3090 *counter_mode = (l3gd20h_counter_mode_t)(prev >> 7); /* get the counter mode */
3091
3092 return 0; /* success return 0 */
3093}
3094
3106uint8_t l3gd20h_set_wait(l3gd20h_handle_t *handle, l3gd20h_bool_t enable)
3107{
3108 uint8_t res, prev;
3109
3110 if (handle == NULL) /* check handle */
3111 {
3112 return 2; /* return error */
3113 }
3114 if (handle->inited != 1) /* check handle initialization */
3115 {
3116 return 3; /* return error */
3117 }
3118
3119 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_IG_DURATION, (uint8_t *)&prev, 1); /* read config */
3120 if (res != 0) /* check result */
3121 {
3122 handle->debug_print("l3gd20h: read duration failed.\n"); /* read duration failed */
3123
3124 return 1; /* return error */
3125 }
3126 prev &= ~(1 << 7); /* clear enable bit */
3127 prev |= enable << 7; /* set enable */
3128
3129 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_IG_DURATION, (uint8_t *)&prev, 1); /* write config */
3130}
3131
3143uint8_t l3gd20h_get_wait(l3gd20h_handle_t *handle, l3gd20h_bool_t *enable)
3144{
3145 uint8_t res, prev;
3146
3147 if (handle == NULL) /* check handle */
3148 {
3149 return 2; /* return error */
3150 }
3151 if (handle->inited != 1) /* check handle initialization */
3152 {
3153 return 3; /* return error */
3154 }
3155
3156 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_IG_DURATION, (uint8_t *)&prev, 1); /* read config */
3157 if (res != 0) /* check result */
3158 {
3159 handle->debug_print("l3gd20h: read duration failed.\n"); /* read duration failed */
3160
3161 return 1; /* return error */
3162 }
3163 prev &= (1 << 7); /* get the wait bit */
3164 *enable = (l3gd20h_bool_t)(prev >> 7); /* get bool */
3165
3166 return 0; /* success return 0 */
3167}
3168
3180uint8_t l3gd20h_set_duration(l3gd20h_handle_t *handle, uint8_t duration)
3181{
3182 uint8_t res, prev;
3183
3184 if (handle == NULL) /* check handle */
3185 {
3186 return 2; /* return error */
3187 }
3188 if (handle->inited != 1) /* check handle initialization */
3189 {
3190 return 3; /* return error */
3191 }
3192 if (duration > 0x7F) /* check the duration */
3193 {
3194 handle->debug_print("l3gd20h: duration is over 0x7F.\n"); /* duration is over 0x7F */
3195
3196 return 1; /* return error */
3197 }
3198
3199 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_IG_DURATION, (uint8_t *)&prev, 1); /* read config */
3200 if (res != 0) /* check result */
3201 {
3202 handle->debug_print("l3gd20h: read duration failed.\n"); /* read duration failed */
3203
3204 return 1; /* return error */
3205 }
3206 prev |= duration & 0x7F; /* set the duration */
3207
3208 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_IG_DURATION, (uint8_t *)&prev, 1); /* write config */
3209}
3210
3222uint8_t l3gd20h_get_duration(l3gd20h_handle_t *handle, uint8_t *duration)
3223{
3224 uint8_t res, prev;
3225
3226 if (handle == NULL) /* check handle */
3227 {
3228 return 2; /* return error */
3229 }
3230 if (handle->inited != 1) /* check handle initialization */
3231 {
3232 return 3; /* return error */
3233 }
3234
3235 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_IG_DURATION, (uint8_t *)&prev, 1); /* read config */
3236 if (res != 0) /* check result */
3237 {
3238 handle->debug_print("l3gd20h: read duration failed.\n"); /* read duration failed */
3239
3240 return 1; /* return error */
3241 }
3242 prev &= 0x7F; /* get duration bits */
3243 *duration = prev; /* get duration */
3244
3245 return 0; /* success return 0 */
3246}
3247
3259uint8_t l3gd20h_set_data_ready_active_level(l3gd20h_handle_t *handle, l3gd20h_interrupt_active_level_t level)
3260{
3261 uint8_t res, prev;
3262
3263 if (handle == NULL) /* check handle */
3264 {
3265 return 2; /* return error */
3266 }
3267 if (handle->inited != 1) /* check handle initialization */
3268 {
3269 return 3; /* return error */
3270 }
3271
3272 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_LOW_ODR, (uint8_t *)&prev, 1); /* read config */
3273 if (res != 0) /* check result */
3274 {
3275 handle->debug_print("l3gd20h: read low odr failed.\n"); /* read low odr failed */
3276
3277 return 1; /* return error */
3278 }
3279 prev &= ~(1 << 5); /* clear level bit */
3280 prev |= level << 5; /* set level */
3281
3282 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_LOW_ODR, (uint8_t *)&prev, 1); /* write config */
3283}
3284
3296uint8_t l3gd20h_get_data_ready_active_level(l3gd20h_handle_t *handle, l3gd20h_interrupt_active_level_t *level)
3297{
3298 uint8_t res, prev;
3299
3300 if (handle == NULL) /* check handle */
3301 {
3302 return 2; /* return error */
3303 }
3304 if (handle->inited != 1) /* check handle initialization */
3305 {
3306 return 3; /* return error */
3307 }
3308
3309 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_LOW_ODR, (uint8_t *)&prev, 1); /* read config */
3310 if (res != 0) /* check result */
3311 {
3312 handle->debug_print("l3gd20h: read low odr failed.\n"); /* return error */
3313
3314 return 1; /* return error */
3315 }
3316 prev &= (1 << 5); /* get pin level bit */
3317 *level = (l3gd20h_interrupt_active_level_t)(prev >> 5); /* get pin level */
3318
3319 return 0; /* success return 0 */
3320}
3321
3333uint8_t l3gd20h_set_iic(l3gd20h_handle_t *handle, l3gd20h_bool_t enable)
3334{
3335 uint8_t res, prev;
3336
3337 if (handle == NULL) /* check handle */
3338 {
3339 return 2; /* return error */
3340 }
3341 if (handle->inited != 1) /* check handle initialization */
3342 {
3343 return 3; /* return error */
3344 }
3345
3346 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_LOW_ODR, (uint8_t *)&prev, 1); /* read config */
3347 if (res != 0) /* check result */
3348 {
3349 handle->debug_print("l3gd20h: read low odr failed.\n"); /* read low odr failed */
3350
3351 return 1; /* return error */
3352 }
3353 prev &= ~(1 << 3); /* clear enable bit */
3354 prev |= enable << 3; /* set enable */
3355
3356 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_LOW_ODR, (uint8_t *)&prev, 1); /* write config */
3357}
3358
3370uint8_t l3gd20h_get_iic(l3gd20h_handle_t *handle, l3gd20h_bool_t *enable)
3371{
3372 uint8_t res, prev;
3373
3374 if (handle == NULL) /* check handle */
3375 {
3376 return 2; /* return error */
3377 }
3378 if (handle->inited != 1) /* check handle initialization */
3379 {
3380 return 3; /* return error */
3381 }
3382
3383 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_LOW_ODR, (uint8_t *)&prev, 1); /* read config */
3384 if (res != 0) /* check result */
3385 {
3386 handle->debug_print("l3gd20h: read low odr failed.\n"); /* read low odr failed */
3387
3388 return 1; /* return error */
3389 }
3390 prev &= (1 << 3); /* get enable bit */
3391 *enable = (l3gd20h_bool_t)(prev >> 3); /* get bool */
3392
3393 return 0; /* success return 0 */
3394}
3395
3406uint8_t l3gd20h_soft_reset(l3gd20h_handle_t *handle)
3407{
3408 uint8_t res, prev;
3409
3410 if (handle == NULL) /* check handle */
3411 {
3412 return 2; /* return error */
3413 }
3414 if (handle->inited != 1) /* check handle initialization */
3415 {
3416 return 3; /* return error */
3417 }
3418
3419 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_LOW_ODR, (uint8_t *)&prev, 1); /* read config */
3420 if (res != 0) /* check result */
3421 {
3422 handle->debug_print("l3gd20h: read low odr failed.\n"); /* read low odr failed */
3423
3424 return 1; /* return error */
3425 }
3426 prev &= ~(1 << 2); /* clear reset bit */
3427 prev |= 1 << 2; /* set reset bit */
3428
3429 return a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_LOW_ODR, (uint8_t *)&prev, 1); /* write config */
3430}
3431
3444uint8_t l3gd20h_interrupt_threshold_convert_to_register(l3gd20h_handle_t *handle, float dps, uint16_t *reg)
3445{
3446 uint8_t range, prev;
3447
3448 if (handle == NULL) /* check handle */
3449 {
3450 return 2; /* return error */
3451 }
3452 if (handle->inited != 1) /* check handle initialization */
3453 {
3454 return 3; /* return error */
3455 }
3456
3457 if (a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL4, (uint8_t *)&prev, 1) != 0) /* read config */
3458 {
3459 handle->debug_print("l3gd20h: read ctrl4 failed.\n"); /* read ctrl4 failed */
3460
3461 return 1; /* return error */
3462 }
3463 range = (prev & (3 << 4)) >> 4; /* get range */
3464 if (range == 0)
3465 {
3466 *reg = (uint16_t)(dps * 1000.0f / 7.5f); /* convert */
3467 }
3468 else if (range == 1)
3469 {
3470 *reg = (uint16_t)(dps * 1000.0f / 15.3f); /* convert */
3471 }
3472 else
3473 {
3474 *reg = (uint16_t)(dps * 1000.0f / 61.0f); /* convert */
3475 }
3476
3477 return 0; /* success return 0 */
3478}
3479
3492uint8_t l3gd20h_interrupt_threshold_convert_to_data(l3gd20h_handle_t *handle, uint16_t reg, float *dps)
3493{
3494 uint8_t range, prev;
3495
3496 if (handle == NULL) /* check handle */
3497 {
3498 return 2; /* return error */
3499 }
3500 if (handle->inited != 1) /* check handle initialization */
3501 {
3502 return 3; /* return error */
3503 }
3504
3505 if (a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL4, (uint8_t *)&prev, 1) != 0) /* read config */
3506 {
3507 handle->debug_print("l3gd20h: read ctrl4 failed.\n"); /* read ctrl4 failed */
3508
3509 return 1; /* return error */
3510 }
3511 range = (prev & (3 << 4)) >> 4; /* get range */
3512 if (range == 0)
3513 {
3514 *dps = (float)(reg * 8.75f / 1000.0f); /* convert */
3515 }
3516 else if (range == 1)
3517 {
3518 *dps = (float)(reg * 17.50f / 1000.0f); /* convert */
3519 }
3520 else
3521 {
3522 *dps = (float)(reg * 70.0f / 1000.0f); /* convert */
3523 }
3524
3525 return 0; /* success return 0 */
3526}
3527
3539uint8_t l3gd20h_irq_handler(l3gd20h_handle_t *handle, uint8_t num)
3540{
3541 uint8_t res, prev;
3542
3543 if (handle == NULL) /* check handle */
3544 {
3545 return 2; /* return error */
3546 }
3547 if (handle->inited != 1) /* check handle initialization */
3548 {
3549 return 3; /* return error */
3550 }
3551
3552 if (num == 1) /* interrupt 1 */
3553 {
3554 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_IG_SRC, (uint8_t *)&prev, 1); /* read config */
3555 if (res != 0) /* check result */
3556 {
3557 handle->debug_print("l3gd20h: read interrupt source failed.\n"); /* read interrupt source failed */
3558
3559 return 1; /* return error */
3560 }
3561 if ((prev & (1 << 6)) != 0) /* check active */
3562 {
3563 if (handle->receive_callback != NULL) /* receive callback is valid */
3564 {
3565 handle->receive_callback(L3GD20H_INTERRUPT1_INTERRUPT_ACTIVE); /* run receive callback */
3566 }
3567 }
3568 if ((prev & (1 << 5)) != 0) /* check z high */
3569 {
3570 if (handle->receive_callback != NULL) /* receive callback is valid */
3571 {
3572 handle->receive_callback(L3GD20H_INTERRUPT1_Z_HIGH); /* run receive callback */
3573 }
3574 }
3575 if ((prev & (1 << 4)) != 0) /* check z low */
3576 {
3577 if (handle->receive_callback != NULL) /* receive callback is valid */
3578 {
3579 handle->receive_callback(L3GD20H_INTERRUPT1_Z_LOW); /* run receive callback */
3580 }
3581 }
3582 if ((prev & (1 << 3)) != 0) /* check y high */
3583 {
3584 if (handle->receive_callback != NULL) /* receive callback is valid */
3585 {
3586 handle->receive_callback(L3GD20H_INTERRUPT1_Y_HIGH); /* run receive callback */
3587 }
3588 }
3589 if ((prev & (1 << 2)) != 0) /* check y low */
3590 { /* check y low */
3591 if (handle->receive_callback != NULL) /* receive callback is valid */
3592 {
3593 handle->receive_callback(L3GD20H_INTERRUPT1_Y_LOW); /* run receive callback */
3594 }
3595 }
3596 if ((prev & (1 << 1)) != 0) /* check x high */
3597 {
3598 if (handle->receive_callback != NULL) /* receive callback is valid */
3599 {
3600 handle->receive_callback(L3GD20H_INTERRUPT1_X_HIGH); /* run receive callback */
3601 }
3602 }
3603 if ((prev & (1 << 0)) != 0) /* check x low */
3604 {
3605 if (handle->receive_callback != NULL) /* receive callback is valid */
3606 {
3607 handle->receive_callback(L3GD20H_INTERRUPT1_X_LOW); /* run receive callback */
3608 }
3609 }
3610
3611 return 0; /* success return 0 */
3612 }
3613 else if (num == 2) /* interrupt 2 */
3614 {
3615 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_STATUS, (uint8_t *)&prev, 1); /* read config */
3616 if (res != 0) /* check result */
3617 {
3618 handle->debug_print("l3gd20h: read status failed.\n"); /* read status failed */
3619
3620 return 1; /* return error */
3621 }
3622 if ((prev & (1 << L3GD20H_STATUS_XYZ_OVERRUN)) != 0) /* check status xyz overrun */
3623 {
3624 if (handle->receive_callback != NULL) /* receive callback is valid */
3625 {
3626 handle->receive_callback(L3GD20H_INTERRUPT2_XYZ_OVERRUN); /* run receive callback */
3627 }
3628 }
3629 if ((prev & (1 << L3GD20H_STATUS_Z_OVERRUN)) != 0) /* check status z overrun */
3630 {
3631 if (handle->receive_callback != NULL) /* receive callback is valid */
3632 {
3633 handle->receive_callback(L3GD20H_INTERRUPT2_Z_OVERRUN); /* run receive callback */
3634 }
3635 }
3636 if ((prev & (1 << L3GD20H_STATUS_Y_OVERRUN)) != 0) /* check status y overrun */
3637 {
3638 if (handle->receive_callback != NULL) /* receive callback is valid */
3639 {
3640 handle->receive_callback(L3GD20H_INTERRUPT2_Y_OVERRUN); /* run receive callback */
3641 }
3642 }
3643 if ((prev & (1 << L3GD20H_STATUS_X_OVERRUN)) != 0) /* check status x overrun */
3644 {
3645 if (handle->receive_callback != NULL) /* receive callback is valid */
3646 {
3647 handle->receive_callback(L3GD20H_INTERRUPT2_X_OVERRUN); /* run receive callback */
3648 }
3649 }
3650 if ((prev & (1 << L3GD20H_STATUS_XYZ_DATA_READY)) != 0) /* check status xyz data ready */
3651 {
3652 if (handle->receive_callback != NULL) /* receive callback is valid */
3653 {
3654 handle->receive_callback(L3GD20H_INTERRUPT2_XYZ_DATA_READY); /* run receive callback */
3655 }
3656 }
3657 if ((prev & (1 << L3GD20H_STATUS_Z_DATA_READY)) != 0) /* check status z data ready */
3658 {
3659 if (handle->receive_callback != NULL) /* receive callback is valid */
3660 {
3661 handle->receive_callback(L3GD20H_INTERRUPT2_Z_DATA_READY); /* run receive callback */
3662 }
3663 }
3664 if ((prev & (1 << L3GD20H_STATUS_Y_DATA_READY)) != 0) /* check status y data ready */
3665 {
3666 if (handle->receive_callback != NULL) /* receive callback is valid */
3667 {
3668 handle->receive_callback(L3GD20H_INTERRUPT2_Y_DATA_READY); /* run receive callback */
3669 }
3670 }
3671 if ((prev & (1 << L3GD20H_STATUS_X_DATA_READY)) != 0) /* check status x data ready */
3672 {
3673 if (handle->receive_callback != NULL) /* receive callback is valid */
3674 {
3675 handle->receive_callback(L3GD20H_INTERRUPT2_X_DATA_READY); /* run receive callback */
3676 }
3677 }
3678
3679 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_FIFO_SRC, (uint8_t *)&prev, 1); /* read config */
3680 if (res != 0) /* check result */
3681 {
3682 handle->debug_print("l3gd20h: read fifo source failed.\n"); /* read fifo source failed*/
3683
3684 return 1; /* return error */
3685 }
3686 if ((prev & (1 << 7)) != 0) /* check fifo threshold */
3687 {
3688 if (handle->receive_callback != NULL) /* receive callback is valid */
3689 {
3690 handle->receive_callback(L3GD20H_INTERRUPT2_FIFO_THRESHOLD); /* run receive callback */
3691 }
3692 }
3693 if ((prev & (1 << 6)) != 0) /* check fifo overrun */
3694 {
3695 if (handle->receive_callback != NULL) /* receive callback is valid */
3696 {
3697 handle->receive_callback(L3GD20H_INTERRUPT2_FIFO_OVERRRUN); /* run receive callback */
3698 }
3699 }
3700 if ((prev & (1 << 5)) != 0) /* check fifo empty */
3701 {
3702 if (handle->receive_callback != NULL) /* receive callback is valid */
3703 {
3704 handle->receive_callback(L3GD20H_INTERRUPT2_FIFO_EMPTY); /* run receive callback */
3705 }
3706 }
3707
3708 return 0; /* success return 0 */
3709 }
3710 else
3711 {
3712 handle->debug_print("l3gd20h: interrupt number is invalid.\n"); /* interrupt number is invalid */
3713
3714 return 1; /* return error */
3715 }
3716}
3717
3729uint8_t l3gd20h_init(l3gd20h_handle_t *handle)
3730{
3731 uint8_t res, prev;
3732 uint8_t id;
3733
3734 if (handle == NULL) /* check handle */
3735 {
3736 return 2; /* return error */
3737 }
3738 if (handle->debug_print == NULL) /* check debug_print */
3739 {
3740 return 3; /* return error */
3741 }
3742 if (handle->iic_init == NULL) /* check iic_init */
3743 {
3744 handle->debug_print("l3gd20h: iic_init is null.\n"); /* iic_init is null */
3745
3746 return 3; /* return error */
3747 }
3748 if (handle->iic_deinit == NULL) /* check iic_deinit */
3749 {
3750 handle->debug_print("l3gd20h: iic_deinit is null.\n"); /* iic_deinit is null */
3751
3752 return 3; /* return error */
3753 }
3754 if (handle->iic_read == NULL) /* check iic_read */
3755 {
3756 handle->debug_print("l3gd20h: iic_read is null.\n"); /* iic_read is null */
3757
3758 return 3; /* return error */
3759 }
3760 if (handle->iic_write == NULL) /* check iic_write */
3761 {
3762 handle->debug_print("l3gd20h: iic_write is null.\n"); /* iic_write is null */
3763
3764 return 3; /* return error */
3765 }
3766 if (handle->spi_init == NULL) /* check spi_init */
3767 {
3768 handle->debug_print("l3gd20h: spi_init is null.\n"); /* spi_init is null */
3769
3770 return 3; /* return error */
3771 }
3772 if (handle->spi_deinit == NULL) /* check spi_deinit */
3773 {
3774 handle->debug_print("l3gd20h: spi_deinit is null.\n"); /* spi_deinit is null */
3775
3776 return 3; /* return error */
3777 }
3778 if (handle->spi_read == NULL) /* check spi_read */
3779 {
3780 handle->debug_print("l3gd20h: spi_read is null.\n"); /* spi_read is null */
3781
3782 return 3; /* return error */
3783 }
3784 if (handle->spi_write == NULL) /* check spi_write */
3785 {
3786 handle->debug_print("l3gd20h: spi_write is null.\n"); /* spi_write is null */
3787
3788 return 3; /* return error */
3789 }
3790 if (handle->delay_ms == NULL) /* check delay_ms */
3791 {
3792 handle->debug_print("l3gd20h: delay_ms is null.\n"); /* delay_ms is null */
3793
3794 return 3; /* return error */
3795 }
3796
3797 if (handle->iic_spi == L3GD20H_INTERFACE_IIC) /* iic interface */
3798 {
3799 if (handle->iic_init() != 0) /* initialize iic bus */
3800 {
3801 handle->debug_print("l3gd20h: iic init failed.\n"); /* iic init failed */
3802
3803 return 1; /* return error */
3804 }
3805 }
3806 else
3807 {
3808 if (handle->spi_init() != 0) /* initialize spi bus */
3809 {
3810 handle->debug_print("l3gd20h: spi init failed.\n"); /* spi init failed */
3811
3812 return 1; /* return error */
3813 }
3814 }
3815 if (a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_WHO_AM_I, (uint8_t *)&id, 1) != 0) /* read id */
3816 {
3817 handle->debug_print("l3gd20h: read id failed.\n"); /* read id failed */
3818 if (handle->iic_spi == L3GD20H_INTERFACE_IIC) /* if iic interface */
3819 {
3820 (void)handle->iic_deinit(); /* iic deinit */
3821 }
3822 else /* spi interface */
3823 {
3824 (void)handle->spi_deinit(); /* spi deinit */
3825 }
3826
3827 return 1; /* return error */
3828 }
3829 if (id != 0xD7) /* check id */
3830 {
3831 handle->debug_print("l3gd20h: id is invalid.\n"); /* id is invalid */
3832 if (handle->iic_spi == L3GD20H_INTERFACE_IIC) /* if iic interface */
3833 {
3834 (void)handle->iic_deinit(); /* iic deinit */
3835 }
3836 else
3837 {
3838 (void)handle->spi_deinit(); /* spi deinit */
3839 }
3840
3841 return 4; /* return error */
3842 }
3843
3844 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_LOW_ODR, (uint8_t *)&prev, 1); /* read config */
3845 if (res != 0) /* check result */
3846 {
3847 handle->debug_print("l3gd20h: read low odr failed.\n"); /* read low odr failed */
3848 if (handle->iic_spi == L3GD20H_INTERFACE_IIC) /* if iic interface */
3849 {
3850 (void)handle->iic_deinit(); /* iic deinit */
3851 }
3852 else
3853 {
3854 (void)handle->spi_deinit(); /* spi deinit */
3855 }
3856
3857 return 1; /* return error */
3858 }
3859 prev &= ~(1 << 2); /* clear reset bit */
3860 prev |= 1 << 2; /* set reset bit */
3861 res = a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_LOW_ODR, (uint8_t *)&prev, 1); /* write config */
3862 if (res != 0) /* check result */
3863 {
3864 handle->debug_print("l3gd20h: write low odr failed.\n"); /* write low odr failed */
3865 if (handle->iic_spi == L3GD20H_INTERFACE_IIC) /* if iic interface */
3866 {
3867 (void)handle->iic_deinit(); /* iic deinit */
3868 }
3869 else
3870 {
3871 (void)handle->spi_deinit(); /* spi deinit */
3872 }
3873
3874 return 1; /* return error */
3875 }
3876 handle->delay_ms(12); /* delay 12 ms */
3877 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_LOW_ODR, (uint8_t *)&prev, 1); /* read config */
3878 if (res != 0) /* check result */
3879 {
3880 handle->debug_print("l3gd20h: read low odr failed.\n"); /* read low odr failed */
3881 if (handle->iic_spi == L3GD20H_INTERFACE_IIC) /* if iic interface */
3882 {
3883 (void)handle->iic_deinit(); /* iic deinit */
3884 }
3885 else
3886 {
3887 (void)handle->spi_deinit(); /* spi deinit */
3888 }
3889
3890 return 1; /* return error */
3891 }
3892 if (((prev >> 2) & 0x01) != 0x0) /* check result */
3893 {
3894 handle->debug_print("l3gd20h: reset chip failed.\n"); /* reset chip failed */
3895 if (handle->iic_spi == L3GD20H_INTERFACE_IIC) /* if iic interface */
3896 {
3897 (void)handle->iic_deinit(); /* iic deinit */
3898 }
3899 else
3900 {
3901 (void)handle->spi_deinit(); /* spi deinit */
3902 }
3903
3904 return 1; /* return error */
3905 }
3906
3907 handle->inited = 1; /* flag finish initialization */
3908
3909 return 0; /* success return 0 */
3910}
3911
3923uint8_t l3gd20h_deinit(l3gd20h_handle_t *handle)
3924{
3925 uint8_t res, prev;
3926
3927 if (handle == NULL) /* check handle */
3928 {
3929 return 2; /* return error */
3930 }
3931 if (handle->inited != 1) /* check handle initialization */
3932 {
3933 return 3; /* return error */
3934 }
3935
3936 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL1, (uint8_t *)&prev, 1); /* read config */
3937 if (res != 0) /* check result */
3938 {
3939 handle->debug_print("l3gd20h: read ctrl1 failed.\n"); /* read ctrl1 failed */
3940
3941 return 4; /* return error */
3942 }
3943 prev &= ~(1 << 3); /* set power down bit */
3944 res = a_l3gd20h_iic_spi_write(handle, L3GD20H_REG_CTRL1, (uint8_t *)&prev, 1); /* write config */
3945 if (res != 0) /* check result */
3946 {
3947 handle->debug_print("l3gd20h: write ctrl1 failed.\n"); /* write ctrl1 failed */
3948
3949 return 4; /* return error */
3950 }
3951 handle->inited = 0; /* flag close */
3952
3953 return 0; /* success return 0 */
3954}
3955
3970uint8_t l3gd20h_read(l3gd20h_handle_t *handle, int16_t (*raw)[3], float (*dps)[3], uint16_t *len)
3971{
3972 uint8_t res, prev;
3973 uint8_t mode, cnt, i;
3974 uint8_t ble, range, enable;
3975 uint8_t buf[32 * 6];
3976
3977 if (handle == NULL) /* check handle */
3978 {
3979 return 2; /* return error */
3980 }
3981 if (handle->inited != 1) /* check handle initialization */
3982 {
3983 return 3; /* return error */
3984 }
3985
3986 if ((*len) == 0) /* check length */
3987 {
3988 handle->debug_print("l3gd20h: length is zero.\n"); /* length is zero. */
3989
3990 return 4; /* return error */
3991 }
3992 if (a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_FIFO_CTRL, (uint8_t *)&prev, 1) != 0) /* read fifo ctrl */
3993 {
3994 handle->debug_print("l3gd20h: read fifo ctrl failed.\n"); /* read fifo ctrl failed */
3995
3996 return 1; /* return error */
3997 }
3998 mode = prev >> 5; /* get the mode */
3999 if (a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL5, (uint8_t *)&prev, 1) != 0) /* read ctrl5 */
4000 {
4001 handle->debug_print("l3gd20h: read ctrl5 failed.\n"); /* read ctrl5 failed */
4002
4003 return 1; /* return error */
4004 }
4005 enable = (prev & (1 << 6)) >> 6; /* get enable */
4006 if (a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_CTRL4, (uint8_t *)&prev, 1) != 0) /* get ctrl4 */
4007 {
4008 handle->debug_print("l3gd20h: read ctrl4 failed.\n"); /* read ctrl4 failed */
4009
4010 return 1; /* return error */
4011 }
4012 range = (prev & (3 << 4)) >> 4; /* get range */
4013 ble = (prev & (1 << 6)) >> 6; /* get big little endian */
4014 if ((mode && enable) != 0) /* fifo modes */
4015 {
4016 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_FIFO_SRC, (uint8_t *)&prev, 1); /* read fifo source */
4017 if (res != 0) /* check result */
4018 {
4019 handle->debug_print("l3gd20h: read fifo source failed.\n"); /* read fifo source failed */
4020
4021 return 1; /* return error */
4022 }
4023 cnt = prev & 0x1F; /* get counter */
4024 *len = ((*len) < cnt) ? (*len) : cnt; /* get the length */
4025 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_OUT_X_L, (uint8_t *)buf, 6 * (*len)); /* read all data */
4026 if (res != 0) /* check result */
4027 {
4028 handle->debug_print("l3gd20h: read data failed.\n"); /* read data failed */
4029
4030 return 1; /* return error */
4031 }
4032 for (i = 0; i < (*len); i++) /* get data */
4033 {
4034 if (ble == 0) /* little endian */
4035 {
4036 raw[i][0] = (int16_t)(((uint16_t)buf[1 + i * 6] << 8) | buf[0 + i * 6]); /* set x */
4037 raw[i][1] = (int16_t)(((uint16_t)buf[3 + i * 6] << 8) | buf[2 + i * 6]); /* set y */
4038 raw[i][2] = (int16_t)(((uint16_t)buf[5 + i * 6] << 8) | buf[4 + i * 6]); /* set z */
4039 }
4040 else /* big endian */
4041 {
4042 raw[i][0] = (int16_t)(((uint16_t)buf[0 + i * 6] << 8) | buf[1 + i * 6]); /* set x */
4043 raw[i][1] = (int16_t)(((uint16_t)buf[2 + i * 6] << 8) | buf[3 + i * 6]); /* set y */
4044 raw[i][2] = (int16_t)(((uint16_t)buf[4 + i * 6] << 8) | buf[5 + i * 6]); /* set z */
4045 }
4046 if (range == 0) /* ±245 dps */
4047 {
4048 dps[i][0] = (float)(raw[i][0]) * 8.75f / 1000.0f; /* set x */
4049 dps[i][1] = (float)(raw[i][1]) * 8.75f / 1000.0f; /* set y */
4050 dps[i][2] = (float)(raw[i][2]) * 8.75f / 1000.0f; /* set z */
4051 }
4052 else if (range == 1) /* ±500 dps */
4053 {
4054 dps[i][0] = (float)(raw[i][0]) * 17.5f / 1000.0f; /* set x */
4055 dps[i][1] = (float)(raw[i][1]) * 17.5f / 1000.0f; /* set y */
4056 dps[i][2] = (float)(raw[i][2]) * 17.5f / 1000.0f; /* set z */
4057 }
4058 else /* ±2000 dps */
4059 {
4060 dps[i][0] = (float)(raw[i][0]) * 70.0f / 1000.0f; /* set x */
4061 dps[i][1] = (float)(raw[i][1]) * 70.0f / 1000.0f; /* set y */
4062 dps[i][2] = (float)(raw[i][2]) * 70.0f / 1000.0f; /* set z */
4063 }
4064 }
4065 } /* bypass mode */
4066 else
4067 {
4068 *len = 1; /* set length */
4069 res = a_l3gd20h_iic_spi_read(handle, L3GD20H_REG_OUT_X_L, (uint8_t *)buf, 6); /* read data */
4070 if (res != 0) /* check result */
4071 {
4072 handle->debug_print("l3gd20h: read data failed.\n"); /* read data failed */
4073
4074 return 1; /* return error */
4075 }
4076 if (ble == 0) /* little endian */
4077 {
4078 raw[0][0] = (int16_t)(((uint16_t)buf[1] << 8) | buf[0]); /* set x */
4079 raw[0][1] = (int16_t)(((uint16_t)buf[3] << 8) | buf[2]); /* set y */
4080 raw[0][2] = (int16_t)(((uint16_t)buf[5] << 8) | buf[4]); /* set z */
4081 }
4082 else /* big endian */
4083 {
4084 raw[0][0] = (int16_t)(((uint16_t)buf[0] << 8) | buf[1]); /* set x */
4085 raw[0][1] = (int16_t)(((uint16_t)buf[2] << 8) | buf[3]); /* set y */
4086 raw[0][2] = (int16_t)(((uint16_t)buf[4] << 8) | buf[5]); /* set z */
4087 }
4088 if (range == 0) /* ±245 dps */
4089 {
4090 dps[0][0] = (float)(raw[0][0]) * 8.75f / 1000.0f; /* set x */
4091 dps[0][1] = (float)(raw[0][1]) * 8.75f / 1000.0f; /* set y */
4092 dps[0][2] = (float)(raw[0][2]) * 8.75f / 1000.0f; /* set z */
4093 }
4094 else if (range == 1) /* ±500 dps */
4095 {
4096 dps[0][0] = (float)(raw[0][0]) * 17.5f / 1000.0f; /* set x */
4097 dps[0][1] = (float)(raw[0][1]) * 17.5f / 1000.0f; /* set y */
4098 dps[0][2] = (float)(raw[0][2]) * 17.5f / 1000.0f; /* set z */
4099 }
4100 else /* ±2000 dps */
4101 {
4102 dps[0][0] = (float)(raw[0][0]) * 70.0f / 1000.0f; /* set x */
4103 dps[0][1] = (float)(raw[0][1]) * 70.0f / 1000.0f; /* set y */
4104 dps[0][2] = (float)(raw[0][2]) * 70.0f / 1000.0f; /* set z */
4105 }
4106 }
4107
4108 return 0; /* success return 0 */
4109}
4110
4124uint8_t l3gd20h_set_reg(l3gd20h_handle_t *handle, uint8_t reg, uint8_t *buf, uint16_t len)
4125{
4126 if (handle == NULL) /* check handle */
4127 {
4128 return 2; /* return error */
4129 }
4130 if (handle->inited != 1) /* check handle initialization */
4131 {
4132 return 3; /* return error */
4133 }
4134
4135 return a_l3gd20h_iic_spi_write(handle, reg, buf, len); /* write data */
4136}
4137
4151uint8_t l3gd20h_get_reg(l3gd20h_handle_t *handle, uint8_t reg, uint8_t *buf, uint16_t len)
4152{
4153 if (handle == NULL) /* check handle */
4154 {
4155 return 2; /* return error */
4156 }
4157 if (handle->inited != 1) /* check handle initialization */
4158 {
4159 return 3; /* return error */
4160 }
4161
4162 return a_l3gd20h_iic_spi_read(handle, reg, buf, len); /* read data */
4163}
4164
4173uint8_t l3gd20h_info(l3gd20h_info_t *info)
4174{
4175 if (info == NULL) /* check handle */
4176 {
4177 return 2; /* return error */
4178 }
4179
4180 memset(info, 0, sizeof(l3gd20h_info_t)); /* initialize l3gd20h info structure */
4181 strncpy(info->chip_name, CHIP_NAME, 32); /* copy chip name */
4182 strncpy(info->manufacturer_name, MANUFACTURER_NAME, 32); /* copy manufacturer name */
4183 strncpy(info->interface, "IIC SPI", 8); /* copy interface name */
4184 info->supply_voltage_min_v = SUPPLY_VOLTAGE_MIN; /* set minimal supply voltage */
4185 info->supply_voltage_max_v = SUPPLY_VOLTAGE_MAX; /* set maximum supply voltage */
4186 info->max_current_ma = MAX_CURRENT; /* set maximum current */
4187 info->temperature_max = TEMPERATURE_MAX; /* set minimal temperature */
4188 info->temperature_min = TEMPERATURE_MIN; /* set maximum temperature */
4189 info->driver_version = DRIVER_VERSION; /* set driver version */
4190
4191 return 0; /* success return 0 */
4192}
L3GD20H_REG_WHO_AM_I
#define L3GD20H_REG_WHO_AM_I
chip register definition
Definition driver_l3gd20h.c:55
L3GD20H_REG_REFERENCE
#define L3GD20H_REG_REFERENCE
Definition driver_l3gd20h.c:61
L3GD20H_REG_IG_CFG
#define L3GD20H_REG_IG_CFG
Definition driver_l3gd20h.c:72
L3GD20H_REG_CTRL4
#define L3GD20H_REG_CTRL4
Definition driver_l3gd20h.c:59
L3GD20H_REG_CTRL2
#define L3GD20H_REG_CTRL2
Definition driver_l3gd20h.c:57
L3GD20H_REG_FIFO_SRC
#define L3GD20H_REG_FIFO_SRC
Definition driver_l3gd20h.c:71
MAX_CURRENT
#define MAX_CURRENT
Definition driver_l3gd20h.c:47
L3GD20H_REG_CTRL3
#define L3GD20H_REG_CTRL3
Definition driver_l3gd20h.c:58
L3GD20H_REG_IG_THS_ZH
#define L3GD20H_REG_IG_THS_ZH
Definition driver_l3gd20h.c:78
L3GD20H_REG_IG_THS_YH
#define L3GD20H_REG_IG_THS_YH
Definition driver_l3gd20h.c:76
L3GD20H_REG_CTRL1
#define L3GD20H_REG_CTRL1
Definition driver_l3gd20h.c:56
L3GD20H_REG_FIFO_CTRL
#define L3GD20H_REG_FIFO_CTRL
Definition driver_l3gd20h.c:70
L3GD20H_REG_IG_SRC
#define L3GD20H_REG_IG_SRC
Definition driver_l3gd20h.c:73
SUPPLY_VOLTAGE_MAX
#define SUPPLY_VOLTAGE_MAX
Definition driver_l3gd20h.c:46
L3GD20H_REG_IG_THS_XH
#define L3GD20H_REG_IG_THS_XH
Definition driver_l3gd20h.c:74
TEMPERATURE_MAX
#define TEMPERATURE_MAX
Definition driver_l3gd20h.c:49
L3GD20H_REG_IG_THS_ZL
#define L3GD20H_REG_IG_THS_ZL
Definition driver_l3gd20h.c:79
MANUFACTURER_NAME
#define MANUFACTURER_NAME
Definition driver_l3gd20h.c:44
TEMPERATURE_MIN
#define TEMPERATURE_MIN
Definition driver_l3gd20h.c:48
L3GD20H_REG_OUT_X_L
#define L3GD20H_REG_OUT_X_L
Definition driver_l3gd20h.c:64
SUPPLY_VOLTAGE_MIN
#define SUPPLY_VOLTAGE_MIN
Definition driver_l3gd20h.c:45
L3GD20H_REG_OUT_TEMP
#define L3GD20H_REG_OUT_TEMP
Definition driver_l3gd20h.c:62
L3GD20H_REG_CTRL5
#define L3GD20H_REG_CTRL5
Definition driver_l3gd20h.c:60
L3GD20H_REG_IG_DURATION
#define L3GD20H_REG_IG_DURATION
Definition driver_l3gd20h.c:80
L3GD20H_REG_IG_THS_YL
#define L3GD20H_REG_IG_THS_YL
Definition driver_l3gd20h.c:77
L3GD20H_REG_IG_THS_XL
#define L3GD20H_REG_IG_THS_XL
Definition driver_l3gd20h.c:75
CHIP_NAME
#define CHIP_NAME
chip register definition
Definition driver_l3gd20h.c:43
DRIVER_VERSION
#define DRIVER_VERSION
Definition driver_l3gd20h.c:50
L3GD20H_REG_STATUS
#define L3GD20H_REG_STATUS
Definition driver_l3gd20h.c:63
L3GD20H_REG_LOW_ODR
#define L3GD20H_REG_LOW_ODR
Definition driver_l3gd20h.c:81
driver_l3gd20h.h
driver l3gd20h header file
l3gd20h_set_high_pass_filter
uint8_t l3gd20h_set_high_pass_filter(l3gd20h_handle_t *handle, l3gd20h_bool_t enable)
enable or disable high pass filter
Definition driver_l3gd20h.c:2102
l3gd20h_set_data_format
uint8_t l3gd20h_set_data_format(l3gd20h_handle_t *handle, l3gd20h_data_format_t data_format)
set the data format
Definition driver_l3gd20h.c:1510
l3gd20h_get_status
uint8_t l3gd20h_get_status(l3gd20h_handle_t *handle, uint8_t *status)
get the chip status
Definition driver_l3gd20h.c:2411
l3gd20h_info_t
struct l3gd20h_info_s l3gd20h_info_t
l3gd20h information structure definition
l3gd20h_set_block_data_update
uint8_t l3gd20h_set_block_data_update(l3gd20h_handle_t *handle, l3gd20h_bool_t enable)
enable or disable the block data update
Definition driver_l3gd20h.c:1436
l3gd20h_soft_reset
uint8_t l3gd20h_soft_reset(l3gd20h_handle_t *handle)
soft reset the device
Definition driver_l3gd20h.c:3406
l3gd20h_boot_t
l3gd20h_boot_t
l3gd20h boot enumeration definition
Definition driver_l3gd20h.h:224
l3gd20h_set_mode
uint8_t l3gd20h_set_mode(l3gd20h_handle_t *handle, l3gd20h_mode_t mode)
set the chip mode
Definition driver_l3gd20h.c:269
l3gd20h_get_boot
uint8_t l3gd20h_get_boot(l3gd20h_handle_t *handle, l3gd20h_boot_t *boot)
get the boot
Definition driver_l3gd20h.c:1917
l3gd20h_get_high_pass_filter_reference
uint8_t l3gd20h_get_high_pass_filter_reference(l3gd20h_handle_t *handle, uint8_t *value)
get the high pass filter reference
Definition driver_l3gd20h.c:2349
l3gd20h_get_axis
uint8_t l3gd20h_get_axis(l3gd20h_handle_t *handle, l3gd20h_axis_t axis, l3gd20h_bool_t *enable)
get the axis
Definition driver_l3gd20h.c:408
l3gd20h_get_mode
uint8_t l3gd20h_get_mode(l3gd20h_handle_t *handle, l3gd20h_mode_t *mode)
get the chip mode
Definition driver_l3gd20h.c:317
l3gd20h_get_out_selection
uint8_t l3gd20h_get_out_selection(l3gd20h_handle_t *handle, l3gd20h_selection_t *selection)
get the out selection
Definition driver_l3gd20h.c:2287
l3gd20h_info
uint8_t l3gd20h_info(l3gd20h_info_t *info)
get chip's information
Definition driver_l3gd20h.c:4173
l3gd20h_spi_wire_t
l3gd20h_spi_wire_t
l3gd20h spi wire enumeration definition
Definition driver_l3gd20h.h:215
l3gd20h_read_temperature
uint8_t l3gd20h_read_temperature(l3gd20h_handle_t *handle, int8_t *raw, float *temp)
read the temperature
Definition driver_l3gd20h.c:2375
l3gd20h_get_full_scale
uint8_t l3gd20h_get_full_scale(l3gd20h_handle_t *handle, l3gd20h_full_scale_t *full_scale)
get the full scale
Definition driver_l3gd20h.c:1621
l3gd20h_set_high_pass_filter_mode
uint8_t l3gd20h_set_high_pass_filter_mode(l3gd20h_handle_t *handle, l3gd20h_high_pass_filter_mode_t mode)
set the high pass filter mode
Definition driver_l3gd20h.c:696
l3gd20h_self_test_t
l3gd20h_self_test_t
l3gd20h self test type enumeration definition
Definition driver_l3gd20h.h:205
l3gd20h_set_rate_bandwidth
uint8_t l3gd20h_set_rate_bandwidth(l3gd20h_handle_t *handle, l3gd20h_lodr_odr_bw_t rate_bandwidth)
set the rate bandwidth
Definition driver_l3gd20h.c:445
l3gd20h_get_rate_bandwidth
uint8_t l3gd20h_get_rate_bandwidth(l3gd20h_handle_t *handle, l3gd20h_lodr_odr_bw_t *rate_bandwidth)
get the rate bandwidth
Definition driver_l3gd20h.c:504
l3gd20h_set_level_sensitive_latched
uint8_t l3gd20h_set_level_sensitive_latched(l3gd20h_handle_t *handle, l3gd20h_bool_t enable)
enable or disable the level sensitive latched
Definition driver_l3gd20h.c:1658
l3gd20h_read
uint8_t l3gd20h_read(l3gd20h_handle_t *handle, int16_t(*raw)[3], float(*dps)[3], uint16_t *len)
read the data
Definition driver_l3gd20h.c:3970
l3gd20h_set_out_selection
uint8_t l3gd20h_set_out_selection(l3gd20h_handle_t *handle, l3gd20h_selection_t selection)
set the out selection
Definition driver_l3gd20h.c:2250
l3gd20h_full_scale_t
l3gd20h_full_scale_t
l3gd20h full scale type enumeration definition
Definition driver_l3gd20h.h:195
l3gd20h_set_boot
uint8_t l3gd20h_set_boot(l3gd20h_handle_t *handle, l3gd20h_boot_t boot)
set the boot
Definition driver_l3gd20h.c:1880
l3gd20h_set_addr_pin
uint8_t l3gd20h_set_addr_pin(l3gd20h_handle_t *handle, l3gd20h_address_t addr_pin)
set the iic address pin
Definition driver_l3gd20h.c:225
l3gd20h_address_t
l3gd20h_address_t
l3gd20h address enumeration definition
Definition driver_l3gd20h.h:73
l3gd20h_set_interface
uint8_t l3gd20h_set_interface(l3gd20h_handle_t *handle, l3gd20h_interface_t interface)
set the chip interface
Definition driver_l3gd20h.c:183
l3gd20h_set_iic
uint8_t l3gd20h_set_iic(l3gd20h_handle_t *handle, l3gd20h_bool_t enable)
enable or disable the iic interface
Definition driver_l3gd20h.c:3333
l3gd20h_high_pass_filter_mode_t
l3gd20h_high_pass_filter_mode_t
l3gd20h high pass filter mode enumeration definition
Definition driver_l3gd20h.h:111
l3gd20h_get_level_trigger
uint8_t l3gd20h_get_level_trigger(l3gd20h_handle_t *handle, l3gd20h_bool_t *enable)
get the level trigger status
Definition driver_l3gd20h.c:659
l3gd20h_data_format_t
l3gd20h_data_format_t
l3gd20h data format enumeration definition
Definition driver_l3gd20h.h:186
l3gd20h_high_pass_filter_cut_off_frequency_t
l3gd20h_high_pass_filter_cut_off_frequency_t
l3gd20h high pass filter cut off frequency enumeration definition
Definition driver_l3gd20h.h:134
l3gd20h_set_high_pass_filter_reference
uint8_t l3gd20h_set_high_pass_filter_reference(l3gd20h_handle_t *handle, uint8_t value)
set the high pass filter reference
Definition driver_l3gd20h.c:2324
l3gd20h_deinit
uint8_t l3gd20h_deinit(l3gd20h_handle_t *handle)
close the chip
Definition driver_l3gd20h.c:3923
l3gd20h_get_addr_pin
uint8_t l3gd20h_get_addr_pin(l3gd20h_handle_t *handle, l3gd20h_address_t *addr_pin)
get the iic address pin
Definition driver_l3gd20h.c:246
l3gd20h_set_edge_trigger
uint8_t l3gd20h_set_edge_trigger(l3gd20h_handle_t *handle, l3gd20h_bool_t enable)
enable or disable the edge trigger
Definition driver_l3gd20h.c:547
l3gd20h_interface_t
l3gd20h_interface_t
l3gd20h interface enumeration definition
Definition driver_l3gd20h.h:64
l3gd20h_set_full_scale
uint8_t l3gd20h_set_full_scale(l3gd20h_handle_t *handle, l3gd20h_full_scale_t full_scale)
set the full scale
Definition driver_l3gd20h.c:1584
l3gd20h_axis_t
l3gd20h_axis_t
l3gd20h axis enumeration definition
Definition driver_l3gd20h.h:91
l3gd20h_irq_handler
uint8_t l3gd20h_irq_handler(l3gd20h_handle_t *handle, uint8_t num)
interrupt handler
Definition driver_l3gd20h.c:3539
l3gd20h_selection_t
l3gd20h_selection_t
l3gd20h selection enumeration definition
Definition driver_l3gd20h.h:233
l3gd20h_get_high_pass_filter_cut_off_frequency
uint8_t l3gd20h_get_high_pass_filter_cut_off_frequency(l3gd20h_handle_t *handle, l3gd20h_high_pass_filter_cut_off_frequency_t *frequency)
get the high pass filter cut off frequency
Definition driver_l3gd20h.c:807
l3gd20h_init
uint8_t l3gd20h_init(l3gd20h_handle_t *handle)
initialize the chip
Definition driver_l3gd20h.c:3729
l3gd20h_get_high_pass_filter
uint8_t l3gd20h_get_high_pass_filter(l3gd20h_handle_t *handle, l3gd20h_bool_t *enable)
get high pass filter status
Definition driver_l3gd20h.c:2139
l3gd20h_get_data_format
uint8_t l3gd20h_get_data_format(l3gd20h_handle_t *handle, l3gd20h_data_format_t *data_format)
get the data format
Definition driver_l3gd20h.c:1547
l3gd20h_get_interface
uint8_t l3gd20h_get_interface(l3gd20h_handle_t *handle, l3gd20h_interface_t *interface)
get the chip interface
Definition driver_l3gd20h.c:204
l3gd20h_get_high_pass_filter_mode
uint8_t l3gd20h_get_high_pass_filter_mode(l3gd20h_handle_t *handle, l3gd20h_high_pass_filter_mode_t *mode)
get the high pass filter mode
Definition driver_l3gd20h.c:733
l3gd20h_mode_t
l3gd20h_mode_t
l3gd20h mode enumeration definition
Definition driver_l3gd20h.h:101
l3gd20h_set_spi_wire
uint8_t l3gd20h_set_spi_wire(l3gd20h_handle_t *handle, l3gd20h_spi_wire_t spi_wire)
set the spi wire
Definition driver_l3gd20h.c:1806
l3gd20h_set_level_trigger
uint8_t l3gd20h_set_level_trigger(l3gd20h_handle_t *handle, l3gd20h_bool_t enable)
enable or disable the level trigger
Definition driver_l3gd20h.c:622
l3gd20h_get_block_data_update
uint8_t l3gd20h_get_block_data_update(l3gd20h_handle_t *handle, l3gd20h_bool_t *enable)
get the block data update status
Definition driver_l3gd20h.c:1473
l3gd20h_bool_t
l3gd20h_bool_t
l3gd20h bool enumeration definition
Definition driver_l3gd20h.h:82
l3gd20h_get_edge_trigger
uint8_t l3gd20h_get_edge_trigger(l3gd20h_handle_t *handle, l3gd20h_bool_t *enable)
get the edge trigger status
Definition driver_l3gd20h.c:584
l3gd20h_lodr_odr_bw_t
l3gd20h_lodr_odr_bw_t
l3gd20h low odr odr bw enumeration definition
Definition driver_l3gd20h.h:151
l3gd20h_get_spi_wire
uint8_t l3gd20h_get_spi_wire(l3gd20h_handle_t *handle, l3gd20h_spi_wire_t *spi_wire)
get the spi wire
Definition driver_l3gd20h.c:1843
l3gd20h_set_self_test
uint8_t l3gd20h_set_self_test(l3gd20h_handle_t *handle, l3gd20h_self_test_t self_test)
set the self test
Definition driver_l3gd20h.c:1732
l3gd20h_set_high_pass_filter_cut_off_frequency
uint8_t l3gd20h_set_high_pass_filter_cut_off_frequency(l3gd20h_handle_t *handle, l3gd20h_high_pass_filter_cut_off_frequency_t frequency)
set the high pass filter cut off frequency
Definition driver_l3gd20h.c:770
l3gd20h_set_axis
uint8_t l3gd20h_set_axis(l3gd20h_handle_t *handle, l3gd20h_axis_t axis, l3gd20h_bool_t enable)
set the axis
Definition driver_l3gd20h.c:370
l3gd20h_get_level_sensitive_latched
uint8_t l3gd20h_get_level_sensitive_latched(l3gd20h_handle_t *handle, l3gd20h_bool_t *enable)
get the level sensitive latched status
Definition driver_l3gd20h.c:1695
l3gd20h_get_iic
uint8_t l3gd20h_get_iic(l3gd20h_handle_t *handle, l3gd20h_bool_t *enable)
get the iic interface status
Definition driver_l3gd20h.c:3370
l3gd20h_get_self_test
uint8_t l3gd20h_get_self_test(l3gd20h_handle_t *handle, l3gd20h_self_test_t *self_test)
get the self test
Definition driver_l3gd20h.c:1769
l3gd20h_handle_t
struct l3gd20h_handle_s l3gd20h_handle_t
l3gd20h handle structure definition
L3GD20H_STATUS_XYZ_OVERRUN
@ L3GD20H_STATUS_XYZ_OVERRUN
Definition driver_l3gd20h.h:244
L3GD20H_STATUS_Y_DATA_READY
@ L3GD20H_STATUS_Y_DATA_READY
Definition driver_l3gd20h.h:250
L3GD20H_STATUS_Y_OVERRUN
@ L3GD20H_STATUS_Y_OVERRUN
Definition driver_l3gd20h.h:246
L3GD20H_STATUS_Z_OVERRUN
@ L3GD20H_STATUS_Z_OVERRUN
Definition driver_l3gd20h.h:245
L3GD20H_STATUS_X_DATA_READY
@ L3GD20H_STATUS_X_DATA_READY
Definition driver_l3gd20h.h:251
L3GD20H_STATUS_Z_DATA_READY
@ L3GD20H_STATUS_Z_DATA_READY
Definition driver_l3gd20h.h:249
L3GD20H_STATUS_XYZ_DATA_READY
@ L3GD20H_STATUS_XYZ_DATA_READY
Definition driver_l3gd20h.h:248
L3GD20H_STATUS_X_OVERRUN
@ L3GD20H_STATUS_X_OVERRUN
Definition driver_l3gd20h.h:247
L3GD20H_INTERFACE_IIC
@ L3GD20H_INTERFACE_IIC
Definition driver_l3gd20h.h:65
L3GD20H_MODE_SLEEP
@ L3GD20H_MODE_SLEEP
Definition driver_l3gd20h.h:104
l3gd20h_set_reg
uint8_t l3gd20h_set_reg(l3gd20h_handle_t *handle, uint8_t reg, uint8_t *buf, uint16_t len)
set the chip register
Definition driver_l3gd20h.c:4124
l3gd20h_get_reg
uint8_t l3gd20h_get_reg(l3gd20h_handle_t *handle, uint8_t reg, uint8_t *buf, uint16_t len)
get the chip register
Definition driver_l3gd20h.c:4151
l3gd20h_get_fifo_mode
uint8_t l3gd20h_get_fifo_mode(l3gd20h_handle_t *handle, l3gd20h_fifo_mode_t *fifo_mode)
get the fifo mode
Definition driver_l3gd20h.c:2473
l3gd20h_get_fifo_threshold
uint8_t l3gd20h_get_fifo_threshold(l3gd20h_handle_t *handle, uint8_t *threshold)
get the fifo threshold
Definition driver_l3gd20h.c:2554
l3gd20h_set_stop_on_fifo_threshold
uint8_t l3gd20h_set_stop_on_fifo_threshold(l3gd20h_handle_t *handle, l3gd20h_bool_t enable)
enable or disable stop on fifo threshold
Definition driver_l3gd20h.c:2028
l3gd20h_set_fifo_mode
uint8_t l3gd20h_set_fifo_mode(l3gd20h_handle_t *handle, l3gd20h_fifo_mode_t fifo_mode)
set the fifo mode
Definition driver_l3gd20h.c:2436
l3gd20h_get_fifo_level
uint8_t l3gd20h_get_fifo_level(l3gd20h_handle_t *handle, uint8_t *level)
get the fifo level
Definition driver_l3gd20h.c:2591
l3gd20h_set_fifo
uint8_t l3gd20h_set_fifo(l3gd20h_handle_t *handle, l3gd20h_bool_t enable)
enable or disable the fifo
Definition driver_l3gd20h.c:1954
l3gd20h_fifo_mode_t
l3gd20h_fifo_mode_t
l3gd20h fifo mode enumeration definition
Definition driver_l3gd20h.h:343
l3gd20h_set_fifo_threshold
uint8_t l3gd20h_set_fifo_threshold(l3gd20h_handle_t *handle, uint8_t threshold)
set the fifo threshold
Definition driver_l3gd20h.c:2511
l3gd20h_get_fifo
uint8_t l3gd20h_get_fifo(l3gd20h_handle_t *handle, l3gd20h_bool_t *enable)
get the fifo status
Definition driver_l3gd20h.c:1991
l3gd20h_get_stop_on_fifo_threshold
uint8_t l3gd20h_get_stop_on_fifo_threshold(l3gd20h_handle_t *handle, l3gd20h_bool_t *enable)
get stop on fifo threshold status
Definition driver_l3gd20h.c:2065
l3gd20h_set_interrupt_pin_type
uint8_t l3gd20h_set_interrupt_pin_type(l3gd20h_handle_t *handle, l3gd20h_pin_type_t pin_type)
set the interrupt pin type
Definition driver_l3gd20h.c:1066
l3gd20h_set_data_ready_on_interrupt2
uint8_t l3gd20h_set_data_ready_on_interrupt2(l3gd20h_handle_t *handle, l3gd20h_bool_t enable)
enable or disable the data ready on interrupt2
Definition driver_l3gd20h.c:1140
l3gd20h_get_interrupt_source
uint8_t l3gd20h_get_interrupt_source(l3gd20h_handle_t *handle, uint8_t *src)
get the interrupt source
Definition driver_l3gd20h.c:2704
l3gd20h_get_interrupt_active_level
uint8_t l3gd20h_get_interrupt_active_level(l3gd20h_handle_t *handle, l3gd20h_interrupt_active_level_t *level)
get the interrupt active level
Definition driver_l3gd20h.c:1029
l3gd20h_get_duration
uint8_t l3gd20h_get_duration(l3gd20h_handle_t *handle, uint8_t *duration)
get the wait duration
Definition driver_l3gd20h.c:3222
l3gd20h_get_interrupt_event
uint8_t l3gd20h_get_interrupt_event(l3gd20h_handle_t *handle, l3gd20h_interrupt_event_t interrupt_event, l3gd20h_bool_t *enable)
get the interrupt event
Definition driver_l3gd20h.c:2667
l3gd20h_get_x_interrupt_threshold
uint8_t l3gd20h_get_x_interrupt_threshold(l3gd20h_handle_t *handle, uint16_t *threshold)
get the x interrupt threshold
Definition driver_l3gd20h.c:2800
l3gd20h_get_fifo_empty_on_interrupt2
uint8_t l3gd20h_get_fifo_empty_on_interrupt2(l3gd20h_handle_t *handle, l3gd20h_bool_t *enable)
get the fifo empty on interrupt2 status
Definition driver_l3gd20h.c:1399
l3gd20h_get_interrupt_pin_type
uint8_t l3gd20h_get_interrupt_pin_type(l3gd20h_handle_t *handle, l3gd20h_pin_type_t *pin_type)
get the interrupt pin type
Definition driver_l3gd20h.c:1103
l3gd20h_get_counter_mode
uint8_t l3gd20h_get_counter_mode(l3gd20h_handle_t *handle, l3gd20h_counter_mode_t *counter_mode)
get the counter mode
Definition driver_l3gd20h.c:3069
l3gd20h_set_boot_on_interrupt1
uint8_t l3gd20h_set_boot_on_interrupt1(l3gd20h_handle_t *handle, l3gd20h_bool_t enable)
enable or disable boot on the interrupt1
Definition driver_l3gd20h.c:918
l3gd20h_set_x_interrupt_threshold
uint8_t l3gd20h_set_x_interrupt_threshold(l3gd20h_handle_t *handle, uint16_t threshold)
set the x interrupt threshold
Definition driver_l3gd20h.c:2740
l3gd20h_interrupt_event_t
l3gd20h_interrupt_event_t
l3gd20h interrupt event enumeration definition
Definition driver_l3gd20h.h:294
l3gd20h_interrupt_threshold_convert_to_data
uint8_t l3gd20h_interrupt_threshold_convert_to_data(l3gd20h_handle_t *handle, uint16_t reg, float *dps)
convert the interrupt threshold register raw data to the real data
Definition driver_l3gd20h.c:3492
l3gd20h_set_wait
uint8_t l3gd20h_set_wait(l3gd20h_handle_t *handle, l3gd20h_bool_t enable)
enable or disable the wait
Definition driver_l3gd20h.c:3106
l3gd20h_set_interrupt_event
uint8_t l3gd20h_set_interrupt_event(l3gd20h_handle_t *handle, l3gd20h_interrupt_event_t interrupt_event, l3gd20h_bool_t enable)
set the interrupt event
Definition driver_l3gd20h.c:2629
l3gd20h_counter_mode_t
l3gd20h_counter_mode_t
l3gd20h counter mode enumeration definition
Definition driver_l3gd20h.h:285
l3gd20h_set_duration
uint8_t l3gd20h_set_duration(l3gd20h_handle_t *handle, uint8_t duration)
set the wait duration
Definition driver_l3gd20h.c:3180
l3gd20h_set_fifo_threshold_on_interrupt2
uint8_t l3gd20h_set_fifo_threshold_on_interrupt2(l3gd20h_handle_t *handle, l3gd20h_bool_t enable)
enable or disable the fifo threshold on interrupt2
Definition driver_l3gd20h.c:1214
l3gd20h_get_y_interrupt_threshold
uint8_t l3gd20h_get_y_interrupt_threshold(l3gd20h_handle_t *handle, uint16_t *threshold)
get the y interrupt threshold
Definition driver_l3gd20h.c:2895
l3gd20h_get_fifo_threshold_on_interrupt2
uint8_t l3gd20h_get_fifo_threshold_on_interrupt2(l3gd20h_handle_t *handle, l3gd20h_bool_t *enable)
get the fifo threshold on interrupt2 status
Definition driver_l3gd20h.c:1251
l3gd20h_get_wait
uint8_t l3gd20h_get_wait(l3gd20h_handle_t *handle, l3gd20h_bool_t *enable)
get the wait status
Definition driver_l3gd20h.c:3143
l3gd20h_set_data_ready_active_level
uint8_t l3gd20h_set_data_ready_active_level(l3gd20h_handle_t *handle, l3gd20h_interrupt_active_level_t level)
set the data ready active level
Definition driver_l3gd20h.c:3259
l3gd20h_get_fifo_overrun_on_interrupt2
uint8_t l3gd20h_get_fifo_overrun_on_interrupt2(l3gd20h_handle_t *handle, l3gd20h_bool_t *enable)
get the fifo overrun on interrupt2 status
Definition driver_l3gd20h.c:1325
l3gd20h_set_counter_mode
uint8_t l3gd20h_set_counter_mode(l3gd20h_handle_t *handle, l3gd20h_counter_mode_t counter_mode)
set the counter mode
Definition driver_l3gd20h.c:3032
l3gd20h_get_data_ready_on_interrupt2
uint8_t l3gd20h_get_data_ready_on_interrupt2(l3gd20h_handle_t *handle, l3gd20h_bool_t *enable)
get the data ready on interrupt2 status
Definition driver_l3gd20h.c:1177
l3gd20h_get_boot_on_interrupt1
uint8_t l3gd20h_get_boot_on_interrupt1(l3gd20h_handle_t *handle, l3gd20h_bool_t *enable)
get the boot on the interrupt1 status
Definition driver_l3gd20h.c:955
l3gd20h_get_interrupt1
uint8_t l3gd20h_get_interrupt1(l3gd20h_handle_t *handle, l3gd20h_bool_t *enable)
get the interrupt1 status
Definition driver_l3gd20h.c:881
l3gd20h_set_interrupt_active_level
uint8_t l3gd20h_set_interrupt_active_level(l3gd20h_handle_t *handle, l3gd20h_interrupt_active_level_t level)
set the interrupt active level
Definition driver_l3gd20h.c:992
l3gd20h_set_fifo_overrun_on_interrupt2
uint8_t l3gd20h_set_fifo_overrun_on_interrupt2(l3gd20h_handle_t *handle, l3gd20h_bool_t enable)
enable or disable the fifo overrun on interrupt2
Definition driver_l3gd20h.c:1288
l3gd20h_interrupt_active_level_t
l3gd20h_interrupt_active_level_t
l3gd20h interrupt active level enumeration definition
Definition driver_l3gd20h.h:267
l3gd20h_interrupt_threshold_convert_to_register
uint8_t l3gd20h_interrupt_threshold_convert_to_register(l3gd20h_handle_t *handle, float dps, uint16_t *reg)
convert the interrupt threshold real data to the register raw data
Definition driver_l3gd20h.c:3444
l3gd20h_get_z_interrupt_threshold
uint8_t l3gd20h_get_z_interrupt_threshold(l3gd20h_handle_t *handle, uint16_t *threshold)
get the z interrupt threshold
Definition driver_l3gd20h.c:2990
l3gd20h_set_interrupt_selection
uint8_t l3gd20h_set_interrupt_selection(l3gd20h_handle_t *handle, l3gd20h_selection_t selection)
set the interrupt selection
Definition driver_l3gd20h.c:2176
l3gd20h_get_interrupt_selection
uint8_t l3gd20h_get_interrupt_selection(l3gd20h_handle_t *handle, l3gd20h_selection_t *selection)
get the interrupt selection
Definition driver_l3gd20h.c:2213
l3gd20h_set_fifo_empty_on_interrupt2
uint8_t l3gd20h_set_fifo_empty_on_interrupt2(l3gd20h_handle_t *handle, l3gd20h_bool_t enable)
enable or disable the fifo empty on interrupt2
Definition driver_l3gd20h.c:1362
l3gd20h_set_z_interrupt_threshold
uint8_t l3gd20h_set_z_interrupt_threshold(l3gd20h_handle_t *handle, uint16_t threshold)
set the z interrupt threshold
Definition driver_l3gd20h.c:2938
l3gd20h_get_data_ready_active_level
uint8_t l3gd20h_get_data_ready_active_level(l3gd20h_handle_t *handle, l3gd20h_interrupt_active_level_t *level)
get the data ready active level
Definition driver_l3gd20h.c:3296
l3gd20h_set_interrupt1
uint8_t l3gd20h_set_interrupt1(l3gd20h_handle_t *handle, l3gd20h_bool_t enable)
enable or disable the interrupt1
Definition driver_l3gd20h.c:844
l3gd20h_set_y_interrupt_threshold
uint8_t l3gd20h_set_y_interrupt_threshold(l3gd20h_handle_t *handle, uint16_t threshold)
set the y interrupt threshold
Definition driver_l3gd20h.c:2843
l3gd20h_pin_type_t
l3gd20h_pin_type_t
l3gd20h interrupt pin type enumeration definition
Definition driver_l3gd20h.h:276
L3GD20H_INTERRUPT1_Y_HIGH
@ L3GD20H_INTERRUPT1_Y_HIGH
Definition driver_l3gd20h.h:313
L3GD20H_INTERRUPT2_Y_DATA_READY
@ L3GD20H_INTERRUPT2_Y_DATA_READY
Definition driver_l3gd20h.h:323
L3GD20H_INTERRUPT1_X_LOW
@ L3GD20H_INTERRUPT1_X_LOW
Definition driver_l3gd20h.h:316
L3GD20H_INTERRUPT2_FIFO_EMPTY
@ L3GD20H_INTERRUPT2_FIFO_EMPTY
Definition driver_l3gd20h.h:327
L3GD20H_INTERRUPT1_X_HIGH
@ L3GD20H_INTERRUPT1_X_HIGH
Definition driver_l3gd20h.h:315
L3GD20H_INTERRUPT2_FIFO_THRESHOLD
@ L3GD20H_INTERRUPT2_FIFO_THRESHOLD
Definition driver_l3gd20h.h:325
L3GD20H_INTERRUPT1_Z_HIGH
@ L3GD20H_INTERRUPT1_Z_HIGH
Definition driver_l3gd20h.h:311
L3GD20H_INTERRUPT2_FIFO_OVERRRUN
@ L3GD20H_INTERRUPT2_FIFO_OVERRRUN
Definition driver_l3gd20h.h:326
L3GD20H_INTERRUPT2_X_OVERRUN
@ L3GD20H_INTERRUPT2_X_OVERRUN
Definition driver_l3gd20h.h:320
L3GD20H_INTERRUPT2_Y_OVERRUN
@ L3GD20H_INTERRUPT2_Y_OVERRUN
Definition driver_l3gd20h.h:319
L3GD20H_INTERRUPT2_X_DATA_READY
@ L3GD20H_INTERRUPT2_X_DATA_READY
Definition driver_l3gd20h.h:324
L3GD20H_INTERRUPT1_Y_LOW
@ L3GD20H_INTERRUPT1_Y_LOW
Definition driver_l3gd20h.h:314
L3GD20H_INTERRUPT1_INTERRUPT_ACTIVE
@ L3GD20H_INTERRUPT1_INTERRUPT_ACTIVE
Definition driver_l3gd20h.h:310
L3GD20H_INTERRUPT2_XYZ_DATA_READY
@ L3GD20H_INTERRUPT2_XYZ_DATA_READY
Definition driver_l3gd20h.h:321
L3GD20H_INTERRUPT2_Z_OVERRUN
@ L3GD20H_INTERRUPT2_Z_OVERRUN
Definition driver_l3gd20h.h:318
L3GD20H_INTERRUPT2_XYZ_OVERRUN
@ L3GD20H_INTERRUPT2_XYZ_OVERRUN
Definition driver_l3gd20h.h:317
L3GD20H_INTERRUPT2_Z_DATA_READY
@ L3GD20H_INTERRUPT2_Z_DATA_READY
Definition driver_l3gd20h.h:322
L3GD20H_INTERRUPT1_Z_LOW
@ L3GD20H_INTERRUPT1_Z_LOW
Definition driver_l3gd20h.h:312
l3gd20h_handle_s::iic_spi
uint8_t iic_spi
Definition driver_l3gd20h.h:380
l3gd20h_handle_s::inited
uint8_t inited
Definition driver_l3gd20h.h:379
l3gd20h_handle_s::spi_init
uint8_t(* spi_init)(void)
Definition driver_l3gd20h.h:372
l3gd20h_handle_s::delay_ms
void(* delay_ms)(uint32_t ms)
Definition driver_l3gd20h.h:377
l3gd20h_handle_s::spi_read
uint8_t(* spi_read)(uint8_t reg, uint8_t *buf, uint16_t len)
Definition driver_l3gd20h.h:374
l3gd20h_handle_s::receive_callback
void(* receive_callback)(uint8_t type)
Definition driver_l3gd20h.h:376
l3gd20h_handle_s::spi_write
uint8_t(* spi_write)(uint8_t reg, uint8_t *buf, uint16_t len)
Definition driver_l3gd20h.h:375
l3gd20h_handle_s::debug_print
void(* debug_print)(const char *const fmt,...)
Definition driver_l3gd20h.h:378
l3gd20h_handle_s::iic_init
uint8_t(* iic_init)(void)
Definition driver_l3gd20h.h:368
l3gd20h_handle_s::spi_deinit
uint8_t(* spi_deinit)(void)
Definition driver_l3gd20h.h:373
l3gd20h_handle_s::iic_write
uint8_t(* iic_write)(uint8_t addr, uint8_t reg, uint8_t *buf, uint16_t len)
Definition driver_l3gd20h.h:371
l3gd20h_handle_s::iic_addr
uint8_t iic_addr
Definition driver_l3gd20h.h:367
l3gd20h_handle_s::iic_read
uint8_t(* iic_read)(uint8_t addr, uint8_t reg, uint8_t *buf, uint16_t len)
Definition driver_l3gd20h.h:370
l3gd20h_handle_s::iic_deinit
uint8_t(* iic_deinit)(void)
Definition driver_l3gd20h.h:369
l3gd20h_info_s::temperature_max
float temperature_max
Definition driver_l3gd20h.h:395
l3gd20h_info_s::supply_voltage_max_v
float supply_voltage_max_v
Definition driver_l3gd20h.h:392
l3gd20h_info_s::driver_version
uint32_t driver_version
Definition driver_l3gd20h.h:396
l3gd20h_info_s::temperature_min
float temperature_min
Definition driver_l3gd20h.h:394
l3gd20h_info_s::max_current_ma
float max_current_ma
Definition driver_l3gd20h.h:393
l3gd20h_info_s::manufacturer_name
char manufacturer_name[32]
Definition driver_l3gd20h.h:389
l3gd20h_info_s::supply_voltage_min_v
float supply_voltage_min_v
Definition driver_l3gd20h.h:391
l3gd20h_info_s::interface
char interface[8]
Definition driver_l3gd20h.h:390
l3gd20h_info_s::chip_name
char chip_name[32]
Definition driver_l3gd20h.h:388