38#ifndef DRIVER_L3GD20H_FIFO_H
39#define DRIVER_L3GD20H_FIFO_H
55#define L3GD20H_FIFO_DEFAULT_BOOT L3GD20H_BOOT_NORMAL
56#define L3GD20H_FIFO_DEFAULT_AXIS_X L3GD20H_BOOL_TRUE
57#define L3GD20H_FIFO_DEFAULT_AXIS_Y L3GD20H_BOOL_TRUE
58#define L3GD20H_FIFO_DEFAULT_AXIS_Z L3GD20H_BOOL_TRUE
59#define L3GD20H_FIFO_DEFAULT_RATE_BANDWIDTH L3GD20H_LOW_ODR_0_ODR_100HZ_BW_0_12P5HZ
60#define L3GD20H_FIFO_DEFAULT_EDGE_TRIGGER L3GD20H_BOOL_FALSE
61#define L3GD20H_FIFO_DEFAULT_LEVEL_TRIGGER L3GD20H_BOOL_FALSE
62#define L3GD20H_FIFO_DEFAULT_LEVEL_SENSITIVE_LATCHED L3GD20H_BOOL_TRUE
63#define L3GD20H_FIFO_DEFAULT_SELF_TEST L3GD20H_SELF_TEST_NORMAL
64#define L3GD20H_FIFO_DEFAULT_HIGH_PASS_FILTER_MODE L3GD20H_HIGH_PASS_FILTER_MODE_NORMAL
65#define L3GD20H_FIFO_DEFAULT_HIGH_PASS_FILTER_CUT_OFF L3GD20H_HIGH_PASS_FILTER_CUT_OFF_FREQUENCY_0
66#define L3GD20H_FIFO_DEFAULT_HIGH_PASS_FILTER L3GD20H_BOOL_TRUE
67#define L3GD20H_FIFO_DEFAULT_BLOCK_DATA_UPDATE L3GD20H_BOOL_FALSE
68#define L3GD20H_FIFO_DEFAULT_OUT_SELECTION L3GD20H_SELECTION_LPF1_HPF_LPF2
69#define L3GD20H_FIFO_DEFAULT_INTERRUPT_SELECTION L3GD20H_SELECTION_LPF1_HPF_LPF2
70#define L3GD20H_FIFO_DEFAULT_HIGH_PASS_FILTER_REFERENCE 0x00
71#define L3GD20H_FIFO_DEFAULT_INTERRUPT1 L3GD20H_BOOL_FALSE
72#define L3GD20H_FIFO_DEFAULT_BOOT_ON_INTERRUPT1 L3GD20H_BOOL_FALSE
73#define L3GD20H_FIFO_DEFAULT_INTERRUPT_ACTIVE_LEVEL L3GD20H_INTERRUPT_ACTIVE_LEVEL_LOW
74#define L3GD20H_FIFO_DEFAULT_INTERRUPT_PIN_TYPE L3GD20H_PIN_PUSH_PULL
75#define L3GD20H_FIFO_DEFAULT_DATA_READY_ON_INTERRUPT2 L3GD20H_BOOL_FALSE
76#define L3GD20H_FIFO_DEFAULT_FIFO_EMPTY_ON_INTERRUPT2 L3GD20H_BOOL_FALSE
77#define L3GD20H_FIFO_DEFAULT_INTERRUPT_EVENT_AND_OR_COMBINATION L3GD20H_BOOL_FALSE
78#define L3GD20H_FIFO_DEFAULT_INTERRUPT_EVENT_LATCH L3GD20H_BOOL_FALSE
79#define L3GD20H_FIFO_DEFAULT_INTERRUPT_EVENT_Z_HIGH_EVENT L3GD20H_BOOL_FALSE
80#define L3GD20H_FIFO_DEFAULT_INTERRUPT_EVENT_Z_LOW_EVENT L3GD20H_BOOL_FALSE
81#define L3GD20H_FIFO_DEFAULT_INTERRUPT_EVENT_Y_HIGH_EVENT L3GD20H_BOOL_FALSE
82#define L3GD20H_FIFO_DEFAULT_INTERRUPT_EVENT_Y_LOW_EVENT L3GD20H_BOOL_FALSE
83#define L3GD20H_FIFO_DEFAULT_INTERRUPT_EVENT_X_HIGH_EVENT L3GD20H_BOOL_FALSE
84#define L3GD20H_FIFO_DEFAULT_INTERRUPT_EVENT_X_LOW_EVENT L3GD20H_BOOL_FALSE
85#define L3GD20H_FIFO_DEFAULT_INTERRUPT_THRESHOLD 0.0f
86#define L3GD20H_FIFO_DEFAULT_COUNTER_MODE L3GD20H_COUNTER_MODE_RESET
87#define L3GD20H_FIFO_DEFAULT_WAIT L3GD20H_BOOL_TRUE
88#define L3GD20H_FIFO_DEFAULT_DURATION 0x01
89#define L3GD20H_FIFO_DEFAULT_DATA_READY_ACTIVE_LEVEL L3GD20H_INTERRUPT_ACTIVE_LEVEL_LOW
90#define L3GD20H_FIFO_DEFAULT_STOP_ON_FIFO_THRESHOLD L3GD20H_BOOL_FALSE
91#define L3GD20H_FIFO_DEFAULT_FIFO_THRESHOLD 16
92#define L3GD20H_FIFO_DEFAULT_DATA_FORMAT L3GD20H_DATA_FORMAT_LITTLE_ENDIAN
93#define L3GD20H_FIFO_DEFAULT_FULL_SCALE L3GD20H_FULL_SCALE_245_DPS
115 void (*callback)(
float (*dps)[3], uint16_t len));
driver l3gd20h interface header file
l3gd20h_address_t
l3gd20h address enumeration definition
l3gd20h_interface_t
l3gd20h interface enumeration definition
uint8_t l3gd20h_fifo_irq_handler(void)
fifo example irq callback
uint8_t l3gd20h_fifo_deinit(void)
fifo example deinit
uint8_t l3gd20h_fifo_init(l3gd20h_interface_t interface, l3gd20h_address_t addr_pin, void(*callback)(float(*dps)[3], uint16_t len))
fifo example init