LibDriver CH9120
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driver_ch9120.c
Go to the documentation of this file.
1
36
37#include "driver_ch9120.h"
38
42#define CHIP_NAME "WCH CH9120"
43#define MANUFACTURER_NAME "WCH"
44#define SUPPLY_VOLTAGE_MIN 2.1f
45#define SUPPLY_VOLTAGE_MAX 3.6f
46#define MAX_CURRENT 100.0f
47#define TEMPERATURE_MIN -40.0f
48#define TEMPERATURE_MAX 85.0f
49#define DRIVER_VERSION 1000
50
54#define CH9120_CMD_CHIP_VERSION 0x01
55#define CH9120_CMD_RESET 0x02
56#define CH9120_CMD_GET_STATUS 0x03
57#define CH9120_CMD_SAVE_TO_EEPROM 0x0D
58#define CH9120_CMD_RUN_AND_RESET 0x0E
59#define CH9120_CMD_EXIT 0x5E
60#define CH9120_CMD_SET_MODE 0x10
61#define CH9120_CMD_SET_IP 0x11
62#define CH9120_CMD_SET_NETMASK 0x12
63#define CH9120_CMD_SET_GATEWAY 0x13
64#define CH9120_CMD_SET_PORT 0x14
65#define CH9120_CMD_SET_DST_IP 0x15
66#define CH9120_CMD_SET_DST_PORT 0x16
67#define CH9120_CMD_RANDOM_PORT 0x17
68#define CH9120_CMD_SET_BAUD 0x21
69#define CH9120_CMD_SET_CONFIG 0x22
70#define CH9120_CMD_SET_TIMEOUT 0x23
71#define CH9120_CMD_SET_DISCONNECT 0x24
72#define CH9120_CMD_SET_LEN 0x25
73#define CH9120_CMD_SET_FLUSH 0x26
74#define CH9120_CMD_DHCP 0x33
75#define CH9120_CMD_GET_MODE 0x60
76#define CH9120_CMD_GET_IP 0x61
77#define CH9120_CMD_GET_NETMASK 0x62
78#define CH9120_CMD_GET_GATEWAY 0x63
79#define CH9120_CMD_GET_PORT 0x64
80#define CH9120_CMD_GET_DST_IP 0x65
81#define CH9120_CMD_GET_DST_PORT 0x66
82#define CH9120_CMD_GET_BAUD 0x71
83#define CH9120_CMD_GET_CONFIG 0x72
84#define CH9120_CMD_GET_TIMEOUT 0x73
85#define CH9120_CMD_GET_DISCONNECT 0x74
86#define CH9120_CMD_GET_LEN 0x75
87#define CH9120_CMD_GET_FLUSH 0x76
88
104static uint8_t a_ch9120_write_check(ch9120_handle_t *handle,
105 uint8_t *param, uint16_t len,
106 uint16_t pre_delay, uint16_t timeout)
107{
108 uint16_t t;
109 uint8_t res;
110
111 if (len > 126) /* check length */
112 {
113 handle->debug_print("ch9120: len is invalid.\n"); /* len is invalid */
114
115 return 2; /* return error */
116 }
117
118 handle->buf[0] = 0x57; /* set header 0 */
119 handle->buf[1] = 0xAB; /* set header 1 */
120 memcpy(&handle->buf[2], param, len); /* copy param */
121 res = handle->cfg_gpio_write(0); /* set low */
122 if (res != 0) /* check result */
123 {
124 return 1; /* return error */
125 }
126 res = handle->uart_flush(); /* uart flush */
127 if (res != 0) /* check result */
128 {
129 return 1; /* return error */
130 }
131 if (handle->uart_write(handle->buf, 2 + len) != 0) /* write command */
132 {
133 handle->debug_print("ch9120: write failed.\n"); /* write failed */
134 (void)handle->cfg_gpio_write(1); /* set high */
135
136 return 1; /* return error */
137 }
138 if (pre_delay != 0) /* check pre_delay */
139 {
140 handle->delay_ms(pre_delay); /* delay pre_delay */
141 }
142
143 t = timeout / 10; /* 10ms */
144 while (t != 0) /* check timeout */
145 {
146 if (handle->uart_read(&res, 1) == 1) /* read data */
147 {
148 if (res == 0xAA) /* check 0xAA */
149 {
150 res = handle->cfg_gpio_write(1); /* set high */
151 if (res != 0) /* check result */
152 {
153 return 1; /* return error */
154 }
155
156 return 0; /* success return 0 */
157 }
158 else
159 {
160 handle->debug_print("ch9120: error.\n"); /* error */
161 (void)handle->cfg_gpio_write(1); /* set high */
162
163 return 3; /* return error */
164 }
165 }
166 handle->delay_ms(10); /* delay 10ms */
167 t--; /* timeout-- */
168 }
169
170 handle->debug_print("ch9120: timeout.\n"); /* timeout */
171 (void)handle->cfg_gpio_write(1); /* set high */
172
173 return 4; /* return error */
174}
175
192static uint8_t a_ch9120_write_read(ch9120_handle_t *handle,
193 uint8_t *param, uint16_t len,
194 uint8_t *out, uint16_t out_len,
195 uint16_t pre_delay, uint16_t timeout)
196{
197 uint8_t res;
198 uint16_t t;
199 uint16_t point;
200
201 if (len > 126) /* check length */
202 {
203 handle->debug_print("ch9120: len is invalid.\n"); /* len is invalid */
204
205 return 2; /* return error */
206 }
207
208 handle->buf[0] = 0x57; /* set header 0 */
209 handle->buf[1] = 0xAB; /* set header 1 */
210 memcpy(&handle->buf[2], param, len); /* copy param */
211 res = handle->cfg_gpio_write(0); /* set low */
212 if (res != 0) /* check result */
213 {
214 return 1; /* return error */
215 }
216 res = handle->uart_flush(); /* uart flush */
217 if (res != 0) /* check result */
218 {
219 return 1; /* return error */
220 }
221 if (handle->uart_write(handle->buf, 2 + len) != 0) /* write command */
222 {
223 handle->debug_print("ch9120: write failed.\n"); /* write failed */
224 (void)handle->cfg_gpio_write(1); /* set high */
225
226 return 1; /* return error */
227 }
228 if (pre_delay != 0) /* check pre_delay */
229 {
230 handle->delay_ms(pre_delay); /* delay pre_delay */
231 }
232
233 point = 0; /* init 0 */
234 t = timeout / 10; /* 10ms */
235 while (t != 0) /* check timeout */
236 {
237 uint16_t l;
238
239 l = handle->uart_read(&out[point], out_len - point); /* read data */
240 if (l != 0)
241 {
242 point += l; /* point += l*/
243 if (point >= out_len) /* check length */
244 {
245 res = handle->cfg_gpio_write(1); /* set high */
246 if (res != 0) /* check result */
247 {
248 return 1; /* return error */
249 }
250
251 return 0; /* success return 0 */
252 }
253 }
254 handle->delay_ms(10); /* delay 10ms */
255 t--; /* timeout-- */
256 }
257
258 handle->debug_print("ch9120: timeout.\n"); /* timeout */
259 (void)handle->cfg_gpio_write(1); /* set high */
260
261 return 3; /* return error */
262}
263
275uint8_t ch9120_get_version(ch9120_handle_t *handle, uint8_t *version)
276{
277 uint8_t cmd;
278
279 if (handle == NULL) /* check handle */
280 {
281 return 2; /* return error */
282 }
283 if (handle->inited != 1) /* check handle initialization */
284 {
285 return 3; /* return error */
286 }
287
288 cmd = CH9120_CMD_CHIP_VERSION; /* set chip version */
289 if (a_ch9120_write_read(handle, &cmd, 1, version, 1,
290 CH9120_UART_PRE_DELAY, 1000) != 0) /* get version */
291 {
292 return 1; /* return error */
293 }
294
295 return 0; /* success return 0 */
296}
297
308uint8_t ch9120_reset(ch9120_handle_t *handle)
309{
310 uint8_t cmd;
311
312 if (handle == NULL) /* check handle */
313 {
314 return 2; /* return error */
315 }
316 if (handle->inited != 1) /* check handle initialization */
317 {
318 return 3; /* return error */
319 }
320
321 cmd = CH9120_CMD_RESET; /* set reset */
322 if (a_ch9120_write_check(handle, &cmd, 1,
323 CH9120_UART_PRE_DELAY, 1000) != 0) /* reset */
324 {
325 return 1; /* return error */
326 }
327 handle->delay_ms(1000); /* delay 1000ms */
328
329 return 0; /* success return 0 */
330}
331
343uint8_t ch9120_get_status(ch9120_handle_t *handle, ch9120_status_t *status)
344{
345 uint8_t cmd;
346 uint8_t param;
347
348 if (handle == NULL) /* check handle */
349 {
350 return 2; /* return error */
351 }
352 if (handle->inited != 1) /* check handle initialization */
353 {
354 return 3; /* return error */
355 }
356
357 cmd = CH9120_CMD_GET_STATUS; /* get status */
358 if (a_ch9120_write_read(handle, &cmd, 1, &param, 1,
359 CH9120_UART_PRE_DELAY, 1000) != 0) /* get status */
360 {
361 return 1; /* return error */
362 }
363 *status = (ch9120_status_t)(param); /* get the status */
364
365 return 0; /* success return 0 */
366}
367
378uint8_t ch9120_save_to_eeprom(ch9120_handle_t *handle)
379{
380 uint8_t cmd;
381
382 if (handle == NULL) /* check handle */
383 {
384 return 2; /* return error */
385 }
386 if (handle->inited != 1) /* check handle initialization */
387 {
388 return 3; /* return error */
389 }
390
391 cmd = CH9120_CMD_SAVE_TO_EEPROM; /* set save to eeprom */
392 if (a_ch9120_write_check(handle, &cmd, 1,
393 CH9120_UART_PRE_DELAY, 1000) != 0) /* save to eeprom */
394 {
395 return 1; /* return error */
396 }
397
398 return 0; /* success return 0 */
399}
400
411uint8_t ch9120_config_and_reset(ch9120_handle_t *handle)
412{
413 uint8_t cmd;
414
415 if (handle == NULL) /* check handle */
416 {
417 return 2; /* return error */
418 }
419 if (handle->inited != 1) /* check handle initialization */
420 {
421 return 3; /* return error */
422 }
423
424 cmd = CH9120_CMD_RUN_AND_RESET; /* set run config reset */
425 if (a_ch9120_write_check(handle, &cmd, 1,
426 CH9120_UART_PRE_DELAY, 1000) != 0) /* run config reset */
427 {
428 return 1; /* return error */
429 }
430 handle->delay_ms(1000); /* delay 1000ms */
431
432 return 0; /* success return 0 */
433}
434
445uint8_t ch9120_exit(ch9120_handle_t *handle)
446{
447 uint8_t cmd;
448
449 if (handle == NULL) /* check handle */
450 {
451 return 2; /* return error */
452 }
453 if (handle->inited != 1) /* check handle initialization */
454 {
455 return 3; /* return error */
456 }
457
458 cmd = CH9120_CMD_EXIT; /* set exit */
459 if (a_ch9120_write_check(handle, &cmd, 1,
460 CH9120_UART_PRE_DELAY, 1000) != 0) /* exit */
461 {
462 return 1; /* return error */
463 }
464
465 return 0; /* success return 0 */
466}
467
479uint8_t ch9120_set_mode(ch9120_handle_t *handle, ch9120_mode_t mode)
480{
481 uint8_t cmd[2];
482
483 if (handle == NULL) /* check handle */
484 {
485 return 2; /* return error */
486 }
487 if (handle->inited != 1) /* check handle initialization */
488 {
489 return 3; /* return error */
490 }
491
492 cmd[0] = CH9120_CMD_SET_MODE; /* set mode */
493 cmd[1] = mode; /* set mode */
494 if (a_ch9120_write_check(handle, cmd, 2,
495 CH9120_UART_PRE_DELAY, 1000) != 0) /* write mode */
496 {
497 return 1; /* return error */
498 }
499
500 return 0; /* success return 0 */
501}
502
514uint8_t ch9120_get_mode(ch9120_handle_t *handle, ch9120_mode_t *mode)
515{
516 uint8_t cmd;
517 uint8_t param;
518
519 if (handle == NULL) /* check handle */
520 {
521 return 2; /* return error */
522 }
523 if (handle->inited != 1) /* check handle initialization */
524 {
525 return 3; /* return error */
526 }
527
528 cmd = CH9120_CMD_GET_MODE; /* get mode */
529 if (a_ch9120_write_read(handle, &cmd, 1, &param, 1,
530 CH9120_UART_PRE_DELAY, 1000) != 0) /* get mode */
531 {
532 return 1; /* return error */
533 }
534 *mode = (ch9120_mode_t)(param); /* get mode */
535
536 return 0; /* success return 0 */
537}
538
550uint8_t ch9120_set_ip(ch9120_handle_t *handle, uint8_t ip[4])
551{
552 uint8_t cmd[5];
553
554 if (handle == NULL) /* check handle */
555 {
556 return 2; /* return error */
557 }
558 if (handle->inited != 1) /* check handle initialization */
559 {
560 return 3; /* return error */
561 }
562
563 cmd[0] = CH9120_CMD_SET_IP; /* set ip */
564 cmd[1] = ip[0]; /* set ip[0] */
565 cmd[2] = ip[1]; /* set ip[1] */
566 cmd[3] = ip[2]; /* set ip[2] */
567 cmd[4] = ip[3]; /* set ip[3] */
568 if (a_ch9120_write_check(handle, cmd, 5,
569 CH9120_UART_PRE_DELAY, 1000) != 0) /* write ip */
570 {
571 return 1; /* return error */
572 }
573
574 return 0; /* success return 0 */
575}
576
588uint8_t ch9120_get_ip(ch9120_handle_t *handle, uint8_t ip[4])
589{
590 uint8_t cmd;
591
592 if (handle == NULL) /* check handle */
593 {
594 return 2; /* return error */
595 }
596 if (handle->inited != 1) /* check handle initialization */
597 {
598 return 3; /* return error */
599 }
600
601 cmd = CH9120_CMD_GET_IP; /* get ip */
602 if (a_ch9120_write_read(handle, &cmd, 1, ip, 4,
603 CH9120_UART_PRE_DELAY, 1000) != 0) /* read ip */
604 {
605 return 1; /* return error */
606 }
607
608 return 0; /* success return 0 */
609}
610
622uint8_t ch9120_set_subnet_mask(ch9120_handle_t *handle, uint8_t mask[4])
623{
624 uint8_t cmd[5];
625
626 if (handle == NULL) /* check handle */
627 {
628 return 2; /* return error */
629 }
630 if (handle->inited != 1) /* check handle initialization */
631 {
632 return 3; /* return error */
633 }
634
635 cmd[0] = CH9120_CMD_SET_NETMASK ; /* set sub mask */
636 cmd[1] = mask[0]; /* set mask[0] */
637 cmd[2] = mask[1]; /* set mask[1] */
638 cmd[3] = mask[2]; /* set mask[2] */
639 cmd[4] = mask[3]; /* set mask[3] */
640 if (a_ch9120_write_check(handle, cmd, 5,
641 CH9120_UART_PRE_DELAY, 1000) != 0) /* write subnet mask */
642 {
643 return 1; /* return error */
644 }
645
646 return 0; /* success return 0 */
647}
648
660uint8_t ch9120_get_subnet_mask(ch9120_handle_t *handle, uint8_t mask[4])
661{
662 uint8_t cmd;
663
664 if (handle == NULL) /* check handle */
665 {
666 return 2; /* return error */
667 }
668 if (handle->inited != 1) /* check handle initialization */
669 {
670 return 3; /* return error */
671 }
672
673 cmd = CH9120_CMD_GET_NETMASK ; /* get mask */
674 if (a_ch9120_write_read(handle, &cmd, 1, mask, 4,
675 CH9120_UART_PRE_DELAY, 1000) != 0) /* read subnet mask */
676 {
677 return 1; /* return error */
678 }
679
680 return 0; /* success return 0 */
681}
682
694uint8_t ch9120_set_gateway(ch9120_handle_t *handle, uint8_t ip[4])
695{
696 uint8_t cmd[5];
697
698 if (handle == NULL) /* check handle */
699 {
700 return 2; /* return error */
701 }
702 if (handle->inited != 1) /* check handle initialization */
703 {
704 return 3; /* return error */
705 }
706
707 cmd[0] = CH9120_CMD_SET_GATEWAY ; /* set gateway */
708 cmd[1] = ip[0]; /* set ip[0] */
709 cmd[2] = ip[1]; /* set ip[1] */
710 cmd[3] = ip[2]; /* set ip[2] */
711 cmd[4] = ip[3]; /* set ip[3] */
712 if (a_ch9120_write_check(handle, cmd, 5,
713 CH9120_UART_PRE_DELAY, 1000) != 0) /* write ip */
714 {
715 return 1; /* return error */
716 }
717
718 return 0; /* success return 0 */
719}
720
732uint8_t ch9120_get_gateway(ch9120_handle_t *handle, uint8_t ip[4])
733{
734 uint8_t cmd;
735
736 if (handle == NULL) /* check handle */
737 {
738 return 2; /* return error */
739 }
740 if (handle->inited != 1) /* check handle initialization */
741 {
742 return 3; /* return error */
743 }
744
745 cmd = CH9120_CMD_GET_GATEWAY; /* get gateway */
746 if (a_ch9120_write_read(handle, &cmd, 1, ip, 4,
747 CH9120_UART_PRE_DELAY, 1000) != 0) /* read gateway */
748 {
749 return 1; /* return error */
750 }
751
752 return 0; /* success return 0 */
753}
754
766uint8_t ch9120_set_source_port(ch9120_handle_t *handle, uint16_t num)
767{
768 uint8_t cmd[3];
769
770 if (handle == NULL) /* check handle */
771 {
772 return 2; /* return error */
773 }
774 if (handle->inited != 1) /* check handle initialization */
775 {
776 return 3; /* return error */
777 }
778
779 cmd[0] = CH9120_CMD_SET_PORT; /* set port */
780 cmd[1] = (num >> 0) & 0xFF; /* set port msb */
781 cmd[2] = (num >> 8) & 0xFF; /* set port lsb */
782 if (a_ch9120_write_check(handle, cmd, 3,
783 CH9120_UART_PRE_DELAY, 1000) != 0) /* write port */
784 {
785 return 1; /* return error */
786 }
787
788 return 0; /* success return 0 */
789}
790
802uint8_t ch9120_get_source_port(ch9120_handle_t *handle, uint16_t *num)
803{
804 uint8_t cmd;
805 uint8_t buf[2];
806
807 if (handle == NULL) /* check handle */
808 {
809 return 2; /* return error */
810 }
811 if (handle->inited != 1) /* check handle initialization */
812 {
813 return 3; /* return error */
814 }
815
816
817 cmd = CH9120_CMD_GET_PORT; /* get port */
818 if (a_ch9120_write_read(handle, &cmd, 1, buf, 2,
819 CH9120_UART_PRE_DELAY, 1000) != 0) /* get port */
820 {
821 return 1; /* return error */
822 }
823 *num= (uint16_t)((uint16_t)buf[1] << 8 | buf[0]); /* get port */
824
825 return 0; /* success return 0 */
826}
827
839uint8_t ch9120_set_dest_ip(ch9120_handle_t *handle, uint8_t ip[4])
840{
841 uint8_t cmd[5];
842
843 if (handle == NULL) /* check handle */
844 {
845 return 2; /* return error */
846 }
847 if (handle->inited != 1) /* check handle initialization */
848 {
849 return 3; /* return error */
850 }
851
852 cmd[0] = CH9120_CMD_SET_DST_IP; /* set dest ip */
853 cmd[1] = ip[0]; /* set ip[0] */
854 cmd[2] = ip[1]; /* set ip[1] */
855 cmd[3] = ip[2]; /* set ip[0] */
856 cmd[4] = ip[3]; /* set ip[1] */
857 if (a_ch9120_write_check(handle, cmd, 5,
858 CH9120_UART_PRE_DELAY, 1000) != 0) /* write dest ip */
859 {
860 return 1; /* return error */
861 }
862
863 return 0; /* success return 0 */
864}
865
877uint8_t ch9120_get_dest_ip(ch9120_handle_t *handle, uint8_t ip[4])
878{
879 uint8_t cmd;
880
881 if (handle == NULL) /* check handle */
882 {
883 return 2; /* return error */
884 }
885 if (handle->inited != 1) /* check handle initialization */
886 {
887 return 3; /* return error */
888 }
889
890 cmd = CH9120_CMD_GET_DST_IP; /* get dest ip */
891 if (a_ch9120_write_read(handle, &cmd, 1, ip, 4,
892 CH9120_UART_PRE_DELAY, 1000) != 0) /* get dest ip */
893 {
894 return 1; /* return error */
895 }
896
897
898 return 0; /* success return 0 */
899}
900
912uint8_t ch9120_set_dest_port(ch9120_handle_t *handle, uint16_t num)
913{
914 uint8_t cmd[3];
915
916 if (handle == NULL) /* check handle */
917 {
918 return 2; /* return error */
919 }
920 if (handle->inited != 1) /* check handle initialization */
921 {
922 return 3; /* return error */
923 }
924
925 cmd[0] = CH9120_CMD_SET_DST_PORT; /* set dest port */
926 cmd[1] = (num >> 0) & 0xFF; /* set port msb */
927 cmd[2] = (num >> 8) & 0xFF; /* set port lsb */
928 if (a_ch9120_write_check(handle, cmd, 3,
929 CH9120_UART_PRE_DELAY, 1000) != 0) /* write dest port */
930 {
931 return 1; /* return error */
932 }
933
934 return 0; /* success return 0 */
935}
936
948uint8_t ch9120_get_dest_port(ch9120_handle_t *handle, uint16_t *num)
949{
950 uint8_t cmd;
951 uint8_t buf[2];
952
953 if (handle == NULL) /* check handle */
954 {
955 return 2; /* return error */
956 }
957 if (handle->inited != 1) /* check handle initialization */
958 {
959 return 3; /* return error */
960 }
961
962 cmd = CH9120_CMD_GET_DST_PORT; /* get dest port */
963 if (a_ch9120_write_read(handle, &cmd, 1, buf, 2,
964 CH9120_UART_PRE_DELAY, 1000) != 0) /* get dest port */
965 {
966 return 1; /* return error */
967 }
968 *num= (uint16_t)((uint16_t)buf[1] << 8 | buf[0]); /* get port */
969
970 return 0; /* success return 0 */
971}
972
984uint8_t ch9120_set_uart_baud(ch9120_handle_t *handle, uint32_t baud)
985{
986 uint8_t cmd[5];
987
988 if (handle == NULL) /* check handle */
989 {
990 return 2; /* return error */
991 }
992 if (handle->inited != 1) /* check handle initialization */
993 {
994 return 3; /* return error */
995 }
996
997 cmd[0] = CH9120_CMD_SET_BAUD; /* set baud */
998 cmd[1] = (baud >> 0) & 0xFF; /* set baud[0] */
999 cmd[2] = (baud >> 8) & 0xFF; /* set baud[8] */
1000 cmd[3] = (baud >> 16) & 0xFF; /* set baud[16] */
1001 cmd[4] = (baud >> 24) & 0xFF; /* set baud[24] */
1002 if (a_ch9120_write_check(handle, cmd, 5,
1003 CH9120_UART_PRE_DELAY, 1000) != 0) /* write dest port */
1004 {
1005 return 1; /* return error */
1006 }
1007
1008 return 0; /* success return 0 */
1009}
1010
1022uint8_t ch9120_get_uart_baud(ch9120_handle_t *handle, uint32_t *baud)
1023{
1024 uint8_t cmd;
1025 uint8_t buf[4];
1026
1027 if (handle == NULL) /* check handle */
1028 {
1029 return 2; /* return error */
1030 }
1031 if (handle->inited != 1) /* check handle initialization */
1032 {
1033 return 3; /* return error */
1034 }
1035
1036 cmd = CH9120_CMD_GET_BAUD; /* get baud */
1037 if (a_ch9120_write_read(handle, &cmd, 1, buf, 4,
1038 CH9120_UART_PRE_DELAY, 1000) != 0) /* get dest port */
1039 {
1040 return 1; /* return error */
1041 }
1042 *baud = (uint32_t)(((uint32_t)buf[0] << 0) | ((uint32_t)buf[1] << 8) |
1043 ((uint32_t)buf[2] << 16) | ((uint32_t)buf[3] << 24)); /* get baud */
1044
1045 return 0; /* success return 0 */
1046}
1047
1061uint8_t ch9120_set_uart_config(ch9120_handle_t *handle, uint8_t data_bit, ch9120_parity_t parity, uint8_t stop_bit)
1062{
1063 uint8_t cmd[4];
1064
1065 if (handle == NULL) /* check handle */
1066 {
1067 return 2; /* return error */
1068 }
1069 if (handle->inited != 1) /* check handle initialization */
1070 {
1071 return 3; /* return error */
1072 }
1073
1074 cmd[0] = CH9120_CMD_SET_CONFIG; /* set config */
1075 cmd[1] = stop_bit; /* set stop bit */
1076 cmd[2] = parity; /* set parity */
1077 cmd[3] = data_bit; /* set data bit */
1078 if (a_ch9120_write_check(handle, cmd, 4,
1079 CH9120_UART_PRE_DELAY, 1000) != 0) /* write dest port */
1080 {
1081 return 1; /* return error */
1082 }
1083
1084 return 0; /* success return 0 */
1085}
1086
1100uint8_t ch9120_get_uart_config(ch9120_handle_t *handle, uint8_t *data_bit, ch9120_parity_t *parity, uint8_t *stop_bit)
1101{
1102 uint8_t cmd;
1103 uint8_t buf[3];
1104
1105 if (handle == NULL) /* check handle */
1106 {
1107 return 2; /* return error */
1108 }
1109 if (handle->inited != 1) /* check handle initialization */
1110 {
1111 return 3; /* return error */
1112 }
1113
1114 cmd = CH9120_CMD_GET_CONFIG; /* get config */
1115 if (a_ch9120_write_read(handle, &cmd, 1, buf, 3,
1116 CH9120_UART_PRE_DELAY, 1000) != 0) /* get dest port */
1117 {
1118 return 1; /* return error */
1119 }
1120 *stop_bit = buf[0]; /* get stop bit */
1121 *parity = (ch9120_parity_t)buf[1]; /* get parity */
1122 *data_bit = buf[2]; /* get data bit */
1123
1124 return 0; /* success return 0 */
1125}
1126
1138uint8_t ch9120_set_uart_timeout(ch9120_handle_t *handle, uint8_t timeout)
1139{
1140 uint8_t cmd[5];
1141
1142 if (handle == NULL) /* check handle */
1143 {
1144 return 2; /* return error */
1145 }
1146 if (handle->inited != 1) /* check handle initialization */
1147 {
1148 return 3; /* return error */
1149 }
1150
1151 cmd[0] = CH9120_CMD_SET_TIMEOUT; /* set timeout */
1152 cmd[1] = timeout; /* set timeout */
1153 cmd[2] = 0x00; /* set 0x00 */
1154 cmd[3] = 0x00; /* set 0x00 */
1155 cmd[4] = 0x00; /* set 0x00 */
1156 if (a_ch9120_write_check(handle, cmd, 5,
1157 CH9120_UART_PRE_DELAY, 1000) != 0) /* write uart timeout */
1158 {
1159 return 1; /* return error */
1160 }
1161
1162 return 0; /* success return 0 */
1163}
1164
1176uint8_t ch9120_get_uart_timeout(ch9120_handle_t *handle, uint8_t *timeout)
1177{
1178 uint8_t cmd;
1179
1180 if (handle == NULL) /* check handle */
1181 {
1182 return 2; /* return error */
1183 }
1184 if (handle->inited != 1) /* check handle initialization */
1185 {
1186 return 3; /* return error */
1187 }
1188
1189 cmd = CH9120_CMD_GET_TIMEOUT; /* get timeout */
1190 if (a_ch9120_write_read(handle, &cmd, 1, timeout, 1,
1191 CH9120_UART_PRE_DELAY, 1000) != 0) /* get uart timeout */
1192 {
1193 return 1; /* return error */
1194 }
1195
1196 return 0; /* success return 0 */
1197}
1198
1210uint8_t ch9120_uart_timeout_convert_to_register(ch9120_handle_t *handle, uint16_t ms, uint8_t *reg)
1211{
1212 if (handle == NULL) /* check handle */
1213 {
1214 return 2; /* return error */
1215 }
1216 if (handle->inited != 1) /* check handle initialization */
1217 {
1218 return 3; /* return error */
1219 }
1220
1221 *reg = (uint8_t)(ms / 5); /* convert real data to register data */
1222
1223 return 0; /* success return 0 */
1224}
1225
1237uint8_t ch9120_uart_timeout_convert_to_data(ch9120_handle_t *handle, uint8_t reg, uint16_t *ms)
1238{
1239 if (handle == NULL) /* check handle */
1240 {
1241 return 2; /* return error */
1242 }
1243 if (handle->inited != 1) /* check handle initialization */
1244 {
1245 return 3; /* return error */
1246 }
1247
1248 *ms = reg * 5; /* convert raw data to real data */
1249
1250 return 0; /* success return 0 */
1251}
1252
1264uint8_t ch9120_set_source_port_random(ch9120_handle_t *handle, ch9120_bool_t enable)
1265{
1266 uint8_t cmd[2];
1267
1268 if (handle == NULL) /* check handle */
1269 {
1270 return 2; /* return error */
1271 }
1272 if (handle->inited != 1) /* check handle initialization */
1273 {
1274 return 3; /* return error */
1275 }
1276
1277 cmd[0] = CH9120_CMD_RANDOM_PORT; /* set random */
1278 cmd[1] = enable; /* set bool */
1279 if (a_ch9120_write_check(handle, cmd, 2,
1280 CH9120_UART_PRE_DELAY, 1000) != 0) /* write source port random */
1281 {
1282 return 1; /* return error */
1283 }
1284
1285 return 0; /* success return 0 */
1286}
1287
1299uint8_t ch9120_set_uart_buffer_length(ch9120_handle_t *handle, uint32_t len)
1300{
1301 uint8_t cmd[5];
1302
1303 if (handle == NULL) /* check handle */
1304 {
1305 return 2; /* return error */
1306 }
1307 if (handle->inited != 1) /* check handle initialization */
1308 {
1309 return 3; /* return error */
1310 }
1311
1312 cmd[0] = CH9120_CMD_SET_LEN; /* set uart buffer */
1313 cmd[1] = (len >> 0) & 0xFF; /* set len[0] */
1314 cmd[2] = (len >> 8) & 0xFF; /* set len[8] */
1315 cmd[3] = (len >> 16) & 0xFF; /* set len[16] */
1316 cmd[4] = (len >> 24) & 0xFF; /* set len[24] */
1317 if (a_ch9120_write_check(handle, cmd, 5,
1318 CH9120_UART_PRE_DELAY, 1000) != 0) /* write uart buffer */
1319 {
1320 return 1; /* return error */
1321 }
1322
1323 return 0; /* success return 0 */
1324}
1325
1337uint8_t ch9120_get_uart_buffer_length(ch9120_handle_t *handle, uint32_t *len)
1338{
1339 uint8_t cmd;
1340 uint8_t buf[4];
1341
1342 if (handle == NULL) /* check handle */
1343 {
1344 return 2; /* return error */
1345 }
1346 if (handle->inited != 1) /* check handle initialization */
1347 {
1348 return 3; /* return error */
1349 }
1350
1351 cmd = CH9120_CMD_GET_LEN; /* get uart buffer length */
1352 if (a_ch9120_write_read(handle, &cmd, 1, buf, 4,
1353 CH9120_UART_PRE_DELAY, 1000) != 0) /* read buffer length */
1354 {
1355 return 1; /* return error */
1356 }
1357 *len = (uint32_t)(((uint32_t)buf[0] << 0) | ((uint32_t)buf[1] << 8) |
1358 ((uint32_t)buf[2] << 16) | ((uint32_t)buf[3] << 24)); /* get length */
1359
1360 return 0; /* success return 0 */
1361}
1362
1374uint8_t ch9120_set_uart_flush(ch9120_handle_t *handle, ch9120_bool_t enable)
1375{
1376 uint8_t cmd[2];
1377
1378 if (handle == NULL) /* check handle */
1379 {
1380 return 2; /* return error */
1381 }
1382 if (handle->inited != 1) /* check handle initialization */
1383 {
1384 return 3; /* return error */
1385 }
1386
1387 cmd[0] = CH9120_CMD_SET_FLUSH; /* set flush */
1388 cmd[1] = enable; /* set bool */
1389 if (a_ch9120_write_check(handle, cmd, 2,
1390 CH9120_UART_PRE_DELAY, 1000) != 0) /* write flush */
1391 {
1392 return 1; /* return error */
1393 }
1394
1395 return 0; /* success return 0 */
1396}
1397
1409uint8_t ch9120_get_uart_flush(ch9120_handle_t *handle, ch9120_bool_t *enable)
1410{
1411 uint8_t cmd;
1412 uint8_t param;
1413
1414 if (handle == NULL) /* check handle */
1415 {
1416 return 2; /* return error */
1417 }
1418 if (handle->inited != 1) /* check handle initialization */
1419 {
1420 return 3; /* return error */
1421 }
1422
1423 cmd = CH9120_CMD_GET_FLUSH; /* get uart flush */
1424 if (a_ch9120_write_read(handle, &cmd, 1, &param, 1,
1425 CH9120_UART_PRE_DELAY, 1000) != 0) /* get uart flush */
1426 {
1427 return 1; /* return error */
1428 }
1429 *enable = (ch9120_bool_t)(param); /* set bool */
1430
1431 return 0; /* success return 0 */
1432}
1433
1445uint8_t ch9120_set_disconnect_with_no_rj45(ch9120_handle_t *handle, ch9120_bool_t enable)
1446{
1447 uint8_t cmd[2];
1448
1449 if (handle == NULL) /* check handle */
1450 {
1451 return 2; /* return error */
1452 }
1453 if (handle->inited != 1) /* check handle initialization */
1454 {
1455 return 3; /* return error */
1456 }
1457
1458 cmd[0] = CH9120_CMD_SET_DISCONNECT; /* set disconnect */
1459 cmd[1] = enable; /* set bool */
1460 if (a_ch9120_write_check(handle, cmd, 2,
1461 CH9120_UART_PRE_DELAY, 1000) != 0) /* write disconnect */
1462 {
1463 return 1; /* return error */
1464 }
1465
1466 return 0; /* success return 0 */
1467}
1468
1480uint8_t ch9120_get_disconnect_with_no_rj45(ch9120_handle_t *handle, ch9120_bool_t *enable)
1481{
1482 uint8_t cmd;
1483 uint8_t param;
1484
1485 if (handle == NULL) /* check handle */
1486 {
1487 return 2; /* return error */
1488 }
1489 if (handle->inited != 1) /* check handle initialization */
1490 {
1491 return 3; /* return error */
1492 }
1493
1494 cmd = CH9120_CMD_GET_DISCONNECT; /* get disconnect */
1495 if (a_ch9120_write_read(handle, &cmd, 1, &param, 1,
1496 CH9120_UART_PRE_DELAY, 1000) != 0) /* get disconnect */
1497 {
1498 return 1; /* return error */
1499 }
1500 *enable = (ch9120_bool_t)(param); /* set bool */
1501
1502 return 0; /* success return 0 */
1503}
1504
1516uint8_t ch9120_set_dhcp(ch9120_handle_t *handle, ch9120_bool_t enable)
1517{
1518 uint8_t cmd[2];
1519
1520 if (handle == NULL) /* check handle */
1521 {
1522 return 2; /* return error */
1523 }
1524 if (handle->inited != 1) /* check handle initialization */
1525 {
1526 return 3; /* return error */
1527 }
1528
1529 cmd[0] = CH9120_CMD_DHCP; /* set dhcp */
1530 cmd[1] = enable; /* set bool */
1531 if (a_ch9120_write_check(handle, cmd, 2,
1532 CH9120_UART_PRE_DELAY, 1000) != 0) /* dhcp */
1533 {
1534 return 1; /* return error */
1535 }
1536
1537 return 0; /* success return 0 */
1538}
1539
1553uint8_t ch9120_init(ch9120_handle_t *handle)
1554{
1555 if (handle == NULL) /* check handle */
1556 {
1557 return 2; /* return error */
1558 }
1559 if (handle->debug_print == NULL) /* check debug_print */
1560 {
1561 return 3; /* return error */
1562 }
1563 if (handle->uart_init == NULL) /* check uart_init */
1564 {
1565 handle->debug_print("ch9120: uart_init is null.\n"); /* uart_init is null */
1566
1567 return 3; /* return error */
1568 }
1569 if (handle->uart_deinit == NULL) /* check uart_deinit */
1570 {
1571 handle->debug_print("ch9120: uart_deinit is null.\n"); /* uart_deinit is null */
1572
1573 return 3; /* return error */
1574 }
1575 if (handle->uart_read == NULL) /* check uart_read */
1576 {
1577 handle->debug_print("ch9120: uart_read is null.\n"); /* uart_read is null */
1578
1579 return 3; /* return error */
1580 }
1581 if (handle->uart_write == NULL) /* check uart_write */
1582 {
1583 handle->debug_print("ch9120: uart_write is null.\n"); /* uart_write is null */
1584
1585 return 3; /* return error */
1586 }
1587 if (handle->uart_flush == NULL) /* check uart_flush */
1588 {
1589 handle->debug_print("ch9120: uart_flush is null.\n"); /* uart_flush is null */
1590
1591 return 3; /* return error */
1592 }
1593 if (handle->delay_ms == NULL) /* check delay_ms */
1594 {
1595 handle->debug_print("ch9120: delay_ms is null.\n"); /* delay_ms is null */
1596
1597 return 3; /* return error */
1598 }
1599 if (handle->reset_gpio_init == NULL) /* check reset_gpio_init */
1600 {
1601 handle->debug_print("ch9120: reset_gpio_init is null.\n"); /* reset_gpio_init is null */
1602
1603 return 3; /* return error */
1604 }
1605 if (handle->reset_gpio_deinit == NULL) /* check reset_gpio_deinit */
1606 {
1607 handle->debug_print("ch9120: reset_gpio_deinit is null.\n"); /* reset_gpio_deinit is null */
1608
1609 return 3; /* return error */
1610 }
1611 if (handle->reset_gpio_write == NULL) /* check reset_gpio_write */
1612 {
1613 handle->debug_print("ch9120: reset_gpio_write is null.\n"); /* reset_gpio_write is null */
1614
1615 return 3; /* return error */
1616 }
1617 if (handle->cfg_gpio_init == NULL) /* check cfg_gpio_init */
1618 {
1619 handle->debug_print("ch9120: cfg_gpio_init is null.\n"); /* cfg_gpio_init is null */
1620
1621 return 3; /* return error */
1622 }
1623 if (handle->cfg_gpio_deinit == NULL) /* check cfg_gpio_deinit */
1624 {
1625 handle->debug_print("ch9120: cfg_gpio_deinit is null.\n"); /* cfg_gpio_deinit is null */
1626
1627 return 3; /* return error */
1628 }
1629 if (handle->cfg_gpio_write == NULL) /* check cfg_gpio_write */
1630 {
1631 handle->debug_print("ch9120: cfg_gpio_write is null.\n"); /* cfg_gpio_write is null */
1632
1633 return 3; /* return error */
1634 }
1635
1636 if (handle->uart_init() != 0) /* uart init */
1637 {
1638 handle->debug_print("ch9120: uart init failed.\n"); /* uart init failed */
1639
1640 return 1; /* return error */
1641 }
1642 if (handle->reset_gpio_init() != 0) /* reset gpio init */
1643 {
1644 handle->debug_print("ch9120: reset gpio init failed.\n"); /* reset gpio init failed */
1645 (void)handle->uart_deinit(); /* uart deinit */
1646
1647 return 4; /* return error */
1648 }
1649 if (handle->cfg_gpio_init() != 0) /* cfg gpio init */
1650 {
1651 handle->debug_print("ch9120: cfg gpio init failed.\n"); /* cfg gpio init failed */
1652 (void)handle->uart_deinit(); /* uart deinit */
1653 (void)handle->reset_gpio_deinit(); /* reset gpio deinit */
1654
1655 return 5; /* return error */
1656 }
1657 if (handle->reset_gpio_write(0) != 0) /* set low */
1658 {
1659 handle->debug_print("ch9120: cfg gpio write failed.\n"); /* cfg gpio write failed */
1660 (void)handle->uart_deinit(); /* uart deinit */
1661 (void)handle->reset_gpio_deinit(); /* reset gpio deinit */
1662 (void)handle->cfg_gpio_deinit(); /* cfg gpio deinit */
1663
1664 return 6; /* return error */
1665 }
1666 handle->delay_ms(10); /* delay 10ms */
1667 if (handle->reset_gpio_write(1) != 0) /* set high */
1668 {
1669 handle->debug_print("ch9120: cfg gpio write failed.\n"); /* cfg gpio write failed */
1670 (void)handle->uart_deinit(); /* uart deinit */
1671 (void)handle->reset_gpio_deinit(); /* reset gpio deinit */
1672 (void)handle->cfg_gpio_deinit(); /* cfg gpio deinit */
1673
1674 return 6; /* return error */
1675 }
1676 handle->delay_ms(500); /* delay 500ms */
1677 handle->inited = 1; /* flag finish initialization */
1678
1679 return 0; /* success return 0 */
1680}
1681
1695uint8_t ch9120_deinit(ch9120_handle_t *handle)
1696{
1697 uint8_t cmd;
1698
1699 if (handle == NULL) /* check handle */
1700 {
1701 return 2; /* return error */
1702 }
1703 if (handle->inited != 1) /* check handle initialization */
1704 {
1705 return 3; /* return error */
1706 }
1707
1708 cmd = CH9120_CMD_RESET; /* set reset */
1709 if (a_ch9120_write_check(handle, &cmd, 1,
1710 CH9120_UART_PRE_DELAY, 1000) != 0) /* reset */
1711 {
1712 return 4; /* return error */
1713 }
1714 handle->delay_ms(10); /* delay 10ms */
1715 if (handle->uart_deinit() != 0) /* uart deinit */
1716 {
1717 handle->debug_print("ch9120: uart deinit failed.\n"); /* uart deinit failed */
1718
1719 return 1; /* return error */
1720 }
1721 if (handle->reset_gpio_deinit() != 0) /* reset gpio deinit */
1722 {
1723 handle->debug_print("ch9120: reset gpio deinit failed.\n"); /* reset gpio deinit failed */
1724
1725 return 5; /* return error */
1726 }
1727 if (handle->cfg_gpio_deinit() != 0) /* cfg gpio deinit */
1728 {
1729 handle->debug_print("ch9120: cfg gpio deinit failed.\n"); /* cfg gpio deinit failed */
1730
1731 return 6; /* return error */
1732 }
1733
1734 return 0; /* success return 0 */
1735}
1736
1749uint8_t ch9120_write(ch9120_handle_t *handle, uint8_t *buf, uint16_t len)
1750{
1751 if (handle == NULL) /* check handle */
1752 {
1753 return 2; /* return error */
1754 }
1755 if (handle->inited != 1) /* check handle initialization */
1756 {
1757 return 3; /* return error */
1758 }
1759
1760 if (handle->cfg_gpio_write(1) != 0) /* cfg gpio write */
1761 {
1762 handle->debug_print("ch9120: cfg gpio write failed.\n"); /* cfg gpio write failed */
1763
1764 return 1; /* return error */
1765 }
1766 if (handle->uart_write(buf, len) != 0) /* uart write */
1767 {
1768 handle->debug_print("ch9120:uart write failed.\n"); /* uart write failed */
1769
1770 return 1; /* return error */
1771 }
1772
1773 return 0; /* success return 0 */
1774}
1775
1788uint8_t ch9120_read(ch9120_handle_t *handle, uint8_t *buf, uint16_t *len)
1789{
1790 uint16_t l;
1791
1792 if (handle == NULL) /* check handle */
1793 {
1794 return 2; /* return error */
1795 }
1796 if (handle->inited != 1) /* check handle initialization */
1797 {
1798 return 3; /* return error */
1799 }
1800
1801 if (handle->cfg_gpio_write(1) != 0) /* cfg gpio write */
1802 {
1803 handle->debug_print("ch9120: cfg gpio write failed.\n"); /* cfg gpio write failed */
1804
1805 return 1; /* return error */
1806 }
1807 l = handle->uart_read(buf, *len); /* uart read */
1808 *len = l; /* set data */
1809
1810 return 0; /* success return 0 */
1811}
1812
1829uint8_t ch9120_set_command(ch9120_handle_t *handle,
1830 uint8_t *param, uint16_t len,
1831 uint8_t *out, uint16_t out_len,
1832 uint16_t pre_delay, uint16_t timeout)
1833{
1834 if (handle == NULL) /* check handle */
1835 {
1836 return 2; /* return error */
1837 }
1838 if (handle->inited != 1) /* check handle initialization */
1839 {
1840 return 3; /* return error */
1841 }
1842
1843 if (a_ch9120_write_read(handle, param, len,
1844 out, out_len,
1845 pre_delay, timeout) != 0) /* set command */
1846 {
1847 return 1; /* return error */
1848 }
1849
1850 return 0; /* success return 0 */
1851}
1852
1861uint8_t ch9120_info(ch9120_info_t *info)
1862{
1863 if (info == NULL) /* check handle */
1864 {
1865 return 2; /* return error */
1866 }
1867
1868 memset(info, 0, sizeof(ch9120_info_t)); /* initialize ch9120 info structure */
1869 strncpy(info->chip_name, CHIP_NAME, 32); /* copy chip name */
1870 strncpy(info->manufacturer_name, MANUFACTURER_NAME, 32); /* copy manufacturer name */
1871 strncpy(info->interface, "UART", 8); /* copy interface name */
1872 info->supply_voltage_min_v = SUPPLY_VOLTAGE_MIN; /* set minimal supply voltage */
1873 info->supply_voltage_max_v = SUPPLY_VOLTAGE_MAX; /* set maximum supply voltage */
1874 info->max_current_ma = MAX_CURRENT; /* set maximum current */
1875 info->temperature_max = TEMPERATURE_MAX; /* set minimal temperature */
1876 info->temperature_min = TEMPERATURE_MIN; /* set maximum temperature */
1877 info->driver_version = DRIVER_VERSION; /* set driver version */
1878
1879 return 0; /* success return 0 */
1880}
CH9120_CMD_GET_MODE
#define CH9120_CMD_GET_MODE
Definition driver_ch9120.c:75
CH9120_CMD_GET_STATUS
#define CH9120_CMD_GET_STATUS
Definition driver_ch9120.c:56
CH9120_CMD_EXIT
#define CH9120_CMD_EXIT
Definition driver_ch9120.c:59
CH9120_CMD_GET_LEN
#define CH9120_CMD_GET_LEN
Definition driver_ch9120.c:86
MAX_CURRENT
#define MAX_CURRENT
Definition driver_ch9120.c:46
CH9120_CMD_SET_DST_IP
#define CH9120_CMD_SET_DST_IP
Definition driver_ch9120.c:65
CH9120_CMD_SET_GATEWAY
#define CH9120_CMD_SET_GATEWAY
Definition driver_ch9120.c:63
CH9120_CMD_GET_TIMEOUT
#define CH9120_CMD_GET_TIMEOUT
Definition driver_ch9120.c:84
CH9120_CMD_SET_CONFIG
#define CH9120_CMD_SET_CONFIG
Definition driver_ch9120.c:69
SUPPLY_VOLTAGE_MAX
#define SUPPLY_VOLTAGE_MAX
Definition driver_ch9120.c:45
CH9120_CMD_DHCP
#define CH9120_CMD_DHCP
Definition driver_ch9120.c:74
CH9120_CMD_RANDOM_PORT
#define CH9120_CMD_RANDOM_PORT
Definition driver_ch9120.c:67
CH9120_CMD_GET_GATEWAY
#define CH9120_CMD_GET_GATEWAY
Definition driver_ch9120.c:78
CH9120_CMD_SET_TIMEOUT
#define CH9120_CMD_SET_TIMEOUT
Definition driver_ch9120.c:70
CH9120_CMD_GET_NETMASK
#define CH9120_CMD_GET_NETMASK
Definition driver_ch9120.c:77
CH9120_CMD_SET_NETMASK
#define CH9120_CMD_SET_NETMASK
Definition driver_ch9120.c:62
CH9120_CMD_SET_MODE
#define CH9120_CMD_SET_MODE
Definition driver_ch9120.c:60
CH9120_CMD_GET_DST_IP
#define CH9120_CMD_GET_DST_IP
Definition driver_ch9120.c:80
TEMPERATURE_MAX
#define TEMPERATURE_MAX
Definition driver_ch9120.c:48
CH9120_CMD_GET_FLUSH
#define CH9120_CMD_GET_FLUSH
Definition driver_ch9120.c:87
CH9120_CMD_SET_FLUSH
#define CH9120_CMD_SET_FLUSH
Definition driver_ch9120.c:73
CH9120_CMD_GET_DST_PORT
#define CH9120_CMD_GET_DST_PORT
Definition driver_ch9120.c:81
CH9120_CMD_RESET
#define CH9120_CMD_RESET
Definition driver_ch9120.c:55
CH9120_CMD_SET_IP
#define CH9120_CMD_SET_IP
Definition driver_ch9120.c:61
CH9120_CMD_GET_BAUD
#define CH9120_CMD_GET_BAUD
Definition driver_ch9120.c:82
MANUFACTURER_NAME
#define MANUFACTURER_NAME
Definition driver_ch9120.c:43
TEMPERATURE_MIN
#define TEMPERATURE_MIN
Definition driver_ch9120.c:47
SUPPLY_VOLTAGE_MIN
#define SUPPLY_VOLTAGE_MIN
Definition driver_ch9120.c:44
CH9120_CMD_SET_DST_PORT
#define CH9120_CMD_SET_DST_PORT
Definition driver_ch9120.c:66
CH9120_CMD_GET_DISCONNECT
#define CH9120_CMD_GET_DISCONNECT
Definition driver_ch9120.c:85
CH9120_CMD_GET_CONFIG
#define CH9120_CMD_GET_CONFIG
Definition driver_ch9120.c:83
CH9120_CMD_GET_PORT
#define CH9120_CMD_GET_PORT
Definition driver_ch9120.c:79
CH9120_CMD_SAVE_TO_EEPROM
#define CH9120_CMD_SAVE_TO_EEPROM
Definition driver_ch9120.c:57
CH9120_CMD_SET_LEN
#define CH9120_CMD_SET_LEN
Definition driver_ch9120.c:72
CHIP_NAME
#define CHIP_NAME
chip information definition
Definition driver_ch9120.c:42
CH9120_CMD_SET_DISCONNECT
#define CH9120_CMD_SET_DISCONNECT
Definition driver_ch9120.c:71
DRIVER_VERSION
#define DRIVER_VERSION
Definition driver_ch9120.c:49
CH9120_CMD_SET_PORT
#define CH9120_CMD_SET_PORT
Definition driver_ch9120.c:64
CH9120_CMD_SET_BAUD
#define CH9120_CMD_SET_BAUD
Definition driver_ch9120.c:68
CH9120_CMD_GET_IP
#define CH9120_CMD_GET_IP
Definition driver_ch9120.c:76
CH9120_CMD_RUN_AND_RESET
#define CH9120_CMD_RUN_AND_RESET
Definition driver_ch9120.c:58
CH9120_CMD_CHIP_VERSION
#define CH9120_CMD_CHIP_VERSION
chip command definition
Definition driver_ch9120.c:54
driver_ch9120.h
driver ch9120 header file
ch9120_set_uart_baud
uint8_t ch9120_set_uart_baud(ch9120_handle_t *handle, uint32_t baud)
set uart baud
Definition driver_ch9120.c:984
ch9120_set_dest_ip
uint8_t ch9120_set_dest_ip(ch9120_handle_t *handle, uint8_t ip[4])
set dest ip
Definition driver_ch9120.c:839
ch9120_get_status
uint8_t ch9120_get_status(ch9120_handle_t *handle, ch9120_status_t *status)
get status
Definition driver_ch9120.c:343
ch9120_get_disconnect_with_no_rj45
uint8_t ch9120_get_disconnect_with_no_rj45(ch9120_handle_t *handle, ch9120_bool_t *enable)
get disconnect with no rj45 status
Definition driver_ch9120.c:1480
ch9120_get_gateway
uint8_t ch9120_get_gateway(ch9120_handle_t *handle, uint8_t ip[4])
get gateway
Definition driver_ch9120.c:732
ch9120_get_uart_baud
uint8_t ch9120_get_uart_baud(ch9120_handle_t *handle, uint32_t *baud)
get uart baud
Definition driver_ch9120.c:1022
ch9120_get_dest_port
uint8_t ch9120_get_dest_port(ch9120_handle_t *handle, uint16_t *num)
get dest port
Definition driver_ch9120.c:948
ch9120_info_t
struct ch9120_info_s ch9120_info_t
ch9120 information structure definition
ch9120_get_uart_buffer_length
uint8_t ch9120_get_uart_buffer_length(ch9120_handle_t *handle, uint32_t *len)
get uart buffer length
Definition driver_ch9120.c:1337
ch9120_uart_timeout_convert_to_data
uint8_t ch9120_uart_timeout_convert_to_data(ch9120_handle_t *handle, uint8_t reg, uint16_t *ms)
convert the register raw data to the offset
Definition driver_ch9120.c:1237
ch9120_init
uint8_t ch9120_init(ch9120_handle_t *handle)
initialize the chip
Definition driver_ch9120.c:1553
ch9120_get_ip
uint8_t ch9120_get_ip(ch9120_handle_t *handle, uint8_t ip[4])
get ip address
Definition driver_ch9120.c:588
ch9120_mode_t
ch9120_mode_t
ch9120 mode enumeration definition
Definition driver_ch9120.h:88
CH9120_UART_PRE_DELAY
#define CH9120_UART_PRE_DELAY
ch9120 uart pre delay definition
Definition driver_ch9120.h:63
ch9120_handle_t
struct ch9120_handle_s ch9120_handle_t
ch9120 handle structure definition
ch9120_get_source_port
uint8_t ch9120_get_source_port(ch9120_handle_t *handle, uint16_t *num)
get source port
Definition driver_ch9120.c:802
ch9120_parity_t
ch9120_parity_t
ch9120 parity enumeration definition
Definition driver_ch9120.h:99
ch9120_read
uint8_t ch9120_read(ch9120_handle_t *handle, uint8_t *buf, uint16_t *len)
read data
Definition driver_ch9120.c:1788
ch9120_get_uart_timeout
uint8_t ch9120_get_uart_timeout(ch9120_handle_t *handle, uint8_t *timeout)
get uart timeout
Definition driver_ch9120.c:1176
ch9120_set_dest_port
uint8_t ch9120_set_dest_port(ch9120_handle_t *handle, uint16_t num)
set dest port
Definition driver_ch9120.c:912
ch9120_reset
uint8_t ch9120_reset(ch9120_handle_t *handle)
reset the chip
Definition driver_ch9120.c:308
ch9120_set_source_port_random
uint8_t ch9120_set_source_port_random(ch9120_handle_t *handle, ch9120_bool_t enable)
enable or disable random source port number
Definition driver_ch9120.c:1264
ch9120_set_uart_config
uint8_t ch9120_set_uart_config(ch9120_handle_t *handle, uint8_t data_bit, ch9120_parity_t parity, uint8_t stop_bit)
set uart config
Definition driver_ch9120.c:1061
ch9120_set_uart_buffer_length
uint8_t ch9120_set_uart_buffer_length(ch9120_handle_t *handle, uint32_t len)
set uart buffer length
Definition driver_ch9120.c:1299
ch9120_set_uart_flush
uint8_t ch9120_set_uart_flush(ch9120_handle_t *handle, ch9120_bool_t enable)
enable or disable uart auto flush
Definition driver_ch9120.c:1374
ch9120_get_dest_ip
uint8_t ch9120_get_dest_ip(ch9120_handle_t *handle, uint8_t ip[4])
get dest ip
Definition driver_ch9120.c:877
ch9120_deinit
uint8_t ch9120_deinit(ch9120_handle_t *handle)
close the chip
Definition driver_ch9120.c:1695
ch9120_get_uart_flush
uint8_t ch9120_get_uart_flush(ch9120_handle_t *handle, ch9120_bool_t *enable)
get uart auto flush status
Definition driver_ch9120.c:1409
ch9120_set_gateway
uint8_t ch9120_set_gateway(ch9120_handle_t *handle, uint8_t ip[4])
set gateway
Definition driver_ch9120.c:694
ch9120_config_and_reset
uint8_t ch9120_config_and_reset(ch9120_handle_t *handle)
config and reset the chip
Definition driver_ch9120.c:411
ch9120_set_uart_timeout
uint8_t ch9120_set_uart_timeout(ch9120_handle_t *handle, uint8_t timeout)
set uart timeout
Definition driver_ch9120.c:1138
ch9120_get_uart_config
uint8_t ch9120_get_uart_config(ch9120_handle_t *handle, uint8_t *data_bit, ch9120_parity_t *parity, uint8_t *stop_bit)
get uart config
Definition driver_ch9120.c:1100
ch9120_exit
uint8_t ch9120_exit(ch9120_handle_t *handle)
exit
Definition driver_ch9120.c:445
ch9120_get_mode
uint8_t ch9120_get_mode(ch9120_handle_t *handle, ch9120_mode_t *mode)
get mode
Definition driver_ch9120.c:514
ch9120_set_disconnect_with_no_rj45
uint8_t ch9120_set_disconnect_with_no_rj45(ch9120_handle_t *handle, ch9120_bool_t enable)
enable or disable disconnect with no rj45
Definition driver_ch9120.c:1445
ch9120_info
uint8_t ch9120_info(ch9120_info_t *info)
get chip's information
Definition driver_ch9120.c:1861
ch9120_set_mode
uint8_t ch9120_set_mode(ch9120_handle_t *handle, ch9120_mode_t mode)
set mode
Definition driver_ch9120.c:479
ch9120_get_subnet_mask
uint8_t ch9120_get_subnet_mask(ch9120_handle_t *handle, uint8_t mask[4])
get subnet mask
Definition driver_ch9120.c:660
ch9120_uart_timeout_convert_to_register
uint8_t ch9120_uart_timeout_convert_to_register(ch9120_handle_t *handle, uint16_t ms, uint8_t *reg)
convert the uart timeout to the register raw data
Definition driver_ch9120.c:1210
ch9120_set_dhcp
uint8_t ch9120_set_dhcp(ch9120_handle_t *handle, ch9120_bool_t enable)
enable or disable dhcp
Definition driver_ch9120.c:1516
ch9120_bool_t
ch9120_bool_t
ch9120 bool enumeration definition
Definition driver_ch9120.h:70
ch9120_save_to_eeprom
uint8_t ch9120_save_to_eeprom(ch9120_handle_t *handle)
save to eeprom
Definition driver_ch9120.c:378
ch9120_set_subnet_mask
uint8_t ch9120_set_subnet_mask(ch9120_handle_t *handle, uint8_t mask[4])
set subnet mask
Definition driver_ch9120.c:622
ch9120_status_t
ch9120_status_t
ch9120 status enumeration definition
Definition driver_ch9120.h:79
ch9120_set_ip
uint8_t ch9120_set_ip(ch9120_handle_t *handle, uint8_t ip[4])
set ip address
Definition driver_ch9120.c:550
ch9120_write
uint8_t ch9120_write(ch9120_handle_t *handle, uint8_t *buf, uint16_t len)
write data
Definition driver_ch9120.c:1749
ch9120_get_version
uint8_t ch9120_get_version(ch9120_handle_t *handle, uint8_t *version)
get version
Definition driver_ch9120.c:275
ch9120_set_source_port
uint8_t ch9120_set_source_port(ch9120_handle_t *handle, uint16_t num)
set source port
Definition driver_ch9120.c:766
ch9120_set_command
uint8_t ch9120_set_command(ch9120_handle_t *handle, uint8_t *param, uint16_t len, uint8_t *out, uint16_t out_len, uint16_t pre_delay, uint16_t timeout)
set command
Definition driver_ch9120.c:1829
ch9120_handle_s::uart_flush
uint8_t(* uart_flush)(void)
Definition driver_ch9120.h:115
ch9120_handle_s::inited
uint8_t inited
Definition driver_ch9120.h:125
ch9120_handle_s::cfg_gpio_write
uint8_t(* cfg_gpio_write)(uint8_t data)
Definition driver_ch9120.h:122
ch9120_handle_s::uart_write
uint8_t(* uart_write)(uint8_t *buf, uint16_t len)
Definition driver_ch9120.h:116
ch9120_handle_s::delay_ms
void(* delay_ms)(uint32_t ms)
Definition driver_ch9120.h:123
ch9120_handle_s::cfg_gpio_init
uint8_t(* cfg_gpio_init)(void)
Definition driver_ch9120.h:120
ch9120_handle_s::uart_deinit
uint8_t(* uart_deinit)(void)
Definition driver_ch9120.h:113
ch9120_handle_s::reset_gpio_deinit
uint8_t(* reset_gpio_deinit)(void)
Definition driver_ch9120.h:118
ch9120_handle_s::debug_print
void(* debug_print)(const char *const fmt,...)
Definition driver_ch9120.h:124
ch9120_handle_s::uart_read
uint16_t(* uart_read)(uint8_t *buf, uint16_t len)
Definition driver_ch9120.h:114
ch9120_handle_s::reset_gpio_init
uint8_t(* reset_gpio_init)(void)
Definition driver_ch9120.h:117
ch9120_handle_s::buf
uint8_t buf[128]
Definition driver_ch9120.h:126
ch9120_handle_s::uart_init
uint8_t(* uart_init)(void)
Definition driver_ch9120.h:112
ch9120_handle_s::reset_gpio_write
uint8_t(* reset_gpio_write)(uint8_t data)
Definition driver_ch9120.h:119
ch9120_handle_s::cfg_gpio_deinit
uint8_t(* cfg_gpio_deinit)(void)
Definition driver_ch9120.h:121
ch9120_info_s::temperature_max
float temperature_max
Definition driver_ch9120.h:141
ch9120_info_s::supply_voltage_max_v
float supply_voltage_max_v
Definition driver_ch9120.h:138
ch9120_info_s::driver_version
uint32_t driver_version
Definition driver_ch9120.h:142
ch9120_info_s::temperature_min
float temperature_min
Definition driver_ch9120.h:140
ch9120_info_s::max_current_ma
float max_current_ma
Definition driver_ch9120.h:139
ch9120_info_s::manufacturer_name
char manufacturer_name[32]
Definition driver_ch9120.h:135
ch9120_info_s::supply_voltage_min_v
float supply_voltage_min_v
Definition driver_ch9120.h:137
ch9120_info_s::interface
char interface[8]
Definition driver_ch9120.h:136
ch9120_info_s::chip_name
char chip_name[32]
Definition driver_ch9120.h:134