LibDriver CH9120
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driver_ch9120.h
Go to the documentation of this file.
1
36
37#ifndef DRIVER_CH9120_H
38#define DRIVER_CH9120_H
39
40#include <stdio.h>
41#include <stdint.h>
42#include <string.h>
43
44#ifdef __cplusplus
45extern "C"{
46#endif
47
53
58
62#ifndef CH9120_UART_PRE_DELAY
63 #define CH9120_UART_PRE_DELAY 50
64#endif
65
69typedef enum
70{
74
83
94
106
110typedef struct ch9120_handle_s
111{
112 uint8_t (*uart_init)(void);
113 uint8_t (*uart_deinit)(void);
114 uint16_t (*uart_read)(uint8_t *buf, uint16_t len);
115 uint8_t (*uart_flush)(void);
116 uint8_t (*uart_write)(uint8_t *buf, uint16_t len);
117 uint8_t (*reset_gpio_init)(void);
118 uint8_t (*reset_gpio_deinit)(void);
119 uint8_t (*reset_gpio_write)(uint8_t data);
120 uint8_t (*cfg_gpio_init)(void);
121 uint8_t (*cfg_gpio_deinit)(void);
122 uint8_t (*cfg_gpio_write)(uint8_t data);
123 void (*delay_ms)(uint32_t ms);
124 void (*debug_print)(const char *const fmt, ...);
125 uint8_t inited;
126 uint8_t buf[128];
128
144
148
155
162#define DRIVER_CH9120_LINK_INIT(HANDLE, STRUCTURE) memset(HANDLE, 0, sizeof(STRUCTURE))
163
170#define DRIVER_CH9120_LINK_UART_INIT(HANDLE, FUC) (HANDLE)->uart_init = FUC
171
178#define DRIVER_CH9120_LINK_UART_DEINIT(HANDLE, FUC) (HANDLE)->uart_deinit = FUC
179
186#define DRIVER_CH9120_LINK_UART_READ(HANDLE, FUC) (HANDLE)->uart_read = FUC
187
194#define DRIVER_CH9120_LINK_UART_WRITE(HANDLE, FUC) (HANDLE)->uart_write = FUC
195
202#define DRIVER_CH9120_LINK_UART_FLUSH(HANDLE, FUC) (HANDLE)->uart_flush = FUC
203
210#define DRIVER_CH9120_LINK_RESET_GPIO_INIT(HANDLE, FUC) (HANDLE)->reset_gpio_init = FUC
211
218#define DRIVER_CH9120_LINK_RESET_GPIO_DEINIT(HANDLE, FUC) (HANDLE)->reset_gpio_deinit = FUC
219
226#define DRIVER_CH9120_LINK_RESET_GPIO_WRITE(HANDLE, FUC) (HANDLE)->reset_gpio_write = FUC
227
234#define DRIVER_CH9120_LINK_CFG_GPIO_INIT(HANDLE, FUC) (HANDLE)->cfg_gpio_init = FUC
235
242#define DRIVER_CH9120_LINK_CFG_GPIO_DEINIT(HANDLE, FUC) (HANDLE)->cfg_gpio_deinit = FUC
243
250#define DRIVER_CH9120_LINK_CFG_GPIO_WRITE(HANDLE, FUC) (HANDLE)->cfg_gpio_write = FUC
251
258#define DRIVER_CH9120_LINK_DELAY_MS(HANDLE, FUC) (HANDLE)->delay_ms = FUC
259
266#define DRIVER_CH9120_LINK_DEBUG_PRINT(HANDLE, FUC) (HANDLE)->debug_print = FUC
267
271
278
287uint8_t ch9120_info(ch9120_info_t *info);
288
302uint8_t ch9120_init(ch9120_handle_t *handle);
303
317uint8_t ch9120_deinit(ch9120_handle_t *handle);
318
331uint8_t ch9120_read(ch9120_handle_t *handle, uint8_t *buf, uint16_t *len);
332
345uint8_t ch9120_write(ch9120_handle_t *handle, uint8_t *buf, uint16_t len);
346
358uint8_t ch9120_get_version(ch9120_handle_t *handle, uint8_t *version);
359
370uint8_t ch9120_reset(ch9120_handle_t *handle);
371
383uint8_t ch9120_get_status(ch9120_handle_t *handle, ch9120_status_t *status);
384
396
408
419uint8_t ch9120_exit(ch9120_handle_t *handle);
420
432uint8_t ch9120_set_mode(ch9120_handle_t *handle, ch9120_mode_t mode);
433
445uint8_t ch9120_get_mode(ch9120_handle_t *handle, ch9120_mode_t *mode);
446
458uint8_t ch9120_set_ip(ch9120_handle_t *handle, uint8_t ip[4]);
459
471uint8_t ch9120_get_ip(ch9120_handle_t *handle, uint8_t ip[4]);
472
484uint8_t ch9120_set_subnet_mask(ch9120_handle_t *handle, uint8_t mask[4]);
485
497uint8_t ch9120_get_subnet_mask(ch9120_handle_t *handle, uint8_t mask[4]);
498
510uint8_t ch9120_set_gateway(ch9120_handle_t *handle, uint8_t ip[4]);
511
523uint8_t ch9120_get_gateway(ch9120_handle_t *handle, uint8_t ip[4]);
524
536uint8_t ch9120_set_source_port(ch9120_handle_t *handle, uint16_t num);
537
549uint8_t ch9120_get_source_port(ch9120_handle_t *handle, uint16_t *num);
550
562uint8_t ch9120_set_dest_ip(ch9120_handle_t *handle, uint8_t ip[4]);
563
575uint8_t ch9120_get_dest_ip(ch9120_handle_t *handle, uint8_t ip[4]);
576
588uint8_t ch9120_set_dest_port(ch9120_handle_t *handle, uint16_t num);
589
601uint8_t ch9120_get_dest_port(ch9120_handle_t *handle, uint16_t *num);
602
614uint8_t ch9120_set_uart_baud(ch9120_handle_t *handle, uint32_t baud);
615
627uint8_t ch9120_get_uart_baud(ch9120_handle_t *handle, uint32_t *baud);
628
642uint8_t ch9120_set_uart_config(ch9120_handle_t *handle, uint8_t data_bit, ch9120_parity_t parity, uint8_t stop_bit);
643
657uint8_t ch9120_get_uart_config(ch9120_handle_t *handle, uint8_t *data_bit, ch9120_parity_t *parity, uint8_t *stop_bit);
658
670uint8_t ch9120_set_uart_timeout(ch9120_handle_t *handle, uint8_t timeout);
671
683uint8_t ch9120_get_uart_timeout(ch9120_handle_t *handle, uint8_t *timeout);
684
696uint8_t ch9120_uart_timeout_convert_to_register(ch9120_handle_t *handle, uint16_t ms, uint8_t *reg);
697
709uint8_t ch9120_uart_timeout_convert_to_data(ch9120_handle_t *handle, uint8_t reg, uint16_t *ms);
710
723
735uint8_t ch9120_set_uart_buffer_length(ch9120_handle_t *handle, uint32_t len);
736
748uint8_t ch9120_get_uart_buffer_length(ch9120_handle_t *handle, uint32_t *len);
749
762
774uint8_t ch9120_get_uart_flush(ch9120_handle_t *handle, ch9120_bool_t *enable);
775
788
801
813uint8_t ch9120_set_dhcp(ch9120_handle_t *handle, ch9120_bool_t enable);
814
818
825
842uint8_t ch9120_set_command(ch9120_handle_t *handle,
843 uint8_t *param, uint16_t len,
844 uint8_t *out, uint16_t out_len,
845 uint16_t pre_delay, uint16_t timeout);
846
850
854
855#ifdef __cplusplus
856}
857#endif
858
859#endif
uint8_t ch9120_set_uart_baud(ch9120_handle_t *handle, uint32_t baud)
set uart baud
uint8_t ch9120_set_dest_ip(ch9120_handle_t *handle, uint8_t ip[4])
set dest ip
uint8_t ch9120_get_status(ch9120_handle_t *handle, ch9120_status_t *status)
get status
uint8_t ch9120_get_disconnect_with_no_rj45(ch9120_handle_t *handle, ch9120_bool_t *enable)
get disconnect with no rj45 status
uint8_t ch9120_get_gateway(ch9120_handle_t *handle, uint8_t ip[4])
get gateway
uint8_t ch9120_get_uart_baud(ch9120_handle_t *handle, uint32_t *baud)
get uart baud
uint8_t ch9120_get_dest_port(ch9120_handle_t *handle, uint16_t *num)
get dest port
struct ch9120_info_s ch9120_info_t
ch9120 information structure definition
uint8_t ch9120_get_uart_buffer_length(ch9120_handle_t *handle, uint32_t *len)
get uart buffer length
uint8_t ch9120_uart_timeout_convert_to_data(ch9120_handle_t *handle, uint8_t reg, uint16_t *ms)
convert the register raw data to the offset
uint8_t ch9120_init(ch9120_handle_t *handle)
initialize the chip
uint8_t ch9120_get_ip(ch9120_handle_t *handle, uint8_t ip[4])
get ip address
ch9120_mode_t
ch9120 mode enumeration definition
struct ch9120_handle_s ch9120_handle_t
ch9120 handle structure definition
uint8_t ch9120_get_source_port(ch9120_handle_t *handle, uint16_t *num)
get source port
ch9120_parity_t
ch9120 parity enumeration definition
uint8_t ch9120_read(ch9120_handle_t *handle, uint8_t *buf, uint16_t *len)
read data
uint8_t ch9120_get_uart_timeout(ch9120_handle_t *handle, uint8_t *timeout)
get uart timeout
uint8_t ch9120_set_dest_port(ch9120_handle_t *handle, uint16_t num)
set dest port
uint8_t ch9120_reset(ch9120_handle_t *handle)
reset the chip
uint8_t ch9120_set_source_port_random(ch9120_handle_t *handle, ch9120_bool_t enable)
enable or disable random source port number
uint8_t ch9120_set_uart_config(ch9120_handle_t *handle, uint8_t data_bit, ch9120_parity_t parity, uint8_t stop_bit)
set uart config
uint8_t ch9120_set_uart_buffer_length(ch9120_handle_t *handle, uint32_t len)
set uart buffer length
uint8_t ch9120_set_uart_flush(ch9120_handle_t *handle, ch9120_bool_t enable)
enable or disable uart auto flush
uint8_t ch9120_get_dest_ip(ch9120_handle_t *handle, uint8_t ip[4])
get dest ip
uint8_t ch9120_deinit(ch9120_handle_t *handle)
close the chip
uint8_t ch9120_get_uart_flush(ch9120_handle_t *handle, ch9120_bool_t *enable)
get uart auto flush status
uint8_t ch9120_set_gateway(ch9120_handle_t *handle, uint8_t ip[4])
set gateway
uint8_t ch9120_config_and_reset(ch9120_handle_t *handle)
config and reset the chip
uint8_t ch9120_set_uart_timeout(ch9120_handle_t *handle, uint8_t timeout)
set uart timeout
uint8_t ch9120_get_uart_config(ch9120_handle_t *handle, uint8_t *data_bit, ch9120_parity_t *parity, uint8_t *stop_bit)
get uart config
uint8_t ch9120_exit(ch9120_handle_t *handle)
exit
uint8_t ch9120_get_mode(ch9120_handle_t *handle, ch9120_mode_t *mode)
get mode
uint8_t ch9120_set_disconnect_with_no_rj45(ch9120_handle_t *handle, ch9120_bool_t enable)
enable or disable disconnect with no rj45
uint8_t ch9120_info(ch9120_info_t *info)
get chip's information
uint8_t ch9120_set_mode(ch9120_handle_t *handle, ch9120_mode_t mode)
set mode
uint8_t ch9120_get_subnet_mask(ch9120_handle_t *handle, uint8_t mask[4])
get subnet mask
uint8_t ch9120_uart_timeout_convert_to_register(ch9120_handle_t *handle, uint16_t ms, uint8_t *reg)
convert the uart timeout to the register raw data
uint8_t ch9120_set_dhcp(ch9120_handle_t *handle, ch9120_bool_t enable)
enable or disable dhcp
ch9120_bool_t
ch9120 bool enumeration definition
uint8_t ch9120_save_to_eeprom(ch9120_handle_t *handle)
save to eeprom
uint8_t ch9120_set_subnet_mask(ch9120_handle_t *handle, uint8_t mask[4])
set subnet mask
ch9120_status_t
ch9120 status enumeration definition
uint8_t ch9120_set_ip(ch9120_handle_t *handle, uint8_t ip[4])
set ip address
uint8_t ch9120_write(ch9120_handle_t *handle, uint8_t *buf, uint16_t len)
write data
uint8_t ch9120_get_version(ch9120_handle_t *handle, uint8_t *version)
get version
uint8_t ch9120_set_source_port(ch9120_handle_t *handle, uint16_t num)
set source port
@ CH9120_MODE_UDP_CLIENT
@ CH9120_MODE_TCP_SERVER
@ CH9120_MODE_UDP_SERVER
@ CH9120_MODE_TCP_CLIENT
@ CH9120_PARITY_EVEN
@ CH9120_PARITY_ODD
@ CH9120_PARITY_MARK
@ CH9120_PARITY_SPACE
@ CH9120_PARITY_NONE
@ CH9120_BOOL_FALSE
@ CH9120_BOOL_TRUE
@ CH9120_STATUS_CONNECT
@ CH9120_STATUS_DISCONNECT
uint8_t ch9120_set_command(ch9120_handle_t *handle, uint8_t *param, uint16_t len, uint8_t *out, uint16_t out_len, uint16_t pre_delay, uint16_t timeout)
set command
ch9120 handle structure definition
uint8_t(* uart_flush)(void)
uint8_t(* cfg_gpio_write)(uint8_t data)
uint8_t(* uart_write)(uint8_t *buf, uint16_t len)
void(* delay_ms)(uint32_t ms)
uint8_t(* cfg_gpio_init)(void)
uint8_t(* uart_deinit)(void)
uint8_t(* reset_gpio_deinit)(void)
void(* debug_print)(const char *const fmt,...)
uint16_t(* uart_read)(uint8_t *buf, uint16_t len)
uint8_t(* reset_gpio_init)(void)
uint8_t buf[128]
uint8_t(* uart_init)(void)
uint8_t(* reset_gpio_write)(uint8_t data)
uint8_t(* cfg_gpio_deinit)(void)
ch9120 information structure definition
float supply_voltage_max_v
uint32_t driver_version
char manufacturer_name[32]
float supply_voltage_min_v
char chip_name[32]