LibDriver CH9121
Loading...
Searching...
No Matches
driver_ch9121.c
Go to the documentation of this file.
1
36
37#include "driver_ch9121.h"
38
42#define CHIP_NAME "WCH CH9121"
43#define MANUFACTURER_NAME "WCH"
44#define SUPPLY_VOLTAGE_MIN 2.7f
45#define SUPPLY_VOLTAGE_MAX 3.6f
46#define MAX_CURRENT 190.0f
47#define TEMPERATURE_MIN -40.0f
48#define TEMPERATURE_MAX 85.0f
49#define DRIVER_VERSION 1000
50
54#define CH9121_CMD_CHIP_VERSION 0x01
55#define CH9121_CMD_RESET 0x02
56#define CH9121_CMD_SAVE_TO_EEPROM 0x0D
57#define CH9121_CMD_RUN_AND_RESET 0x0E
58#define CH9121_CMD_EXIT 0x5E
59#define CH9121_CMD_DHCP 0x33
60#define CH9121_CMD_MAC 0x81
61#define CH9121_CMD_SET_IP 0x11
62#define CH9121_CMD_SET_NETMASK 0x12
63#define CH9121_CMD_SET_GATEWAY 0x13
64#define CH9121_CMD_GET_IP 0x61
65#define CH9121_CMD_GET_NETMASK 0x62
66#define CH9121_CMD_GET_GATEWAY 0x63
67#define CH9121_CMD_DISCONNECT 0x24
68
72#define CH9121_CMD_PORT1_GET_STATUS 0x03
73#define CH9121_CMD_PORT1_SET_MODE 0x10
74#define CH9121_CMD_PORT1_SET_PORT 0x14
75#define CH9121_CMD_PORT1_SET_DST_IP 0x15
76#define CH9121_CMD_PORT1_SET_DST_PORT 0x16
77#define CH9121_CMD_PORT1_SET_BAUD 0x21
78#define CH9121_CMD_PORT1_SET_CONFIG 0x22
79#define CH9121_CMD_PORT1_SET_TIMEOUT 0x23
80#define CH9121_CMD_PORT1_GET_MODE 0x60
81#define CH9121_CMD_PORT1_GET_PORT 0x64
82#define CH9121_CMD_PORT1_GET_DST_IP 0x65
83#define CH9121_CMD_PORT1_GET_DST_PORT 0x66
84#define CH9121_CMD_PORT1_GET_BAUD 0x71
85#define CH9121_CMD_PORT1_GET_CONFIG 0x72
86#define CH9121_CMD_PORT1_GET_TIMEOUT 0x73
87#define CH9121_CMD_PORT2_GET_STATUS 0x04
88#define CH9121_CMD_PORT2_SET_MODE 0x40
89#define CH9121_CMD_PORT2_SET_PORT 0x41
90#define CH9121_CMD_PORT2_SET_DST_IP 0x42
91#define CH9121_CMD_PORT2_SET_DST_PORT 0x43
92#define CH9121_CMD_PORT2_SET_BAUD 0x44
93#define CH9121_CMD_PORT2_SET_CONFIG 0x45
94#define CH9121_CMD_PORT2_SET_TIMEOUT 0x46
95#define CH9121_CMD_PORT2_GET_MODE 0x90
96#define CH9121_CMD_PORT2_GET_PORT 0x91
97#define CH9121_CMD_PORT2_GET_DST_IP 0x92
98#define CH9121_CMD_PORT2_GET_DST_PORT 0x93
99#define CH9121_CMD_PORT2_GET_BAUD 0x94
100#define CH9121_CMD_PORT2_GET_CONFIG 0x95
101#define CH9121_CMD_PORT2_GET_TIMEOUT 0x96
102
106#define CH9121_CMD_PORT1_RANDOM_PORT 0x17
107#define CH9121_CMD_PORT1_LEN 0x25
108#define CH9121_CMD_PORT1_FLUSH 0x26
109#define CH9121_CMD_PORT1_DOMAIN 0x34
110#define CH9121_CMD_PORT2_ENABLE 0x39
111#define CH9121_CMD_PORT2_RANDOM_PORT 0x47
112#define CH9121_CMD_PORT2_LEN 0x48
113#define CH9121_CMD_PORT2_FLUSH 0x49
114
130static uint8_t a_ch9121_write_check(ch9121_handle_t *handle,
131 uint8_t *param, uint16_t len,
132 uint16_t pre_delay, uint16_t timeout)
133{
134 uint16_t t;
135 uint8_t res;
136
137 if (len > 126) /* check length */
138 {
139 handle->debug_print("ch9121: len is invalid.\n"); /* len is invalid */
140
141 return 2; /* return error */
142 }
143
144 handle->buf[0] = 0x57; /* set header 0 */
145 handle->buf[1] = 0xAB; /* set header 1 */
146 memcpy(&handle->buf[2], param, len); /* copy param */
147 res = handle->cfg_gpio_write(0); /* set low */
148 if (res != 0) /* check result */
149 {
150 return 1; /* return error */
151 }
152 res = handle->uart_flush(); /* uart flush */
153 if (res != 0) /* check result */
154 {
155 return 1; /* return error */
156 }
157 if (handle->uart_write(handle->buf, 2 + len) != 0) /* write command */
158 {
159 handle->debug_print("ch9121: write failed.\n"); /* write failed */
160 (void)handle->cfg_gpio_write(1); /* set high */
161
162 return 1; /* return error */
163 }
164 if (pre_delay != 0) /* check pre_delay */
165 {
166 handle->delay_ms(pre_delay); /* delay pre_delay */
167 }
168
169 t = timeout / 10; /* 10ms */
170 while (t != 0) /* check timeout */
171 {
172 if (handle->uart_read(&res, 1) == 1) /* read data */
173 {
174 if (res == 0xAA) /* check 0xAA */
175 {
176 res = handle->cfg_gpio_write(1); /* set high */
177 if (res != 0) /* check result */
178 {
179 return 1; /* return error */
180 }
181
182 return 0; /* success return 0 */
183 }
184 else
185 {
186 handle->debug_print("ch9121: error.\n"); /* error */
187 (void)handle->cfg_gpio_write(1); /* set high */
188
189 return 3; /* return error */
190 }
191 }
192 handle->delay_ms(10); /* delay 10ms */
193 t--; /* timeout-- */
194 }
195
196 handle->debug_print("ch9121: timeout.\n"); /* timeout */
197 (void)handle->cfg_gpio_write(1); /* set high */
198
199 return 4; /* return error */
200}
201
218static uint8_t a_ch9121_write_read(ch9121_handle_t *handle,
219 uint8_t *param, uint16_t len,
220 uint8_t *out, uint16_t out_len,
221 uint16_t pre_delay, uint16_t timeout)
222{
223 uint8_t res;
224 uint16_t t;
225 uint16_t point;
226
227 if (len > 126) /* check length */
228 {
229 handle->debug_print("ch9121: len is invalid.\n"); /* len is invalid */
230
231 return 2; /* return error */
232 }
233
234 handle->buf[0] = 0x57; /* set header 0 */
235 handle->buf[1] = 0xAB; /* set header 1 */
236 memcpy(&handle->buf[2], param, len); /* copy param */
237 res = handle->cfg_gpio_write(0); /* set low */
238 if (res != 0) /* check result */
239 {
240 return 1; /* return error */
241 }
242 res = handle->uart_flush(); /* uart flush */
243 if (res != 0) /* check result */
244 {
245 return 1; /* return error */
246 }
247 if (handle->uart_write(handle->buf, 2 + len) != 0) /* write command */
248 {
249 handle->debug_print("ch9121: write failed.\n"); /* write failed */
250 (void)handle->cfg_gpio_write(1); /* set high */
251
252 return 1; /* return error */
253 }
254 if (pre_delay != 0) /* check pre_delay */
255 {
256 handle->delay_ms(pre_delay); /* delay pre_delay */
257 }
258
259 point = 0; /* init 0 */
260 t = timeout / 10; /* 10ms */
261 while (t != 0) /* check timeout */
262 {
263 uint16_t l;
264
265 l = handle->uart_read(&out[point], out_len - point); /* read data */
266 if (l != 0)
267 {
268 point += l; /* point += l*/
269 if (point >= out_len) /* check length */
270 {
271 res = handle->cfg_gpio_write(1); /* set high */
272 if (res != 0) /* check result */
273 {
274 return 1; /* return error */
275 }
276
277 return 0; /* success return 0 */
278 }
279 }
280 handle->delay_ms(10); /* delay 10ms */
281 t--; /* timeout-- */
282 }
283
284 handle->debug_print("ch9121: timeout.\n"); /* timeout */
285 (void)handle->cfg_gpio_write(1); /* set high */
286
287 return 3; /* return error */
288}
289
301uint8_t ch9121_get_version(ch9121_handle_t *handle, uint8_t *version)
302{
303 uint8_t cmd;
304
305 if (handle == NULL) /* check handle */
306 {
307 return 2; /* return error */
308 }
309 if (handle->inited != 1) /* check handle initialization */
310 {
311 return 3; /* return error */
312 }
313
314 cmd = CH9121_CMD_CHIP_VERSION; /* set chip version */
315 if (a_ch9121_write_read(handle, &cmd, 1, version, 1,
316 CH9121_UART_PRE_DELAY, 1000) != 0) /* get version */
317 {
318 return 1; /* return error */
319 }
320
321 return 0; /* success return 0 */
322}
323
334uint8_t ch9121_reset(ch9121_handle_t *handle)
335{
336 uint8_t cmd;
337
338 if (handle == NULL) /* check handle */
339 {
340 return 2; /* return error */
341 }
342 if (handle->inited != 1) /* check handle initialization */
343 {
344 return 3; /* return error */
345 }
346
347 cmd = CH9121_CMD_RESET; /* set reset */
348 if (a_ch9121_write_check(handle, &cmd, 1,
349 CH9121_UART_PRE_DELAY, 1000) != 0) /* reset */
350 {
351 return 1; /* return error */
352 }
353 handle->delay_ms(1000); /* delay 1000ms */
354
355 return 0; /* success return 0 */
356}
357
368uint8_t ch9121_save_to_eeprom(ch9121_handle_t *handle)
369{
370 uint8_t cmd;
371
372 if (handle == NULL) /* check handle */
373 {
374 return 2; /* return error */
375 }
376 if (handle->inited != 1) /* check handle initialization */
377 {
378 return 3; /* return error */
379 }
380
381 cmd = CH9121_CMD_SAVE_TO_EEPROM; /* set save to eeprom */
382 if (a_ch9121_write_check(handle, &cmd, 1,
383 CH9121_UART_PRE_DELAY, 1000) != 0) /* save to eeprom */
384 {
385 return 1; /* return error */
386 }
387
388 return 0; /* success return 0 */
389}
390
401uint8_t ch9121_config_and_reset(ch9121_handle_t *handle)
402{
403 uint8_t cmd;
404
405 if (handle == NULL) /* check handle */
406 {
407 return 2; /* return error */
408 }
409 if (handle->inited != 1) /* check handle initialization */
410 {
411 return 3; /* return error */
412 }
413
414 cmd = CH9121_CMD_RUN_AND_RESET; /* set run config reset */
415 if (a_ch9121_write_check(handle, &cmd, 1,
416 CH9121_UART_PRE_DELAY, 1000) != 0) /* run config reset */
417 {
418 return 1; /* return error */
419 }
420 handle->delay_ms(1000); /* delay 1000ms */
421
422 return 0; /* success return 0 */
423}
424
435uint8_t ch9121_exit(ch9121_handle_t *handle)
436{
437 uint8_t cmd;
438
439 if (handle == NULL) /* check handle */
440 {
441 return 2; /* return error */
442 }
443 if (handle->inited != 1) /* check handle initialization */
444 {
445 return 3; /* return error */
446 }
447
448 cmd = CH9121_CMD_EXIT; /* set exit */
449 if (a_ch9121_write_check(handle, &cmd, 1,
450 CH9121_UART_PRE_DELAY, 1000) != 0) /* exit */
451 {
452 return 1; /* return error */
453 }
454
455 return 0; /* success return 0 */
456}
457
469uint8_t ch9121_set_dhcp(ch9121_handle_t *handle, ch9121_bool_t enable)
470{
471 uint8_t cmd[2];
472
473 if (handle == NULL) /* check handle */
474 {
475 return 2; /* return error */
476 }
477 if (handle->inited != 1) /* check handle initialization */
478 {
479 return 3; /* return error */
480 }
481
482 cmd[0] = CH9121_CMD_DHCP; /* set dhcp */
483 cmd[1] = enable; /* set bool */
484 if (a_ch9121_write_check(handle, cmd, 2,
485 CH9121_UART_PRE_DELAY, 1000) != 0) /* dhcp */
486 {
487 return 1; /* return error */
488 }
489
490 return 0; /* success return 0 */
491}
492
504uint8_t ch9121_get_mac(ch9121_handle_t *handle, uint8_t mac[6])
505{
506 uint8_t cmd;
507
508 if (handle == NULL) /* check handle */
509 {
510 return 2; /* return error */
511 }
512 if (handle->inited != 1) /* check handle initialization */
513 {
514 return 3; /* return error */
515 }
516
517 cmd = CH9121_CMD_MAC; /* set mac */
518 if (a_ch9121_write_read(handle, &cmd, 1, mac, 6,
519 CH9121_UART_PRE_DELAY, 1000) != 0) /* mac*/
520 {
521 return 1; /* return error */
522 }
523
524 return 0; /* success return 0 */
525}
526
539uint8_t ch9121_get_status(ch9121_handle_t *handle, ch9121_port_t port, ch9121_status_t *status)
540{
541 uint8_t cmd;
542 uint8_t param;
543
544 if (handle == NULL) /* check handle */
545 {
546 return 2; /* return error */
547 }
548 if (handle->inited != 1) /* check handle initialization */
549 {
550 return 3; /* return error */
551 }
552
553 if (port == CH9121_PORT1) /* port1 */
554 {
555 cmd = CH9121_CMD_PORT1_GET_STATUS; /* get port1 status */
556 }
557 else /* port2 */
558 {
559 cmd = CH9121_CMD_PORT2_GET_STATUS; /* get port2 status */
560 }
561 if (a_ch9121_write_read(handle, &cmd, 1, &param, 1,
562 CH9121_UART_PRE_DELAY, 1000) != 0) /* get status */
563 {
564 return 1; /* return error */
565 }
566 *status = (ch9121_status_t)(param); /* get the status */
567
568 return 0; /* success return 0 */
569}
570
583uint8_t ch9121_set_mode(ch9121_handle_t *handle, ch9121_port_t port, ch9121_mode_t mode)
584{
585 uint8_t cmd[2];
586
587 if (handle == NULL) /* check handle */
588 {
589 return 2; /* return error */
590 }
591 if (handle->inited != 1) /* check handle initialization */
592 {
593 return 3; /* return error */
594 }
595
596 if (port == CH9121_PORT1) /* port1 */
597 {
598 cmd[0] = CH9121_CMD_PORT1_SET_MODE; /* set port1 mode */
599 }
600 else /* port2 */
601 {
602 cmd[0] = CH9121_CMD_PORT2_SET_MODE; /* set port2 mode */
603 }
604 cmd[1] = mode; /* set mode */
605 if (a_ch9121_write_check(handle, cmd, 2,
606 CH9121_UART_PRE_DELAY, 1000) != 0) /* write mode */
607 {
608 return 1; /* return error */
609 }
610
611 return 0; /* success return 0 */
612}
613
626uint8_t ch9121_get_mode(ch9121_handle_t *handle, ch9121_port_t port, ch9121_mode_t *mode)
627{
628 uint8_t cmd;
629 uint8_t param;
630
631 if (handle == NULL) /* check handle */
632 {
633 return 2; /* return error */
634 }
635 if (handle->inited != 1) /* check handle initialization */
636 {
637 return 3; /* return error */
638 }
639
640 if (port == CH9121_PORT1) /* port1 */
641 {
642 cmd = CH9121_CMD_PORT1_GET_MODE; /* get port1 mode */
643 }
644 else /* port2 */
645 {
646 cmd = CH9121_CMD_PORT2_GET_MODE; /* get port2 mode */
647 }
648 if (a_ch9121_write_read(handle, &cmd, 1, &param, 1,
649 CH9121_UART_PRE_DELAY, 1000) != 0) /* get mode */
650 {
651 return 1; /* return error */
652 }
653 *mode = (ch9121_mode_t)(param); /* get mode */
654
655 return 0; /* success return 0 */
656}
657
669uint8_t ch9121_set_ip(ch9121_handle_t *handle, uint8_t ip[4])
670{
671 uint8_t cmd[5];
672
673 if (handle == NULL) /* check handle */
674 {
675 return 2; /* return error */
676 }
677 if (handle->inited != 1) /* check handle initialization */
678 {
679 return 3; /* return error */
680 }
681
682 cmd[0] = CH9121_CMD_SET_IP; /* set ip */
683 cmd[1] = ip[0]; /* set ip[0] */
684 cmd[2] = ip[1]; /* set ip[1] */
685 cmd[3] = ip[2]; /* set ip[2] */
686 cmd[4] = ip[3]; /* set ip[3] */
687 if (a_ch9121_write_check(handle, cmd, 5,
688 CH9121_UART_PRE_DELAY, 1000) != 0) /* write ip */
689 {
690 return 1; /* return error */
691 }
692
693 return 0; /* success return 0 */
694}
695
707uint8_t ch9121_get_ip(ch9121_handle_t *handle, uint8_t ip[4])
708{
709 uint8_t cmd;
710
711 if (handle == NULL) /* check handle */
712 {
713 return 2; /* return error */
714 }
715 if (handle->inited != 1) /* check handle initialization */
716 {
717 return 3; /* return error */
718 }
719
720 cmd = CH9121_CMD_GET_IP; /* get ip */
721 if (a_ch9121_write_read(handle, &cmd, 1, ip, 4,
722 CH9121_UART_PRE_DELAY, 1000) != 0) /* read ip */
723 {
724 return 1; /* return error */
725 }
726
727 return 0; /* success return 0 */
728}
729
741uint8_t ch9121_set_subnet_mask(ch9121_handle_t *handle, uint8_t mask[4])
742{
743 uint8_t cmd[5];
744
745 if (handle == NULL) /* check handle */
746 {
747 return 2; /* return error */
748 }
749 if (handle->inited != 1) /* check handle initialization */
750 {
751 return 3; /* return error */
752 }
753
754 cmd[0] = CH9121_CMD_SET_NETMASK ; /* set sub mask */
755 cmd[1] = mask[0]; /* set mask[0] */
756 cmd[2] = mask[1]; /* set mask[1] */
757 cmd[3] = mask[2]; /* set mask[2] */
758 cmd[4] = mask[3]; /* set mask[3] */
759 if (a_ch9121_write_check(handle, cmd, 5,
760 CH9121_UART_PRE_DELAY, 1000) != 0) /* write subnet mask */
761 {
762 return 1; /* return error */
763 }
764
765 return 0; /* success return 0 */
766}
767
779uint8_t ch9121_get_subnet_mask(ch9121_handle_t *handle, uint8_t mask[4])
780{
781 uint8_t cmd;
782
783 if (handle == NULL) /* check handle */
784 {
785 return 2; /* return error */
786 }
787 if (handle->inited != 1) /* check handle initialization */
788 {
789 return 3; /* return error */
790 }
791
792 cmd = CH9121_CMD_GET_NETMASK ; /* get mask */
793 if (a_ch9121_write_read(handle, &cmd, 1, mask, 4,
794 CH9121_UART_PRE_DELAY, 1000) != 0) /* read subnet mask */
795 {
796 return 1; /* return error */
797 }
798
799 return 0; /* success return 0 */
800}
801
813uint8_t ch9121_set_gateway(ch9121_handle_t *handle, uint8_t ip[4])
814{
815 uint8_t cmd[5];
816
817 if (handle == NULL) /* check handle */
818 {
819 return 2; /* return error */
820 }
821 if (handle->inited != 1) /* check handle initialization */
822 {
823 return 3; /* return error */
824 }
825
826 cmd[0] = CH9121_CMD_SET_GATEWAY ; /* set gateway */
827 cmd[1] = ip[0]; /* set ip[0] */
828 cmd[2] = ip[1]; /* set ip[1] */
829 cmd[3] = ip[2]; /* set ip[2] */
830 cmd[4] = ip[3]; /* set ip[3] */
831 if (a_ch9121_write_check(handle, cmd, 5,
832 CH9121_UART_PRE_DELAY, 1000) != 0) /* write ip */
833 {
834 return 1; /* return error */
835 }
836
837 return 0; /* success return 0 */
838}
839
851uint8_t ch9121_get_gateway(ch9121_handle_t *handle, uint8_t ip[4])
852{
853 uint8_t cmd;
854
855 if (handle == NULL) /* check handle */
856 {
857 return 2; /* return error */
858 }
859 if (handle->inited != 1) /* check handle initialization */
860 {
861 return 3; /* return error */
862 }
863
864 cmd = CH9121_CMD_GET_GATEWAY; /* get gateway */
865 if (a_ch9121_write_read(handle, &cmd, 1, ip, 4,
866 CH9121_UART_PRE_DELAY, 1000) != 0) /* read gateway */
867 {
868 return 1; /* return error */
869 }
870
871 return 0; /* success return 0 */
872}
873
886uint8_t ch9121_set_source_port(ch9121_handle_t *handle, ch9121_port_t port, uint16_t num)
887{
888 uint8_t cmd[3];
889
890 if (handle == NULL) /* check handle */
891 {
892 return 2; /* return error */
893 }
894 if (handle->inited != 1) /* check handle initialization */
895 {
896 return 3; /* return error */
897 }
898
899 if (port == CH9121_PORT1) /* port1 */
900 {
901 cmd[0] = CH9121_CMD_PORT1_SET_PORT; /* set port1 port */
902 }
903 else /* port2 */
904 {
905 cmd[0] = CH9121_CMD_PORT2_SET_PORT; /* set port2 port */
906 }
907 cmd[1] = (num >> 0) & 0xFF; /* set port msb */
908 cmd[2] = (num >> 8) & 0xFF; /* set port lsb */
909 if (a_ch9121_write_check(handle, cmd, 3,
910 CH9121_UART_PRE_DELAY, 1000) != 0) /* write port */
911 {
912 return 1; /* return error */
913 }
914
915 return 0; /* success return 0 */
916}
917
930uint8_t ch9121_get_source_port(ch9121_handle_t *handle, ch9121_port_t port, uint16_t *num)
931{
932 uint8_t cmd;
933 uint8_t buf[2];
934
935 if (handle == NULL) /* check handle */
936 {
937 return 2; /* return error */
938 }
939 if (handle->inited != 1) /* check handle initialization */
940 {
941 return 3; /* return error */
942 }
943
944 if (port == CH9121_PORT1) /* port1 */
945 {
946 cmd = CH9121_CMD_PORT1_GET_PORT; /* get port1 port */
947 }
948 else /* port2 */
949 {
950 cmd = CH9121_CMD_PORT2_GET_PORT; /* get port2 port */
951 }
952 if (a_ch9121_write_read(handle, &cmd, 1, buf, 2,
953 CH9121_UART_PRE_DELAY, 1000) != 0) /* get port */
954 {
955 return 1; /* return error */
956 }
957 *num= (uint16_t)((uint16_t)buf[1] << 8 | buf[0]); /* get port */
958
959 return 0; /* success return 0 */
960}
961
974uint8_t ch9121_set_dest_ip(ch9121_handle_t *handle, ch9121_port_t port, uint8_t ip[4])
975{
976 uint8_t cmd[5];
977
978 if (handle == NULL) /* check handle */
979 {
980 return 2; /* return error */
981 }
982 if (handle->inited != 1) /* check handle initialization */
983 {
984 return 3; /* return error */
985 }
986
987 if (port == CH9121_PORT1) /* port1 */
988 {
989 cmd[0] = CH9121_CMD_PORT1_SET_DST_IP; /* set port1 dest ip */
990 }
991 else /* port2 */
992 {
993 cmd[0] = CH9121_CMD_PORT2_SET_DST_IP; /* set port2 dest ip */
994 }
995 cmd[1] = ip[0]; /* set ip[0] */
996 cmd[2] = ip[1]; /* set ip[1] */
997 cmd[3] = ip[2]; /* set ip[0] */
998 cmd[4] = ip[3]; /* set ip[1] */
999 if (a_ch9121_write_check(handle, cmd, 5,
1000 CH9121_UART_PRE_DELAY, 1000) != 0) /* write dest ip */
1001 {
1002 return 1; /* return error */
1003 }
1004
1005 return 0; /* success return 0 */
1006}
1007
1020uint8_t ch9121_get_dest_ip(ch9121_handle_t *handle, ch9121_port_t port, uint8_t ip[4])
1021{
1022 uint8_t cmd;
1023
1024 if (handle == NULL) /* check handle */
1025 {
1026 return 2; /* return error */
1027 }
1028 if (handle->inited != 1) /* check handle initialization */
1029 {
1030 return 3; /* return error */
1031 }
1032
1033 if (port == CH9121_PORT1) /* port1 */
1034 {
1035 cmd = CH9121_CMD_PORT1_GET_DST_IP; /* get port1 dest ip */
1036 }
1037 else /* port2 */
1038 {
1039 cmd = CH9121_CMD_PORT2_GET_DST_IP; /* get port2 dest ip */
1040 }
1041 if (a_ch9121_write_read(handle, &cmd, 1, ip, 4,
1042 CH9121_UART_PRE_DELAY, 1000) != 0) /* get dest ip */
1043 {
1044 return 1; /* return error */
1045 }
1046
1047 return 0; /* success return 0 */
1048}
1049
1062uint8_t ch9121_set_dest_port(ch9121_handle_t *handle, ch9121_port_t port, uint16_t num)
1063{
1064 uint8_t cmd[3];
1065
1066 if (handle == NULL) /* check handle */
1067 {
1068 return 2; /* return error */
1069 }
1070 if (handle->inited != 1) /* check handle initialization */
1071 {
1072 return 3; /* return error */
1073 }
1074
1075 if (port == CH9121_PORT1) /* port1 */
1076 {
1077 cmd[0] = CH9121_CMD_PORT1_SET_DST_PORT; /* set port1 dest port */
1078 }
1079 else /* port2 */
1080 {
1081 cmd[0] = CH9121_CMD_PORT2_SET_DST_PORT; /* set port2 dest port */
1082 }
1083 cmd[1] = (num >> 0) & 0xFF; /* set port msb */
1084 cmd[2] = (num >> 8) & 0xFF; /* set port lsb */
1085 if (a_ch9121_write_check(handle, cmd, 3,
1086 CH9121_UART_PRE_DELAY, 1000) != 0) /* write dest port */
1087 {
1088 return 1; /* return error */
1089 }
1090
1091 return 0; /* success return 0 */
1092}
1093
1106uint8_t ch9121_get_dest_port(ch9121_handle_t *handle, ch9121_port_t port, uint16_t *num)
1107{
1108 uint8_t cmd;
1109 uint8_t buf[2];
1110
1111 if (handle == NULL) /* check handle */
1112 {
1113 return 2; /* return error */
1114 }
1115 if (handle->inited != 1) /* check handle initialization */
1116 {
1117 return 3; /* return error */
1118 }
1119
1120 if (port == CH9121_PORT1) /* port1 */
1121 {
1122 cmd = CH9121_CMD_PORT1_GET_DST_PORT; /* get port1 dest port */
1123 }
1124 else /* port2 */
1125 {
1126 cmd = CH9121_CMD_PORT2_GET_DST_PORT; /* get port2 dest port */
1127 }
1128 if (a_ch9121_write_read(handle, &cmd, 1, buf, 2,
1129 CH9121_UART_PRE_DELAY, 1000) != 0) /* get dest port */
1130 {
1131 return 1; /* return error */
1132 }
1133 *num= (uint16_t)((uint16_t)buf[1] << 8 | buf[0]); /* get port */
1134
1135 return 0; /* success return 0 */
1136}
1137
1150uint8_t ch9121_set_uart_baud(ch9121_handle_t *handle, ch9121_port_t port, uint32_t baud)
1151{
1152 uint8_t cmd[5];
1153
1154 if (handle == NULL) /* check handle */
1155 {
1156 return 2; /* return error */
1157 }
1158 if (handle->inited != 1) /* check handle initialization */
1159 {
1160 return 3; /* return error */
1161 }
1162
1163 if (port == CH9121_PORT1) /* port1 */
1164 {
1165 cmd[0] = CH9121_CMD_PORT1_SET_BAUD; /* set port1 baud */
1166 }
1167 else /* port2 */
1168 {
1169 cmd[0] = CH9121_CMD_PORT2_SET_BAUD; /* set port2 baud */
1170 }
1171 cmd[1] = (baud >> 0) & 0xFF; /* set baud[0] */
1172 cmd[2] = (baud >> 8) & 0xFF; /* set baud[8] */
1173 cmd[3] = (baud >> 16) & 0xFF; /* set baud[16] */
1174 cmd[4] = (baud >> 24) & 0xFF; /* set baud[24] */
1175 if (a_ch9121_write_check(handle, cmd, 5,
1176 CH9121_UART_PRE_DELAY, 1000) != 0) /* write dest port */
1177 {
1178 return 1; /* return error */
1179 }
1180
1181 return 0; /* success return 0 */
1182}
1183
1196uint8_t ch9121_get_uart_baud(ch9121_handle_t *handle, ch9121_port_t port, uint32_t *baud)
1197{
1198 uint8_t cmd;
1199 uint8_t buf[4];
1200
1201 if (handle == NULL) /* check handle */
1202 {
1203 return 2; /* return error */
1204 }
1205 if (handle->inited != 1) /* check handle initialization */
1206 {
1207 return 3; /* return error */
1208 }
1209
1210 if (port == CH9121_PORT1) /* port1 */
1211 {
1212 cmd = CH9121_CMD_PORT1_GET_BAUD; /* get port1 baud */
1213 }
1214 else /* port2 */
1215 {
1216 cmd = CH9121_CMD_PORT2_GET_BAUD; /* get port2 baud */
1217 }
1218 if (a_ch9121_write_read(handle, &cmd, 1, buf, 4,
1219 CH9121_UART_PRE_DELAY, 1000) != 0) /* get dest port */
1220 {
1221 return 1; /* return error */
1222 }
1223 *baud = (uint32_t)(((uint32_t)buf[0] << 0) | ((uint32_t)buf[1] << 8) |
1224 ((uint32_t)buf[2] << 16) | ((uint32_t)buf[3] << 24)); /* get baud */
1225
1226 return 0; /* success return 0 */
1227}
1228
1243uint8_t ch9121_set_uart_config(ch9121_handle_t *handle, ch9121_port_t port, uint8_t data_bit, ch9121_parity_t parity, uint8_t stop_bit)
1244{
1245 uint8_t cmd[4];
1246
1247 if (handle == NULL) /* check handle */
1248 {
1249 return 2; /* return error */
1250 }
1251 if (handle->inited != 1) /* check handle initialization */
1252 {
1253 return 3; /* return error */
1254 }
1255
1256 if (port == CH9121_PORT1) /* port1 */
1257 {
1258 cmd[0] = CH9121_CMD_PORT1_SET_CONFIG; /* set port1 config */
1259 }
1260 else /* port2 */
1261 {
1262 cmd[0] = CH9121_CMD_PORT2_SET_CONFIG; /* set port2 config */
1263 }
1264 cmd[1] = stop_bit; /* set stop bit */
1265 cmd[2] = parity; /* set parity */
1266 cmd[3] = data_bit; /* set data bit */
1267 if (a_ch9121_write_check(handle, cmd, 4,
1268 CH9121_UART_PRE_DELAY, 1000) != 0) /* write dest port */
1269 {
1270 return 1; /* return error */
1271 }
1272
1273 return 0; /* success return 0 */
1274}
1275
1290uint8_t ch9121_get_uart_config(ch9121_handle_t *handle, ch9121_port_t port, uint8_t *data_bit, ch9121_parity_t *parity, uint8_t *stop_bit)
1291{
1292 uint8_t cmd;
1293 uint8_t buf[3];
1294
1295 if (handle == NULL) /* check handle */
1296 {
1297 return 2; /* return error */
1298 }
1299 if (handle->inited != 1) /* check handle initialization */
1300 {
1301 return 3; /* return error */
1302 }
1303
1304 if (port == CH9121_PORT1) /* port1 */
1305 {
1306 cmd = CH9121_CMD_PORT1_GET_CONFIG; /* get port1 config */
1307 }
1308 else /* port2 */
1309 {
1310 cmd = CH9121_CMD_PORT2_GET_CONFIG; /* get port2 config */
1311 }
1312 if (a_ch9121_write_read(handle, &cmd, 1, buf, 3,
1313 CH9121_UART_PRE_DELAY, 1000) != 0) /* get dest port */
1314 {
1315 return 1; /* return error */
1316 }
1317 *stop_bit = buf[0]; /* get stop bit */
1318 *parity = (ch9121_parity_t)buf[1]; /* get parity */
1319 *data_bit = buf[2]; /* get data bit */
1320
1321 return 0; /* success return 0 */
1322}
1323
1336uint8_t ch9121_set_uart_timeout(ch9121_handle_t *handle, ch9121_port_t port, uint8_t timeout)
1337{
1338 uint8_t cmd[5];
1339
1340 if (handle == NULL) /* check handle */
1341 {
1342 return 2; /* return error */
1343 }
1344 if (handle->inited != 1) /* check handle initialization */
1345 {
1346 return 3; /* return error */
1347 }
1348
1349 if (port == CH9121_PORT1) /* port1 */
1350 {
1351 cmd[0] = CH9121_CMD_PORT1_SET_TIMEOUT; /* set port1 timeout */
1352 }
1353 else /* port2 */
1354 {
1355 cmd[0] = CH9121_CMD_PORT2_SET_TIMEOUT; /* set port2 timeout */
1356 }
1357 cmd[1] = timeout; /* set timeout */
1358 cmd[2] = 0x00; /* set 0x00 */
1359 cmd[3] = 0x00; /* set 0x00 */
1360 cmd[4] = 0x00; /* set 0x00 */
1361 if (a_ch9121_write_check(handle, cmd, 5,
1362 CH9121_UART_PRE_DELAY, 1000) != 0) /* write uart timeout */
1363 {
1364 return 1; /* return error */
1365 }
1366
1367 return 0; /* success return 0 */
1368}
1369
1382uint8_t ch9121_get_uart_timeout(ch9121_handle_t *handle, ch9121_port_t port, uint8_t *timeout)
1383{
1384 uint8_t cmd;
1385
1386 if (handle == NULL) /* check handle */
1387 {
1388 return 2; /* return error */
1389 }
1390 if (handle->inited != 1) /* check handle initialization */
1391 {
1392 return 3; /* return error */
1393 }
1394
1395 if (port == CH9121_PORT1) /* port1 */
1396 {
1397 cmd = CH9121_CMD_PORT1_GET_TIMEOUT; /* get port1 timeout */
1398 }
1399 else /* port2 */
1400 {
1401 cmd = CH9121_CMD_PORT2_GET_TIMEOUT; /* get port2 timeout */
1402 }
1403 if (a_ch9121_write_read(handle, &cmd, 1, timeout, 1,
1404 CH9121_UART_PRE_DELAY, 1000) != 0) /* get uart timeout */
1405 {
1406 return 1; /* return error */
1407 }
1408
1409 return 0; /* success return 0 */
1410}
1411
1423uint8_t ch9121_uart_timeout_convert_to_register(ch9121_handle_t *handle, uint16_t ms, uint8_t *reg)
1424{
1425 if (handle == NULL) /* check handle */
1426 {
1427 return 2; /* return error */
1428 }
1429 if (handle->inited != 1) /* check handle initialization */
1430 {
1431 return 3; /* return error */
1432 }
1433
1434 *reg = (uint8_t)(ms / 5); /* convert real data to register data */
1435
1436 return 0; /* success return 0 */
1437}
1438
1450uint8_t ch9121_uart_timeout_convert_to_data(ch9121_handle_t *handle, uint8_t reg, uint16_t *ms)
1451{
1452 if (handle == NULL) /* check handle */
1453 {
1454 return 2; /* return error */
1455 }
1456 if (handle->inited != 1) /* check handle initialization */
1457 {
1458 return 3; /* return error */
1459 }
1460
1461 *ms = reg * 5; /* convert raw data to real data */
1462
1463 return 0; /* success return 0 */
1464}
1465
1478uint8_t ch9121_set_source_port_random(ch9121_handle_t *handle, ch9121_port_t port, ch9121_bool_t enable)
1479{
1480 uint8_t cmd[2];
1481
1482 if (handle == NULL) /* check handle */
1483 {
1484 return 2; /* return error */
1485 }
1486 if (handle->inited != 1) /* check handle initialization */
1487 {
1488 return 3; /* return error */
1489 }
1490
1491 if (port == CH9121_PORT1) /* port1 */
1492 {
1493 cmd[0] = CH9121_CMD_PORT1_RANDOM_PORT; /* set port1 random */
1494 }
1495 else /* port2 */
1496 {
1497 cmd[0] = CH9121_CMD_PORT2_RANDOM_PORT ; /* set port2 random */
1498 }
1499 cmd[1] = enable; /* set bool */
1500 if (a_ch9121_write_check(handle, cmd, 2,
1501 CH9121_UART_PRE_DELAY, 1000) != 0) /* write source port random */
1502 {
1503 return 1; /* return error */
1504 }
1505
1506 return 0; /* success return 0 */
1507}
1508
1521uint8_t ch9121_set_uart_buffer_length(ch9121_handle_t *handle, ch9121_port_t port, uint32_t len)
1522{
1523 uint8_t cmd[5];
1524
1525 if (handle == NULL) /* check handle */
1526 {
1527 return 2; /* return error */
1528 }
1529 if (handle->inited != 1) /* check handle initialization */
1530 {
1531 return 3; /* return error */
1532 }
1533
1534 if (port == CH9121_PORT1) /* port1 */
1535 {
1536 cmd[0] = CH9121_CMD_PORT1_LEN; /* set port1 uart buffer */
1537 }
1538 else /* port2 */
1539 {
1540 cmd[0] = CH9121_CMD_PORT2_LEN ; /* set port2 uart buffer */
1541 }
1542 cmd[1] = (len >> 0) & 0xFF; /* set len[0] */
1543 cmd[2] = (len >> 8) & 0xFF; /* set len[8] */
1544 cmd[3] = (len >> 16) & 0xFF; /* set len[16] */
1545 cmd[4] = (len >> 24) & 0xFF; /* set len[24] */
1546 if (a_ch9121_write_check(handle, cmd, 5,
1547 CH9121_UART_PRE_DELAY, 1000) != 0) /* write uart buffer */
1548 {
1549 return 1; /* return error */
1550 }
1551
1552 return 0; /* success return 0 */
1553}
1554
1567uint8_t ch9121_set_uart_flush(ch9121_handle_t *handle, ch9121_port_t port, ch9121_bool_t enable)
1568{
1569 uint8_t cmd[2];
1570
1571 if (handle == NULL) /* check handle */
1572 {
1573 return 2; /* return error */
1574 }
1575 if (handle->inited != 1) /* check handle initialization */
1576 {
1577 return 3; /* return error */
1578 }
1579
1580 if (port == CH9121_PORT1) /* port1 */
1581 {
1582 cmd[0] = CH9121_CMD_PORT1_FLUSH; /* set port1 flush */
1583 }
1584 else /* port2 */
1585 {
1586 cmd[0] = CH9121_CMD_PORT2_FLUSH ; /* set port2 flush */
1587 }
1588 cmd[1] = enable; /* set bool */
1589 if (a_ch9121_write_check(handle, cmd, 2,
1590 CH9121_UART_PRE_DELAY, 1000) != 0) /* write flush */
1591 {
1592 return 1; /* return error */
1593 }
1594
1595 return 0; /* success return 0 */
1596}
1597
1609uint8_t ch9121_set_port2(ch9121_handle_t *handle, ch9121_bool_t enable)
1610{
1611 uint8_t cmd[2];
1612
1613 if (handle == NULL) /* check handle */
1614 {
1615 return 2; /* return error */
1616 }
1617 if (handle->inited != 1) /* check handle initialization */
1618 {
1619 return 3; /* return error */
1620 }
1621
1622 cmd[0] = CH9121_CMD_PORT2_ENABLE; /* enable port2 */
1623 cmd[1] = enable; /* set bool */
1624 if (a_ch9121_write_check(handle, cmd, 2,
1625 CH9121_UART_PRE_DELAY, 1000) != 0) /* write enable */
1626 {
1627 return 1; /* return error */
1628 }
1629
1630 return 0; /* success return 0 */
1631}
1632
1644uint8_t ch9121_set_disconnect_with_no_rj45(ch9121_handle_t *handle, ch9121_bool_t enable)
1645{
1646 uint8_t cmd[2];
1647
1648 if (handle == NULL) /* check handle */
1649 {
1650 return 2; /* return error */
1651 }
1652 if (handle->inited != 1) /* check handle initialization */
1653 {
1654 return 3; /* return error */
1655 }
1656
1657 cmd[0] = CH9121_CMD_DISCONNECT; /* set disconnect */
1658 cmd[1] = enable; /* set bool */
1659 if (a_ch9121_write_check(handle, cmd, 2,
1660 CH9121_UART_PRE_DELAY, 1000) != 0) /* write disconnect */
1661 {
1662 return 1; /* return error */
1663 }
1664
1665 return 0; /* success return 0 */
1666}
1667
1679uint8_t ch9121_set_domain(ch9121_handle_t *handle, char *domain)
1680{
1681 uint8_t cmd[29];
1682
1683 if (handle == NULL) /* check handle */
1684 {
1685 return 2; /* return error */
1686 }
1687 if (handle->inited != 1) /* check handle initialization */
1688 {
1689 return 3; /* return error */
1690 }
1691 if (strlen(domain) > 28) /* check domain */
1692 {
1693 handle->debug_print("ch9121: domain > 28.\n"); /* domain > 28 */
1694
1695 return 4; /* return error */
1696 }
1697
1698 cmd[0] = CH9121_CMD_PORT1_DOMAIN ; /* set domain */
1699 memcpy(&cmd[1], (uint8_t *)domain, strlen(domain));
1700 if (a_ch9121_write_check(handle, cmd,
1701 (uint16_t)(strlen(domain) + 1),
1702 CH9121_UART_PRE_DELAY, 1000) != 0) /* write domain */
1703 {
1704 return 1; /* return error */
1705 }
1706
1707 return 0; /* success return 0 */
1708}
1709
1723uint8_t ch9121_init(ch9121_handle_t *handle)
1724{
1725 if (handle == NULL) /* check handle */
1726 {
1727 return 2; /* return error */
1728 }
1729 if (handle->debug_print == NULL) /* check debug_print */
1730 {
1731 return 3; /* return error */
1732 }
1733 if (handle->uart_init == NULL) /* check uart_init */
1734 {
1735 handle->debug_print("ch9121: uart_init is null.\n"); /* uart_init is null */
1736
1737 return 3; /* return error */
1738 }
1739 if (handle->uart_deinit == NULL) /* check uart_deinit */
1740 {
1741 handle->debug_print("ch9121: uart_deinit is null.\n"); /* uart_deinit is null */
1742
1743 return 3; /* return error */
1744 }
1745 if (handle->uart_read == NULL) /* check uart_read */
1746 {
1747 handle->debug_print("ch9121: uart_read is null.\n"); /* uart_read is null */
1748
1749 return 3; /* return error */
1750 }
1751 if (handle->uart_write == NULL) /* check uart_write */
1752 {
1753 handle->debug_print("ch9121: uart_write is null.\n"); /* uart_write is null */
1754
1755 return 3; /* return error */
1756 }
1757 if (handle->uart_flush == NULL) /* check uart_flush */
1758 {
1759 handle->debug_print("ch9121: uart_flush is null.\n"); /* uart_flush is null */
1760
1761 return 3; /* return error */
1762 }
1763 if (handle->delay_ms == NULL) /* check delay_ms */
1764 {
1765 handle->debug_print("ch9121: delay_ms is null.\n"); /* delay_ms is null */
1766
1767 return 3; /* return error */
1768 }
1769 if (handle->reset_gpio_init == NULL) /* check reset_gpio_init */
1770 {
1771 handle->debug_print("ch9121: reset_gpio_init is null.\n"); /* reset_gpio_init is null */
1772
1773 return 3; /* return error */
1774 }
1775 if (handle->reset_gpio_deinit == NULL) /* check reset_gpio_deinit */
1776 {
1777 handle->debug_print("ch9121: reset_gpio_deinit is null.\n"); /* reset_gpio_deinit is null */
1778
1779 return 3; /* return error */
1780 }
1781 if (handle->reset_gpio_write == NULL) /* check reset_gpio_write */
1782 {
1783 handle->debug_print("ch9121: reset_gpio_write is null.\n"); /* reset_gpio_write is null */
1784
1785 return 3; /* return error */
1786 }
1787 if (handle->cfg_gpio_init == NULL) /* check cfg_gpio_init */
1788 {
1789 handle->debug_print("ch9121: cfg_gpio_init is null.\n"); /* cfg_gpio_init is null */
1790
1791 return 3; /* return error */
1792 }
1793 if (handle->cfg_gpio_deinit == NULL) /* check cfg_gpio_deinit */
1794 {
1795 handle->debug_print("ch9121: cfg_gpio_deinit is null.\n"); /* cfg_gpio_deinit is null */
1796
1797 return 3; /* return error */
1798 }
1799 if (handle->cfg_gpio_write == NULL) /* check cfg_gpio_write */
1800 {
1801 handle->debug_print("ch9121: cfg_gpio_write is null.\n"); /* cfg_gpio_write is null */
1802
1803 return 3; /* return error */
1804 }
1805
1806 if (handle->uart_init() != 0) /* uart init */
1807 {
1808 handle->debug_print("ch9121: uart init failed.\n"); /* uart init failed */
1809
1810 return 1; /* return error */
1811 }
1812 if (handle->reset_gpio_init() != 0) /* reset gpio init */
1813 {
1814 handle->debug_print("ch9121: reset gpio init failed.\n"); /* reset gpio init failed */
1815 (void)handle->uart_deinit(); /* uart deinit */
1816
1817 return 4; /* return error */
1818 }
1819 if (handle->cfg_gpio_init() != 0) /* cfg gpio init */
1820 {
1821 handle->debug_print("ch9121: cfg gpio init failed.\n"); /* cfg gpio init failed */
1822 (void)handle->uart_deinit(); /* uart deinit */
1823 (void)handle->reset_gpio_deinit(); /* reset gpio deinit */
1824
1825 return 5; /* return error */
1826 }
1827 if (handle->reset_gpio_write(0) != 0) /* set low */
1828 {
1829 handle->debug_print("ch9121: cfg gpio write failed.\n"); /* cfg gpio write failed */
1830 (void)handle->uart_deinit(); /* uart deinit */
1831 (void)handle->reset_gpio_deinit(); /* reset gpio deinit */
1832 (void)handle->cfg_gpio_deinit(); /* cfg gpio deinit */
1833
1834 return 6; /* return error */
1835 }
1836 handle->delay_ms(10); /* delay 10ms */
1837 if (handle->reset_gpio_write(1) != 0) /* set high */
1838 {
1839 handle->debug_print("ch9121: cfg gpio write failed.\n"); /* cfg gpio write failed */
1840 (void)handle->uart_deinit(); /* uart deinit */
1841 (void)handle->reset_gpio_deinit(); /* reset gpio deinit */
1842 (void)handle->cfg_gpio_deinit(); /* cfg gpio deinit */
1843
1844 return 6; /* return error */
1845 }
1846 handle->delay_ms(1000); /* delay 1000ms */
1847 handle->inited = 1; /* flag finish initialization */
1848
1849 return 0; /* success return 0 */
1850}
1851
1865uint8_t ch9121_deinit(ch9121_handle_t *handle)
1866{
1867 uint8_t cmd;
1868
1869 if (handle == NULL) /* check handle */
1870 {
1871 return 2; /* return error */
1872 }
1873 if (handle->inited != 1) /* check handle initialization */
1874 {
1875 return 3; /* return error */
1876 }
1877
1878 cmd = CH9121_CMD_RESET; /* set reset */
1879 if (a_ch9121_write_check(handle, &cmd, 1,
1880 CH9121_UART_PRE_DELAY, 1000) != 0) /* reset */
1881 {
1882 return 4; /* return error */
1883 }
1884 handle->delay_ms(10); /* delay 10ms */
1885 if (handle->uart_deinit() != 0) /* uart deinit */
1886 {
1887 handle->debug_print("ch9121: uart deinit failed.\n"); /* uart deinit failed */
1888
1889 return 1; /* return error */
1890 }
1891 if (handle->reset_gpio_deinit() != 0) /* reset gpio deinit */
1892 {
1893 handle->debug_print("ch9121: reset gpio deinit failed.\n"); /* reset gpio deinit failed */
1894
1895 return 5; /* return error */
1896 }
1897 if (handle->cfg_gpio_deinit() != 0) /* cfg gpio deinit */
1898 {
1899 handle->debug_print("ch9121: cfg gpio deinit failed.\n"); /* cfg gpio deinit failed */
1900
1901 return 6; /* return error */
1902 }
1903
1904 return 0; /* success return 0 */
1905}
1906
1919uint8_t ch9121_write(ch9121_handle_t *handle, uint8_t *buf, uint16_t len)
1920{
1921 if (handle == NULL) /* check handle */
1922 {
1923 return 2; /* return error */
1924 }
1925 if (handle->inited != 1) /* check handle initialization */
1926 {
1927 return 3; /* return error */
1928 }
1929
1930 if (handle->cfg_gpio_write(1) != 0) /* cfg gpio write */
1931 {
1932 handle->debug_print("ch9121: cfg gpio write failed.\n"); /* cfg gpio write failed */
1933
1934 return 1; /* return error */
1935 }
1936 if (handle->uart_write(buf, len) != 0) /* uart write */
1937 {
1938 handle->debug_print("ch9121:uart write failed.\n"); /* uart write failed */
1939
1940 return 1; /* return error */
1941 }
1942
1943 return 0; /* success return 0 */
1944}
1945
1958uint8_t ch9121_read(ch9121_handle_t *handle, uint8_t *buf, uint16_t *len)
1959{
1960 uint16_t l;
1961
1962 if (handle == NULL) /* check handle */
1963 {
1964 return 2; /* return error */
1965 }
1966 if (handle->inited != 1) /* check handle initialization */
1967 {
1968 return 3; /* return error */
1969 }
1970
1971 if (handle->cfg_gpio_write(1) != 0) /* cfg gpio write */
1972 {
1973 handle->debug_print("ch9121: cfg gpio write failed.\n"); /* cfg gpio write failed */
1974
1975 return 1; /* return error */
1976 }
1977 l = handle->uart_read(buf, *len); /* uart read */
1978 *len = l; /* set data */
1979
1980 return 0; /* success return 0 */
1981}
1982
1999uint8_t ch9121_set_command(ch9121_handle_t *handle,
2000 uint8_t *param, uint16_t len,
2001 uint8_t *out, uint16_t out_len,
2002 uint16_t pre_delay, uint16_t timeout)
2003{
2004 if (handle == NULL) /* check handle */
2005 {
2006 return 2; /* return error */
2007 }
2008 if (handle->inited != 1) /* check handle initialization */
2009 {
2010 return 3; /* return error */
2011 }
2012
2013 if (a_ch9121_write_read(handle, param, len,
2014 out, out_len,
2015 pre_delay, timeout) != 0) /* set command */
2016 {
2017 return 1; /* return error */
2018 }
2019
2020 return 0; /* success return 0 */
2021}
2022
2031uint8_t ch9121_info(ch9121_info_t *info)
2032{
2033 if (info == NULL) /* check handle */
2034 {
2035 return 2; /* return error */
2036 }
2037
2038 memset(info, 0, sizeof(ch9121_info_t)); /* initialize ch9121 info structure */
2039 strncpy(info->chip_name, CHIP_NAME, 32); /* copy chip name */
2040 strncpy(info->manufacturer_name, MANUFACTURER_NAME, 32); /* copy manufacturer name */
2041 strncpy(info->interface, "UART", 8); /* copy interface name */
2042 info->supply_voltage_min_v = SUPPLY_VOLTAGE_MIN; /* set minimal supply voltage */
2043 info->supply_voltage_max_v = SUPPLY_VOLTAGE_MAX; /* set maximum supply voltage */
2044 info->max_current_ma = MAX_CURRENT; /* set maximum current */
2045 info->temperature_max = TEMPERATURE_MAX; /* set minimal temperature */
2046 info->temperature_min = TEMPERATURE_MIN; /* set maximum temperature */
2047 info->driver_version = DRIVER_VERSION; /* set driver version */
2048
2049 return 0; /* success return 0 */
2050}
CH9121_CMD_PORT2_SET_DST_PORT
#define CH9121_CMD_PORT2_SET_DST_PORT
Definition driver_ch9121.c:91
CH9121_CMD_GET_GATEWAY
#define CH9121_CMD_GET_GATEWAY
Definition driver_ch9121.c:66
CH9121_CMD_PORT2_GET_MODE
#define CH9121_CMD_PORT2_GET_MODE
Definition driver_ch9121.c:95
CH9121_CMD_PORT1_SET_DST_PORT
#define CH9121_CMD_PORT1_SET_DST_PORT
Definition driver_ch9121.c:76
CH9121_CMD_PORT1_SET_TIMEOUT
#define CH9121_CMD_PORT1_SET_TIMEOUT
Definition driver_ch9121.c:79
CH9121_CMD_EXIT
#define CH9121_CMD_EXIT
Definition driver_ch9121.c:58
MAX_CURRENT
#define MAX_CURRENT
Definition driver_ch9121.c:46
CH9121_CMD_PORT1_GET_TIMEOUT
#define CH9121_CMD_PORT1_GET_TIMEOUT
Definition driver_ch9121.c:86
CH9121_CMD_PORT1_GET_MODE
#define CH9121_CMD_PORT1_GET_MODE
Definition driver_ch9121.c:80
CH9121_CMD_GET_NETMASK
#define CH9121_CMD_GET_NETMASK
Definition driver_ch9121.c:65
CH9121_CMD_PORT1_RANDOM_PORT
#define CH9121_CMD_PORT1_RANDOM_PORT
chip port extern command definition
Definition driver_ch9121.c:106
CH9121_CMD_PORT2_GET_CONFIG
#define CH9121_CMD_PORT2_GET_CONFIG
Definition driver_ch9121.c:100
CH9121_CMD_PORT2_RANDOM_PORT
#define CH9121_CMD_PORT2_RANDOM_PORT
Definition driver_ch9121.c:111
CH9121_CMD_MAC
#define CH9121_CMD_MAC
Definition driver_ch9121.c:60
CH9121_CMD_PORT1_SET_BAUD
#define CH9121_CMD_PORT1_SET_BAUD
Definition driver_ch9121.c:77
CH9121_CMD_PORT1_GET_PORT
#define CH9121_CMD_PORT1_GET_PORT
Definition driver_ch9121.c:81
CH9121_CMD_PORT1_GET_CONFIG
#define CH9121_CMD_PORT1_GET_CONFIG
Definition driver_ch9121.c:85
CH9121_CMD_PORT2_SET_BAUD
#define CH9121_CMD_PORT2_SET_BAUD
Definition driver_ch9121.c:92
CH9121_CMD_DHCP
#define CH9121_CMD_DHCP
Definition driver_ch9121.c:59
CH9121_CMD_PORT1_LEN
#define CH9121_CMD_PORT1_LEN
Definition driver_ch9121.c:107
CH9121_CMD_PORT2_GET_STATUS
#define CH9121_CMD_PORT2_GET_STATUS
Definition driver_ch9121.c:87
CH9121_CMD_PORT2_SET_CONFIG
#define CH9121_CMD_PORT2_SET_CONFIG
Definition driver_ch9121.c:93
CH9121_CMD_CHIP_VERSION
#define CH9121_CMD_CHIP_VERSION
chip basic command definition
Definition driver_ch9121.c:54
CH9121_CMD_PORT2_SET_PORT
#define CH9121_CMD_PORT2_SET_PORT
Definition driver_ch9121.c:89
CH9121_CMD_RESET
#define CH9121_CMD_RESET
Definition driver_ch9121.c:55
CH9121_CMD_PORT1_SET_MODE
#define CH9121_CMD_PORT1_SET_MODE
Definition driver_ch9121.c:73
SUPPLY_VOLTAGE_MAX
#define SUPPLY_VOLTAGE_MAX
Definition driver_ch9121.c:45
CH9121_CMD_PORT2_SET_DST_IP
#define CH9121_CMD_PORT2_SET_DST_IP
Definition driver_ch9121.c:90
CH9121_CMD_PORT2_GET_DST_IP
#define CH9121_CMD_PORT2_GET_DST_IP
Definition driver_ch9121.c:97
CH9121_CMD_PORT1_GET_STATUS
#define CH9121_CMD_PORT1_GET_STATUS
chip port command definition
Definition driver_ch9121.c:72
CH9121_CMD_SAVE_TO_EEPROM
#define CH9121_CMD_SAVE_TO_EEPROM
Definition driver_ch9121.c:56
CH9121_CMD_SET_NETMASK
#define CH9121_CMD_SET_NETMASK
Definition driver_ch9121.c:62
CH9121_CMD_PORT2_SET_MODE
#define CH9121_CMD_PORT2_SET_MODE
Definition driver_ch9121.c:88
CH9121_CMD_GET_IP
#define CH9121_CMD_GET_IP
Definition driver_ch9121.c:64
CH9121_CMD_PORT1_FLUSH
#define CH9121_CMD_PORT1_FLUSH
Definition driver_ch9121.c:108
CH9121_CMD_PORT2_GET_DST_PORT
#define CH9121_CMD_PORT2_GET_DST_PORT
Definition driver_ch9121.c:98
CH9121_CMD_SET_IP
#define CH9121_CMD_SET_IP
Definition driver_ch9121.c:61
CH9121_CMD_PORT2_ENABLE
#define CH9121_CMD_PORT2_ENABLE
Definition driver_ch9121.c:110
CH9121_CMD_SET_GATEWAY
#define CH9121_CMD_SET_GATEWAY
Definition driver_ch9121.c:63
TEMPERATURE_MAX
#define TEMPERATURE_MAX
Definition driver_ch9121.c:48
CH9121_CMD_PORT1_GET_DST_IP
#define CH9121_CMD_PORT1_GET_DST_IP
Definition driver_ch9121.c:82
CH9121_CMD_PORT2_GET_BAUD
#define CH9121_CMD_PORT2_GET_BAUD
Definition driver_ch9121.c:99
MANUFACTURER_NAME
#define MANUFACTURER_NAME
Definition driver_ch9121.c:43
TEMPERATURE_MIN
#define TEMPERATURE_MIN
Definition driver_ch9121.c:47
SUPPLY_VOLTAGE_MIN
#define SUPPLY_VOLTAGE_MIN
Definition driver_ch9121.c:44
CH9121_CMD_PORT1_SET_DST_IP
#define CH9121_CMD_PORT1_SET_DST_IP
Definition driver_ch9121.c:75
CH9121_CMD_PORT2_GET_TIMEOUT
#define CH9121_CMD_PORT2_GET_TIMEOUT
Definition driver_ch9121.c:101
CH9121_CMD_RUN_AND_RESET
#define CH9121_CMD_RUN_AND_RESET
Definition driver_ch9121.c:57
CH9121_CMD_PORT1_SET_PORT
#define CH9121_CMD_PORT1_SET_PORT
Definition driver_ch9121.c:74
CHIP_NAME
#define CHIP_NAME
chip information definition
Definition driver_ch9121.c:42
CH9121_CMD_PORT1_SET_CONFIG
#define CH9121_CMD_PORT1_SET_CONFIG
Definition driver_ch9121.c:78
CH9121_CMD_PORT2_LEN
#define CH9121_CMD_PORT2_LEN
Definition driver_ch9121.c:112
CH9121_CMD_PORT1_DOMAIN
#define CH9121_CMD_PORT1_DOMAIN
Definition driver_ch9121.c:109
DRIVER_VERSION
#define DRIVER_VERSION
Definition driver_ch9121.c:49
CH9121_CMD_PORT2_FLUSH
#define CH9121_CMD_PORT2_FLUSH
Definition driver_ch9121.c:113
CH9121_CMD_PORT1_GET_BAUD
#define CH9121_CMD_PORT1_GET_BAUD
Definition driver_ch9121.c:84
CH9121_CMD_DISCONNECT
#define CH9121_CMD_DISCONNECT
Definition driver_ch9121.c:67
CH9121_CMD_PORT2_SET_TIMEOUT
#define CH9121_CMD_PORT2_SET_TIMEOUT
Definition driver_ch9121.c:94
CH9121_CMD_PORT2_GET_PORT
#define CH9121_CMD_PORT2_GET_PORT
Definition driver_ch9121.c:96
CH9121_CMD_PORT1_GET_DST_PORT
#define CH9121_CMD_PORT1_GET_DST_PORT
Definition driver_ch9121.c:83
driver_ch9121.h
driver ch9121 header file
ch9121_parity_t
ch9121_parity_t
ch9121 parity enumeration definition
Definition driver_ch9121.h:108
ch9121_bool_t
ch9121_bool_t
ch9121 bool enumeration definition
Definition driver_ch9121.h:79
ch9121_get_ip
uint8_t ch9121_get_ip(ch9121_handle_t *handle, uint8_t ip[4])
get ip address
Definition driver_ch9121.c:707
ch9121_init
uint8_t ch9121_init(ch9121_handle_t *handle)
initialize the chip
Definition driver_ch9121.c:1723
ch9121_mode_t
ch9121_mode_t
ch9121 mode enumeration definition
Definition driver_ch9121.h:97
ch9121_set_uart_baud
uint8_t ch9121_set_uart_baud(ch9121_handle_t *handle, ch9121_port_t port, uint32_t baud)
set uart baud
Definition driver_ch9121.c:1150
ch9121_set_dhcp
uint8_t ch9121_set_dhcp(ch9121_handle_t *handle, ch9121_bool_t enable)
enable or disable dhcp
Definition driver_ch9121.c:469
ch9121_info
uint8_t ch9121_info(ch9121_info_t *info)
get chip's information
Definition driver_ch9121.c:2031
ch9121_set_ip
uint8_t ch9121_set_ip(ch9121_handle_t *handle, uint8_t ip[4])
set ip address
Definition driver_ch9121.c:669
ch9121_get_gateway
uint8_t ch9121_get_gateway(ch9121_handle_t *handle, uint8_t ip[4])
get gateway
Definition driver_ch9121.c:851
ch9121_config_and_reset
uint8_t ch9121_config_and_reset(ch9121_handle_t *handle)
config and reset the chip
Definition driver_ch9121.c:401
ch9121_set_disconnect_with_no_rj45
uint8_t ch9121_set_disconnect_with_no_rj45(ch9121_handle_t *handle, ch9121_bool_t enable)
enable or disable disconnect with no rj45
Definition driver_ch9121.c:1644
ch9121_set_uart_flush
uint8_t ch9121_set_uart_flush(ch9121_handle_t *handle, ch9121_port_t port, ch9121_bool_t enable)
enable or disable uart auto flush
Definition driver_ch9121.c:1567
ch9121_deinit
uint8_t ch9121_deinit(ch9121_handle_t *handle)
close the chip
Definition driver_ch9121.c:1865
ch9121_read
uint8_t ch9121_read(ch9121_handle_t *handle, uint8_t *buf, uint16_t *len)
read data
Definition driver_ch9121.c:1958
ch9121_reset
uint8_t ch9121_reset(ch9121_handle_t *handle)
reset the chip
Definition driver_ch9121.c:334
ch9121_set_source_port_random
uint8_t ch9121_set_source_port_random(ch9121_handle_t *handle, ch9121_port_t port, ch9121_bool_t enable)
enable or disable random source port number
Definition driver_ch9121.c:1478
ch9121_info_t
struct ch9121_info_s ch9121_info_t
ch9121 information structure definition
ch9121_set_mode
uint8_t ch9121_set_mode(ch9121_handle_t *handle, ch9121_port_t port, ch9121_mode_t mode)
set mode
Definition driver_ch9121.c:583
ch9121_get_uart_timeout
uint8_t ch9121_get_uart_timeout(ch9121_handle_t *handle, ch9121_port_t port, uint8_t *timeout)
get uart timeout
Definition driver_ch9121.c:1382
ch9121_uart_timeout_convert_to_data
uint8_t ch9121_uart_timeout_convert_to_data(ch9121_handle_t *handle, uint8_t reg, uint16_t *ms)
convert the register raw data to the offset
Definition driver_ch9121.c:1450
ch9121_handle_t
struct ch9121_handle_s ch9121_handle_t
ch9121 handle structure definition
ch9121_set_dest_ip
uint8_t ch9121_set_dest_ip(ch9121_handle_t *handle, ch9121_port_t port, uint8_t ip[4])
set dest ip
Definition driver_ch9121.c:974
ch9121_get_dest_port
uint8_t ch9121_get_dest_port(ch9121_handle_t *handle, ch9121_port_t port, uint16_t *num)
get dest port
Definition driver_ch9121.c:1106
ch9121_save_to_eeprom
uint8_t ch9121_save_to_eeprom(ch9121_handle_t *handle)
save to eeprom
Definition driver_ch9121.c:368
ch9121_get_subnet_mask
uint8_t ch9121_get_subnet_mask(ch9121_handle_t *handle, uint8_t mask[4])
get subnet mask
Definition driver_ch9121.c:779
ch9121_set_uart_config
uint8_t ch9121_set_uart_config(ch9121_handle_t *handle, ch9121_port_t port, uint8_t data_bit, ch9121_parity_t parity, uint8_t stop_bit)
set uart config
Definition driver_ch9121.c:1243
ch9121_status_t
ch9121_status_t
ch9121 status enumeration definition
Definition driver_ch9121.h:88
ch9121_get_dest_ip
uint8_t ch9121_get_dest_ip(ch9121_handle_t *handle, ch9121_port_t port, uint8_t ip[4])
get dest ip
Definition driver_ch9121.c:1020
ch9121_get_uart_config
uint8_t ch9121_get_uart_config(ch9121_handle_t *handle, ch9121_port_t port, uint8_t *data_bit, ch9121_parity_t *parity, uint8_t *stop_bit)
get uart config
Definition driver_ch9121.c:1290
ch9121_port_t
ch9121_port_t
ch9121 port enumeration definition
Definition driver_ch9121.h:70
ch9121_uart_timeout_convert_to_register
uint8_t ch9121_uart_timeout_convert_to_register(ch9121_handle_t *handle, uint16_t ms, uint8_t *reg)
convert the uart timeout to the register raw data
Definition driver_ch9121.c:1423
ch9121_set_subnet_mask
uint8_t ch9121_set_subnet_mask(ch9121_handle_t *handle, uint8_t mask[4])
set subnet mask
Definition driver_ch9121.c:741
ch9121_set_domain
uint8_t ch9121_set_domain(ch9121_handle_t *handle, char *domain)
set chip domain
Definition driver_ch9121.c:1679
ch9121_get_uart_baud
uint8_t ch9121_get_uart_baud(ch9121_handle_t *handle, ch9121_port_t port, uint32_t *baud)
get uart baud
Definition driver_ch9121.c:1196
ch9121_set_uart_timeout
uint8_t ch9121_set_uart_timeout(ch9121_handle_t *handle, ch9121_port_t port, uint8_t timeout)
set uart timeout
Definition driver_ch9121.c:1336
ch9121_set_gateway
uint8_t ch9121_set_gateway(ch9121_handle_t *handle, uint8_t ip[4])
set gateway
Definition driver_ch9121.c:813
ch9121_set_source_port
uint8_t ch9121_set_source_port(ch9121_handle_t *handle, ch9121_port_t port, uint16_t num)
set source port
Definition driver_ch9121.c:886
ch9121_set_port2
uint8_t ch9121_set_port2(ch9121_handle_t *handle, ch9121_bool_t enable)
enable or disable uart port2
Definition driver_ch9121.c:1609
ch9121_get_version
uint8_t ch9121_get_version(ch9121_handle_t *handle, uint8_t *version)
get version
Definition driver_ch9121.c:301
ch9121_set_dest_port
uint8_t ch9121_set_dest_port(ch9121_handle_t *handle, ch9121_port_t port, uint16_t num)
set dest port
Definition driver_ch9121.c:1062
ch9121_exit
uint8_t ch9121_exit(ch9121_handle_t *handle)
exit
Definition driver_ch9121.c:435
ch9121_get_mode
uint8_t ch9121_get_mode(ch9121_handle_t *handle, ch9121_port_t port, ch9121_mode_t *mode)
get mode
Definition driver_ch9121.c:626
ch9121_get_status
uint8_t ch9121_get_status(ch9121_handle_t *handle, ch9121_port_t port, ch9121_status_t *status)
get status
Definition driver_ch9121.c:539
ch9121_get_source_port
uint8_t ch9121_get_source_port(ch9121_handle_t *handle, ch9121_port_t port, uint16_t *num)
get source port
Definition driver_ch9121.c:930
ch9121_set_uart_buffer_length
uint8_t ch9121_set_uart_buffer_length(ch9121_handle_t *handle, ch9121_port_t port, uint32_t len)
set uart buffer length
Definition driver_ch9121.c:1521
ch9121_get_mac
uint8_t ch9121_get_mac(ch9121_handle_t *handle, uint8_t mac[6])
get chip mac
Definition driver_ch9121.c:504
CH9121_UART_PRE_DELAY
#define CH9121_UART_PRE_DELAY
ch9121 uart pre delay definition
Definition driver_ch9121.h:63
ch9121_write
uint8_t ch9121_write(ch9121_handle_t *handle, uint8_t *buf, uint16_t len)
write data
Definition driver_ch9121.c:1919
CH9121_PORT1
@ CH9121_PORT1
Definition driver_ch9121.h:71
ch9121_set_command
uint8_t ch9121_set_command(ch9121_handle_t *handle, uint8_t *param, uint16_t len, uint8_t *out, uint16_t out_len, uint16_t pre_delay, uint16_t timeout)
set command
Definition driver_ch9121.c:1999
ch9121_handle_s::uart_flush
uint8_t(* uart_flush)(void)
Definition driver_ch9121.h:124
ch9121_handle_s::inited
uint8_t inited
Definition driver_ch9121.h:134
ch9121_handle_s::cfg_gpio_write
uint8_t(* cfg_gpio_write)(uint8_t data)
Definition driver_ch9121.h:131
ch9121_handle_s::uart_write
uint8_t(* uart_write)(uint8_t *buf, uint16_t len)
Definition driver_ch9121.h:125
ch9121_handle_s::delay_ms
void(* delay_ms)(uint32_t ms)
Definition driver_ch9121.h:132
ch9121_handle_s::cfg_gpio_init
uint8_t(* cfg_gpio_init)(void)
Definition driver_ch9121.h:129
ch9121_handle_s::uart_deinit
uint8_t(* uart_deinit)(void)
Definition driver_ch9121.h:122
ch9121_handle_s::reset_gpio_deinit
uint8_t(* reset_gpio_deinit)(void)
Definition driver_ch9121.h:127
ch9121_handle_s::debug_print
void(* debug_print)(const char *const fmt,...)
Definition driver_ch9121.h:133
ch9121_handle_s::uart_read
uint16_t(* uart_read)(uint8_t *buf, uint16_t len)
Definition driver_ch9121.h:123
ch9121_handle_s::reset_gpio_init
uint8_t(* reset_gpio_init)(void)
Definition driver_ch9121.h:126
ch9121_handle_s::buf
uint8_t buf[128]
Definition driver_ch9121.h:135
ch9121_handle_s::uart_init
uint8_t(* uart_init)(void)
Definition driver_ch9121.h:121
ch9121_handle_s::reset_gpio_write
uint8_t(* reset_gpio_write)(uint8_t data)
Definition driver_ch9121.h:128
ch9121_handle_s::cfg_gpio_deinit
uint8_t(* cfg_gpio_deinit)(void)
Definition driver_ch9121.h:130
ch9121_info_s::temperature_max
float temperature_max
Definition driver_ch9121.h:150
ch9121_info_s::supply_voltage_max_v
float supply_voltage_max_v
Definition driver_ch9121.h:147
ch9121_info_s::driver_version
uint32_t driver_version
Definition driver_ch9121.h:151
ch9121_info_s::temperature_min
float temperature_min
Definition driver_ch9121.h:149
ch9121_info_s::max_current_ma
float max_current_ma
Definition driver_ch9121.h:148
ch9121_info_s::manufacturer_name
char manufacturer_name[32]
Definition driver_ch9121.h:144
ch9121_info_s::supply_voltage_min_v
float supply_voltage_min_v
Definition driver_ch9121.h:146
ch9121_info_s::interface
char interface[8]
Definition driver_ch9121.h:145
ch9121_info_s::chip_name
char chip_name[32]
Definition driver_ch9121.h:143