LibDriver CH9121
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driver_ch9121.c
Go to the documentation of this file.
1
36
37#include "driver_ch9121.h"
38
42#define CHIP_NAME "WCH CH9121"
43#define MANUFACTURER_NAME "WCH"
44#define SUPPLY_VOLTAGE_MIN 2.7f
45#define SUPPLY_VOLTAGE_MAX 3.6f
46#define MAX_CURRENT 190.0f
47#define TEMPERATURE_MIN -40.0f
48#define TEMPERATURE_MAX 85.0f
49#define DRIVER_VERSION 1000
50
54#define CH9121_CMD_CHIP_VERSION 0x01
55#define CH9121_CMD_RESET 0x02
56#define CH9121_CMD_SAVE_TO_EEPROM 0x0D
57#define CH9121_CMD_RUN_AND_RESET 0x0E
58#define CH9121_CMD_EXIT 0x5E
59#define CH9121_CMD_DHCP 0x33
60#define CH9121_CMD_MAC 0x81
61#define CH9121_CMD_SET_IP 0x11
62#define CH9121_CMD_SET_NETMASK 0x12
63#define CH9121_CMD_SET_GATEWAY 0x13
64#define CH9121_CMD_GET_IP 0x61
65#define CH9121_CMD_GET_NETMASK 0x62
66#define CH9121_CMD_GET_GATEWAY 0x63
67#define CH9121_CMD_DISCONNECT 0x24
68
72#define CH9121_CMD_PORT1_GET_STATUS 0x03
73#define CH9121_CMD_PORT1_SET_MODE 0x10
74#define CH9121_CMD_PORT1_SET_PORT 0x14
75#define CH9121_CMD_PORT1_SET_DST_IP 0x15
76#define CH9121_CMD_PORT1_SET_DST_PORT 0x16
77#define CH9121_CMD_PORT1_SET_BAUD 0x21
78#define CH9121_CMD_PORT1_SET_CONFIG 0x22
79#define CH9121_CMD_PORT1_SET_TIMEOUT 0x23
80#define CH9121_CMD_PORT1_GET_MODE 0x60
81#define CH9121_CMD_PORT1_GET_PORT 0x64
82#define CH9121_CMD_PORT1_GET_DST_IP 0x65
83#define CH9121_CMD_PORT1_GET_DST_PORT 0x66
84#define CH9121_CMD_PORT1_GET_BAUD 0x71
85#define CH9121_CMD_PORT1_GET_CONFIG 0x72
86#define CH9121_CMD_PORT1_GET_TIMEOUT 0x73
87#define CH9121_CMD_PORT2_GET_STATUS 0x04
88#define CH9121_CMD_PORT2_SET_MODE 0x40
89#define CH9121_CMD_PORT2_SET_PORT 0x41
90#define CH9121_CMD_PORT2_SET_DST_IP 0x42
91#define CH9121_CMD_PORT2_SET_DST_PORT 0x43
92#define CH9121_CMD_PORT2_SET_BAUD 0x44
93#define CH9121_CMD_PORT2_SET_CONFIG 0x45
94#define CH9121_CMD_PORT2_SET_TIMEOUT 0x46
95#define CH9121_CMD_PORT2_GET_MODE 0x90
96#define CH9121_CMD_PORT2_GET_PORT 0x91
97#define CH9121_CMD_PORT2_GET_DST_IP 0x92
98#define CH9121_CMD_PORT2_GET_DST_PORT 0x93
99#define CH9121_CMD_PORT2_GET_BAUD 0x94
100#define CH9121_CMD_PORT2_GET_CONFIG 0x95
101#define CH9121_CMD_PORT2_GET_TIMEOUT 0x96
102
106#define CH9121_CMD_PORT1_RANDOM_PORT 0x17
107#define CH9121_CMD_PORT1_LEN 0x25
108#define CH9121_CMD_PORT1_FLUSH 0x26
109#define CH9121_CMD_PORT1_DOMAIN 0x34
110#define CH9121_CMD_PORT2_ENABLE 0x39
111#define CH9121_CMD_PORT2_RANDOM_PORT 0x47
112#define CH9121_CMD_PORT2_LEN 0x48
113#define CH9121_CMD_PORT2_FLUSH 0x49
114
130static uint8_t a_ch9121_write_check(ch9121_handle_t *handle,
131 uint8_t *param, uint16_t len,
132 uint16_t pre_delay, uint16_t timeout)
133{
134 uint16_t t;
135 uint8_t res;
136
137 if (len > 126) /* check length */
138 {
139 handle->debug_print("ch9121: len is invalid.\n"); /* len is invalid */
140
141 return 2; /* return error */
142 }
143
144 handle->buf[0] = 0x57; /* set header 0 */
145 handle->buf[1] = 0xAB; /* set header 1 */
146 memcpy(&handle->buf[2], param, len); /* copy param */
147 res = handle->cfg_gpio_write(0); /* set low */
148 if (res != 0) /* check result */
149 {
150 return 1; /* return error */
151 }
152 res = handle->uart_flush(); /* uart flush */
153 if (res != 0) /* check result */
154 {
155 return 1; /* return error */
156 }
157 if (handle->uart_write(handle->buf, 2 + len) != 0) /* write command */
158 {
159 handle->debug_print("ch9121: write failed.\n"); /* write failed */
160 (void)handle->cfg_gpio_write(1); /* set high */
161
162 return 1; /* return error */
163 }
164 if (pre_delay != 0) /* check pre_delay */
165 {
166 handle->delay_ms(pre_delay); /* delay pre_delay */
167 }
168
169 t = timeout / 10; /* 10ms */
170 while (t != 0) /* check timeout */
171 {
172 if (handle->uart_read(&res, 1) == 1) /* read data */
173 {
174 if (res == 0xAA) /* check 0xAA */
175 {
176 res = handle->cfg_gpio_write(1); /* set high */
177 if (res != 0) /* check result */
178 {
179 return 1; /* return error */
180 }
181
182 return 0; /* success return 0 */
183 }
184 else
185 {
186 handle->debug_print("ch9121: error.\n"); /* error */
187 (void)handle->cfg_gpio_write(1); /* set high */
188
189 return 3; /* return error */
190 }
191 }
192 handle->delay_ms(10); /* delay 10ms */
193 t--; /* timeout-- */
194 }
195
196 handle->debug_print("ch9121: timeout.\n"); /* timeout */
197 (void)handle->cfg_gpio_write(1); /* set high */
198
199 return 4; /* return error */
200}
201
218static uint8_t a_ch9121_write_read(ch9121_handle_t *handle,
219 uint8_t *param, uint16_t len,
220 uint8_t *out, uint16_t out_len,
221 uint16_t pre_delay, uint16_t timeout)
222{
223 uint8_t res;
224 uint16_t t;
225 uint16_t point;
226
227 if (len > 126) /* check length */
228 {
229 handle->debug_print("ch9121: len is invalid.\n"); /* len is invalid */
230
231 return 2; /* return error */
232 }
233
234 handle->buf[0] = 0x57; /* set header 0 */
235 handle->buf[1] = 0xAB; /* set header 1 */
236 memcpy(&handle->buf[2], param, len); /* copy param */
237 res = handle->cfg_gpio_write(0); /* set low */
238 if (res != 0) /* check result */
239 {
240 return 1; /* return error */
241 }
242 res = handle->uart_flush(); /* uart flush */
243 if (res != 0) /* check result */
244 {
245 return 1; /* return error */
246 }
247 if (handle->uart_write(handle->buf, 2 + len) != 0) /* write command */
248 {
249 handle->debug_print("ch9121: write failed.\n"); /* write failed */
250 (void)handle->cfg_gpio_write(1); /* set high */
251
252 return 1; /* return error */
253 }
254 if (pre_delay != 0) /* check pre_delay */
255 {
256 handle->delay_ms(pre_delay); /* delay pre_delay */
257 }
258
259 point = 0; /* init 0 */
260 t = timeout / 10; /* 10ms */
261 while (t != 0) /* check timeout */
262 {
263 uint16_t l;
264
265 l = handle->uart_read(&out[point], out_len - point); /* read data */
266 if (l != 0)
267 {
268 point += l; /* point += l*/
269 if (point >= out_len) /* check length */
270 {
271 res = handle->cfg_gpio_write(1); /* set high */
272 if (res != 0) /* check result */
273 {
274 return 1; /* return error */
275 }
276
277 return 0; /* success return 0 */
278 }
279 }
280 handle->delay_ms(10); /* delay 10ms */
281 t--; /* timeout-- */
282 }
283
284 handle->debug_print("ch9121: timeout.\n"); /* timeout */
285 (void)handle->cfg_gpio_write(1); /* set high */
286
287 return 3; /* return error */
288}
289
301uint8_t ch9121_get_version(ch9121_handle_t *handle, uint8_t *version)
302{
303 uint8_t cmd;
304
305 if (handle == NULL) /* check handle */
306 {
307 return 2; /* return error */
308 }
309 if (handle->inited != 1) /* check handle initialization */
310 {
311 return 3; /* return error */
312 }
313
314 cmd = CH9121_CMD_CHIP_VERSION; /* set chip version */
315 if (a_ch9121_write_read(handle, &cmd, 1, version, 1,
316 CH9121_UART_PRE_DELAY, 1000) != 0) /* get version */
317 {
318 return 1; /* return error */
319 }
320
321 return 0; /* success return 0 */
322}
323
334uint8_t ch9121_reset(ch9121_handle_t *handle)
335{
336 uint8_t cmd;
337
338 if (handle == NULL) /* check handle */
339 {
340 return 2; /* return error */
341 }
342 if (handle->inited != 1) /* check handle initialization */
343 {
344 return 3; /* return error */
345 }
346
347 cmd = CH9121_CMD_RESET; /* set reset */
348 if (a_ch9121_write_check(handle, &cmd, 1,
349 CH9121_UART_PRE_DELAY, 1000) != 0) /* reset */
350 {
351 return 1; /* return error */
352 }
353 handle->delay_ms(1000); /* delay 1000ms */
354
355 return 0; /* success return 0 */
356}
357
368uint8_t ch9121_save_to_eeprom(ch9121_handle_t *handle)
369{
370 uint8_t cmd;
371
372 if (handle == NULL) /* check handle */
373 {
374 return 2; /* return error */
375 }
376 if (handle->inited != 1) /* check handle initialization */
377 {
378 return 3; /* return error */
379 }
380
381 cmd = CH9121_CMD_SAVE_TO_EEPROM; /* set save to eeprom */
382 if (a_ch9121_write_check(handle, &cmd, 1,
383 CH9121_UART_PRE_DELAY, 1000) != 0) /* save to eeprom */
384 {
385 return 1; /* return error */
386 }
387
388 return 0; /* success return 0 */
389}
390
401uint8_t ch9121_config_and_reset(ch9121_handle_t *handle)
402{
403 uint8_t cmd;
404
405 if (handle == NULL) /* check handle */
406 {
407 return 2; /* return error */
408 }
409 if (handle->inited != 1) /* check handle initialization */
410 {
411 return 3; /* return error */
412 }
413
414 cmd = CH9121_CMD_RUN_AND_RESET; /* set run config reset */
415 if (a_ch9121_write_check(handle, &cmd, 1,
416 CH9121_UART_PRE_DELAY, 1000) != 0) /* run config reset */
417 {
418 return 1; /* return error */
419 }
420 handle->delay_ms(1000); /* delay 1000ms */
421
422 return 0; /* success return 0 */
423}
424
435uint8_t ch9121_exit(ch9121_handle_t *handle)
436{
437 uint8_t cmd;
438
439 if (handle == NULL) /* check handle */
440 {
441 return 2; /* return error */
442 }
443 if (handle->inited != 1) /* check handle initialization */
444 {
445 return 3; /* return error */
446 }
447
448 cmd = CH9121_CMD_EXIT; /* set exit */
449 if (a_ch9121_write_check(handle, &cmd, 1,
450 CH9121_UART_PRE_DELAY, 1000) != 0) /* exit */
451 {
452 return 1; /* return error */
453 }
454
455 return 0; /* success return 0 */
456}
457
469uint8_t ch9121_set_dhcp(ch9121_handle_t *handle, ch9121_bool_t enable)
470{
471 uint8_t cmd[2];
472
473 if (handle == NULL) /* check handle */
474 {
475 return 2; /* return error */
476 }
477 if (handle->inited != 1) /* check handle initialization */
478 {
479 return 3; /* return error */
480 }
481
482 cmd[0] = CH9121_CMD_DHCP; /* set dhcp */
483 cmd[1] = enable; /* set bool */
484 if (a_ch9121_write_check(handle, cmd, 2,
485 CH9121_UART_PRE_DELAY, 1000) != 0) /* dhcp */
486 {
487 return 1; /* return error */
488 }
489
490 return 0; /* success return 0 */
491}
492
504uint8_t ch9121_get_mac(ch9121_handle_t *handle, uint8_t mac[6])
505{
506 uint8_t cmd;
507
508 if (handle == NULL) /* check handle */
509 {
510 return 2; /* return error */
511 }
512 if (handle->inited != 1) /* check handle initialization */
513 {
514 return 3; /* return error */
515 }
516
517 cmd = CH9121_CMD_MAC; /* set mac */
518 if (a_ch9121_write_read(handle, &cmd, 1, mac, 6,
519 CH9121_UART_PRE_DELAY, 1000) != 0) /* mac*/
520 {
521 return 1; /* return error */
522 }
523
524 return 0; /* success return 0 */
525}
526
539uint8_t ch9121_get_status(ch9121_handle_t *handle, ch9121_port_t port, ch9121_status_t *status)
540{
541 uint8_t cmd;
542 uint8_t param;
543
544 if (handle == NULL) /* check handle */
545 {
546 return 2; /* return error */
547 }
548 if (handle->inited != 1) /* check handle initialization */
549 {
550 return 3; /* return error */
551 }
552
553 if (port == CH9121_PORT1) /* port1 */
554 {
555 cmd = CH9121_CMD_PORT1_GET_STATUS; /* get port1 status */
556 }
557 else /* port2 */
558 {
559 cmd = CH9121_CMD_PORT2_GET_STATUS; /* get port2 status */
560 }
561 if (a_ch9121_write_read(handle, &cmd, 1, &param, 1,
562 CH9121_UART_PRE_DELAY, 1000) != 0) /* get status */
563 {
564 return 1; /* return error */
565 }
566 *status = (ch9121_status_t)(param); /* get the status */
567
568 return 0; /* success return 0 */
569}
570
583uint8_t ch9121_set_mode(ch9121_handle_t *handle, ch9121_port_t port, ch9121_mode_t mode)
584{
585 uint8_t cmd[2];
586
587 if (handle == NULL) /* check handle */
588 {
589 return 2; /* return error */
590 }
591 if (handle->inited != 1) /* check handle initialization */
592 {
593 return 3; /* return error */
594 }
595
596 if (port == CH9121_PORT1) /* port1 */
597 {
598 cmd[0] = CH9121_CMD_PORT1_SET_MODE; /* set port1 mode */
599 }
600 else /* port2 */
601 {
602 cmd[0] = CH9121_CMD_PORT2_SET_MODE; /* set port2 mode */
603 }
604 cmd[1] = mode; /* set mode */
605 if (a_ch9121_write_check(handle, cmd, 2,
606 CH9121_UART_PRE_DELAY, 1000) != 0) /* write mode */
607 {
608 return 1; /* return error */
609 }
610
611 return 0; /* success return 0 */
612}
613
626uint8_t ch9121_get_mode(ch9121_handle_t *handle, ch9121_port_t port, ch9121_mode_t *mode)
627{
628 uint8_t cmd;
629 uint8_t param;
630
631 if (handle == NULL) /* check handle */
632 {
633 return 2; /* return error */
634 }
635 if (handle->inited != 1) /* check handle initialization */
636 {
637 return 3; /* return error */
638 }
639
640 if (port == CH9121_PORT1) /* port1 */
641 {
642 cmd = CH9121_CMD_PORT1_GET_MODE; /* get port1 mode */
643 }
644 else /* port2 */
645 {
646 cmd = CH9121_CMD_PORT2_GET_MODE; /* get port2 mode */
647 }
648 if (a_ch9121_write_read(handle, &cmd, 1, &param, 1,
649 CH9121_UART_PRE_DELAY, 1000) != 0) /* get mode */
650 {
651 return 1; /* return error */
652 }
653 *mode = (ch9121_mode_t)(param); /* get mode */
654
655 return 0; /* success return 0 */
656}
657
669uint8_t ch9121_set_ip(ch9121_handle_t *handle, uint8_t ip[4])
670{
671 uint8_t cmd[5];
672
673 if (handle == NULL) /* check handle */
674 {
675 return 2; /* return error */
676 }
677 if (handle->inited != 1) /* check handle initialization */
678 {
679 return 3; /* return error */
680 }
681
682 cmd[0] = CH9121_CMD_SET_IP; /* set ip */
683 cmd[1] = ip[0]; /* set ip[0] */
684 cmd[2] = ip[1]; /* set ip[1] */
685 cmd[3] = ip[2]; /* set ip[2] */
686 cmd[4] = ip[3]; /* set ip[3] */
687 if (a_ch9121_write_check(handle, cmd, 5,
688 CH9121_UART_PRE_DELAY, 1000) != 0) /* write ip */
689 {
690 return 1; /* return error */
691 }
692
693 return 0; /* success return 0 */
694}
695
707uint8_t ch9121_get_ip(ch9121_handle_t *handle, uint8_t ip[4])
708{
709 uint8_t cmd;
710
711 if (handle == NULL) /* check handle */
712 {
713 return 2; /* return error */
714 }
715 if (handle->inited != 1) /* check handle initialization */
716 {
717 return 3; /* return error */
718 }
719
720 cmd = CH9121_CMD_GET_IP; /* get ip */
721 if (a_ch9121_write_read(handle, &cmd, 1, ip, 4,
722 CH9121_UART_PRE_DELAY, 1000) != 0) /* read ip */
723 {
724 return 1; /* return error */
725 }
726
727 return 0; /* success return 0 */
728}
729
741uint8_t ch9121_set_subnet_mask(ch9121_handle_t *handle, uint8_t mask[4])
742{
743 uint8_t cmd[5];
744
745 if (handle == NULL) /* check handle */
746 {
747 return 2; /* return error */
748 }
749 if (handle->inited != 1) /* check handle initialization */
750 {
751 return 3; /* return error */
752 }
753
754 cmd[0] = CH9121_CMD_SET_NETMASK ; /* set sub mask */
755 cmd[1] = mask[0]; /* set mask[0] */
756 cmd[2] = mask[1]; /* set mask[1] */
757 cmd[3] = mask[2]; /* set mask[2] */
758 cmd[4] = mask[3]; /* set mask[3] */
759 if (a_ch9121_write_check(handle, cmd, 5,
760 CH9121_UART_PRE_DELAY, 1000) != 0) /* write subnet mask */
761 {
762 return 1; /* return error */
763 }
764
765 return 0; /* success return 0 */
766}
767
779uint8_t ch9121_get_subnet_mask(ch9121_handle_t *handle, uint8_t mask[4])
780{
781 uint8_t cmd;
782
783 if (handle == NULL) /* check handle */
784 {
785 return 2; /* return error */
786 }
787 if (handle->inited != 1) /* check handle initialization */
788 {
789 return 3; /* return error */
790 }
791
792 cmd = CH9121_CMD_GET_NETMASK ; /* get mask */
793 if (a_ch9121_write_read(handle, &cmd, 1, mask, 4,
794 CH9121_UART_PRE_DELAY, 1000) != 0) /* read subnet mask */
795 {
796 return 1; /* return error */
797 }
798
799 return 0; /* success return 0 */
800}
801
813uint8_t ch9121_set_gateway(ch9121_handle_t *handle, uint8_t ip[4])
814{
815 uint8_t cmd[5];
816
817 if (handle == NULL) /* check handle */
818 {
819 return 2; /* return error */
820 }
821 if (handle->inited != 1) /* check handle initialization */
822 {
823 return 3; /* return error */
824 }
825
826 cmd[0] = CH9121_CMD_SET_GATEWAY ; /* set gateway */
827 cmd[1] = ip[0]; /* set ip[0] */
828 cmd[2] = ip[1]; /* set ip[1] */
829 cmd[3] = ip[2]; /* set ip[2] */
830 cmd[4] = ip[3]; /* set ip[3] */
831 if (a_ch9121_write_check(handle, cmd, 5,
832 CH9121_UART_PRE_DELAY, 1000) != 0) /* write ip */
833 {
834 return 1; /* return error */
835 }
836
837 return 0; /* success return 0 */
838}
839
851uint8_t ch9121_get_gateway(ch9121_handle_t *handle, uint8_t ip[4])
852{
853 uint8_t cmd;
854
855 if (handle == NULL) /* check handle */
856 {
857 return 2; /* return error */
858 }
859 if (handle->inited != 1) /* check handle initialization */
860 {
861 return 3; /* return error */
862 }
863
864 cmd = CH9121_CMD_GET_GATEWAY; /* get gateway */
865 if (a_ch9121_write_read(handle, &cmd, 1, ip, 4,
866 CH9121_UART_PRE_DELAY, 1000) != 0) /* read gateway */
867 {
868 return 1; /* return error */
869 }
870
871 return 0; /* success return 0 */
872}
873
886uint8_t ch9121_set_source_port(ch9121_handle_t *handle, ch9121_port_t port, uint16_t num)
887{
888 uint8_t cmd[3];
889
890 if (handle == NULL) /* check handle */
891 {
892 return 2; /* return error */
893 }
894 if (handle->inited != 1) /* check handle initialization */
895 {
896 return 3; /* return error */
897 }
898
899 if (port == CH9121_PORT1) /* port1 */
900 {
901 cmd[0] = CH9121_CMD_PORT1_SET_PORT; /* set port1 port */
902 }
903 else /* port2 */
904 {
905 cmd[0] = CH9121_CMD_PORT2_SET_PORT; /* set port2 port */
906 }
907 cmd[1] = (num >> 0) & 0xFF; /* set port msb */
908 cmd[2] = (num >> 8) & 0xFF; /* set port lsb */
909 if (a_ch9121_write_check(handle, cmd, 3,
910 CH9121_UART_PRE_DELAY, 1000) != 0) /* write port */
911 {
912 return 1; /* return error */
913 }
914
915 return 0; /* success return 0 */
916}
917
930uint8_t ch9121_get_source_port(ch9121_handle_t *handle, ch9121_port_t port, uint16_t *num)
931{
932 uint8_t cmd;
933 uint8_t buf[2];
934
935 if (handle == NULL) /* check handle */
936 {
937 return 2; /* return error */
938 }
939 if (handle->inited != 1) /* check handle initialization */
940 {
941 return 3; /* return error */
942 }
943
944 if (port == CH9121_PORT1) /* port1 */
945 {
946 cmd = CH9121_CMD_PORT1_GET_PORT; /* get port1 port */
947 }
948 else /* port2 */
949 {
950 cmd = CH9121_CMD_PORT2_GET_PORT; /* get port2 port */
951 }
952 if (a_ch9121_write_read(handle, &cmd, 1, buf, 2,
953 CH9121_UART_PRE_DELAY, 1000) != 0) /* get port */
954 {
955 return 1; /* return error */
956 }
957 *num= (uint16_t)((uint16_t)buf[1] << 8 | buf[0]); /* get port */
958
959 return 0; /* success return 0 */
960}
961
974uint8_t ch9121_set_dest_ip(ch9121_handle_t *handle, ch9121_port_t port, uint8_t ip[4])
975{
976 uint8_t cmd[5];
977
978 if (handle == NULL) /* check handle */
979 {
980 return 2; /* return error */
981 }
982 if (handle->inited != 1) /* check handle initialization */
983 {
984 return 3; /* return error */
985 }
986
987 if (port == CH9121_PORT1) /* port1 */
988 {
989 cmd[0] = CH9121_CMD_PORT1_SET_DST_IP; /* set port1 dest ip */
990 }
991 else /* port2 */
992 {
993 cmd[0] = CH9121_CMD_PORT2_SET_DST_IP; /* set port2 dest ip */
994 }
995 cmd[1] = ip[0]; /* set ip[0] */
996 cmd[2] = ip[1]; /* set ip[1] */
997 cmd[3] = ip[2]; /* set ip[0] */
998 cmd[4] = ip[3]; /* set ip[1] */
999 if (a_ch9121_write_check(handle, cmd, 5,
1000 CH9121_UART_PRE_DELAY, 1000) != 0) /* write dest ip */
1001 {
1002 return 1; /* return error */
1003 }
1004
1005 return 0; /* success return 0 */
1006}
1007
1020uint8_t ch9121_get_dest_ip(ch9121_handle_t *handle, ch9121_port_t port, uint8_t ip[4])
1021{
1022 uint8_t cmd;
1023
1024 if (handle == NULL) /* check handle */
1025 {
1026 return 2; /* return error */
1027 }
1028 if (handle->inited != 1) /* check handle initialization */
1029 {
1030 return 3; /* return error */
1031 }
1032
1033 if (port == CH9121_PORT1) /* port1 */
1034 {
1035 cmd = CH9121_CMD_PORT1_GET_DST_IP; /* get port1 dest ip */
1036 }
1037 else /* port2 */
1038 {
1039 cmd = CH9121_CMD_PORT2_GET_DST_IP; /* get port2 dest ip */
1040 }
1041 if (a_ch9121_write_read(handle, &cmd, 1, ip, 4,
1042 CH9121_UART_PRE_DELAY, 1000) != 0) /* get dest ip */
1043 {
1044 return 1; /* return error */
1045 }
1046
1047
1048 return 0; /* success return 0 */
1049}
1050
1063uint8_t ch9121_set_dest_port(ch9121_handle_t *handle, ch9121_port_t port, uint16_t num)
1064{
1065 uint8_t cmd[3];
1066
1067 if (handle == NULL) /* check handle */
1068 {
1069 return 2; /* return error */
1070 }
1071 if (handle->inited != 1) /* check handle initialization */
1072 {
1073 return 3; /* return error */
1074 }
1075
1076 if (port == CH9121_PORT1) /* port1 */
1077 {
1078 cmd[0] = CH9121_CMD_PORT1_SET_DST_PORT; /* set port1 dest port */
1079 }
1080 else /* port2 */
1081 {
1082 cmd[0] = CH9121_CMD_PORT2_SET_DST_PORT; /* set port2 dest port */
1083 }
1084 cmd[1] = (num >> 0) & 0xFF; /* set port msb */
1085 cmd[2] = (num >> 8) & 0xFF; /* set port lsb */
1086 if (a_ch9121_write_check(handle, cmd, 3,
1087 CH9121_UART_PRE_DELAY, 1000) != 0) /* write dest port */
1088 {
1089 return 1; /* return error */
1090 }
1091
1092 return 0; /* success return 0 */
1093}
1094
1107uint8_t ch9121_get_dest_port(ch9121_handle_t *handle, ch9121_port_t port, uint16_t *num)
1108{
1109 uint8_t cmd;
1110 uint8_t buf[2];
1111
1112 if (handle == NULL) /* check handle */
1113 {
1114 return 2; /* return error */
1115 }
1116 if (handle->inited != 1) /* check handle initialization */
1117 {
1118 return 3; /* return error */
1119 }
1120
1121 if (port == CH9121_PORT1) /* port1 */
1122 {
1123 cmd = CH9121_CMD_PORT1_GET_DST_PORT; /* get port1 dest port */
1124 }
1125 else /* port2 */
1126 {
1127 cmd = CH9121_CMD_PORT2_GET_DST_PORT; /* get port2 dest port */
1128 }
1129 if (a_ch9121_write_read(handle, &cmd, 1, buf, 2,
1130 CH9121_UART_PRE_DELAY, 1000) != 0) /* get dest port */
1131 {
1132 return 1; /* return error */
1133 }
1134 *num= (uint16_t)((uint16_t)buf[1] << 8 | buf[0]); /* get port */
1135
1136 return 0; /* success return 0 */
1137}
1138
1151uint8_t ch9121_set_uart_baud(ch9121_handle_t *handle, ch9121_port_t port, uint32_t baud)
1152{
1153 uint8_t cmd[5];
1154
1155 if (handle == NULL) /* check handle */
1156 {
1157 return 2; /* return error */
1158 }
1159 if (handle->inited != 1) /* check handle initialization */
1160 {
1161 return 3; /* return error */
1162 }
1163
1164 if (port == CH9121_PORT1) /* port1 */
1165 {
1166 cmd[0] = CH9121_CMD_PORT1_SET_BAUD; /* set port1 baud */
1167 }
1168 else /* port2 */
1169 {
1170 cmd[0] = CH9121_CMD_PORT2_SET_BAUD; /* set port2 baud */
1171 }
1172 cmd[1] = (baud >> 0) & 0xFF; /* set baud[0] */
1173 cmd[2] = (baud >> 8) & 0xFF; /* set baud[8] */
1174 cmd[3] = (baud >> 16) & 0xFF; /* set baud[16] */
1175 cmd[4] = (baud >> 24) & 0xFF; /* set baud[24] */
1176 if (a_ch9121_write_check(handle, cmd, 5,
1177 CH9121_UART_PRE_DELAY, 1000) != 0) /* write dest port */
1178 {
1179 return 1; /* return error */
1180 }
1181
1182 return 0; /* success return 0 */
1183}
1184
1197uint8_t ch9121_get_uart_baud(ch9121_handle_t *handle, ch9121_port_t port, uint32_t *baud)
1198{
1199 uint8_t cmd;
1200 uint8_t buf[4];
1201
1202 if (handle == NULL) /* check handle */
1203 {
1204 return 2; /* return error */
1205 }
1206 if (handle->inited != 1) /* check handle initialization */
1207 {
1208 return 3; /* return error */
1209 }
1210
1211 if (port == CH9121_PORT1) /* port1 */
1212 {
1213 cmd = CH9121_CMD_PORT1_GET_BAUD; /* get port1 baud */
1214 }
1215 else /* port2 */
1216 {
1217 cmd = CH9121_CMD_PORT2_GET_BAUD; /* get port2 baud */
1218 }
1219 if (a_ch9121_write_read(handle, &cmd, 1, buf, 4,
1220 CH9121_UART_PRE_DELAY, 1000) != 0) /* get dest port */
1221 {
1222 return 1; /* return error */
1223 }
1224 *baud = (uint32_t)(((uint32_t)buf[0] << 0) | ((uint32_t)buf[1] << 8) |
1225 ((uint32_t)buf[2] << 16) | ((uint32_t)buf[3] << 24)); /* get baud */
1226
1227 return 0; /* success return 0 */
1228}
1229
1244uint8_t ch9121_set_uart_config(ch9121_handle_t *handle, ch9121_port_t port, uint8_t data_bit, ch9121_parity_t parity, uint8_t stop_bit)
1245{
1246 uint8_t cmd[4];
1247
1248 if (handle == NULL) /* check handle */
1249 {
1250 return 2; /* return error */
1251 }
1252 if (handle->inited != 1) /* check handle initialization */
1253 {
1254 return 3; /* return error */
1255 }
1256
1257 if (port == CH9121_PORT1) /* port1 */
1258 {
1259 cmd[0] = CH9121_CMD_PORT1_SET_CONFIG; /* set port1 config */
1260 }
1261 else /* port2 */
1262 {
1263 cmd[0] = CH9121_CMD_PORT2_SET_CONFIG; /* set port2 config */
1264 }
1265 cmd[1] = stop_bit; /* set stop bit */
1266 cmd[2] = parity; /* set parity */
1267 cmd[3] = data_bit; /* set data bit */
1268 if (a_ch9121_write_check(handle, cmd, 4,
1269 CH9121_UART_PRE_DELAY, 1000) != 0) /* write dest port */
1270 {
1271 return 1; /* return error */
1272 }
1273
1274 return 0; /* success return 0 */
1275}
1276
1291uint8_t ch9121_get_uart_config(ch9121_handle_t *handle, ch9121_port_t port, uint8_t *data_bit, ch9121_parity_t *parity, uint8_t *stop_bit)
1292{
1293 uint8_t cmd;
1294 uint8_t buf[3];
1295
1296 if (handle == NULL) /* check handle */
1297 {
1298 return 2; /* return error */
1299 }
1300 if (handle->inited != 1) /* check handle initialization */
1301 {
1302 return 3; /* return error */
1303 }
1304
1305 if (port == CH9121_PORT1) /* port1 */
1306 {
1307 cmd = CH9121_CMD_PORT1_GET_CONFIG; /* get port1 config */
1308 }
1309 else /* port2 */
1310 {
1311 cmd = CH9121_CMD_PORT2_GET_CONFIG; /* get port2 config */
1312 }
1313 if (a_ch9121_write_read(handle, &cmd, 1, buf, 3,
1314 CH9121_UART_PRE_DELAY, 1000) != 0) /* get dest port */
1315 {
1316 return 1; /* return error */
1317 }
1318 *stop_bit = buf[0]; /* get stop bit */
1319 *parity = (ch9121_parity_t)buf[1]; /* get parity */
1320 *data_bit = buf[2]; /* get data bit */
1321
1322 return 0; /* success return 0 */
1323}
1324
1337uint8_t ch9121_set_uart_timeout(ch9121_handle_t *handle, ch9121_port_t port, uint8_t timeout)
1338{
1339 uint8_t cmd[5];
1340
1341 if (handle == NULL) /* check handle */
1342 {
1343 return 2; /* return error */
1344 }
1345 if (handle->inited != 1) /* check handle initialization */
1346 {
1347 return 3; /* return error */
1348 }
1349
1350 if (port == CH9121_PORT1) /* port1 */
1351 {
1352 cmd[0] = CH9121_CMD_PORT1_SET_TIMEOUT; /* set port1 timeout */
1353 }
1354 else /* port2 */
1355 {
1356 cmd[0] = CH9121_CMD_PORT2_SET_TIMEOUT; /* set port2 timeout */
1357 }
1358 cmd[1] = timeout; /* set timeout */
1359 cmd[2] = 0x00; /* set 0x00 */
1360 cmd[3] = 0x00; /* set 0x00 */
1361 cmd[4] = 0x00; /* set 0x00 */
1362 if (a_ch9121_write_check(handle, cmd, 5,
1363 CH9121_UART_PRE_DELAY, 1000) != 0) /* write uart timeout */
1364 {
1365 return 1; /* return error */
1366 }
1367
1368 return 0; /* success return 0 */
1369}
1370
1383uint8_t ch9121_get_uart_timeout(ch9121_handle_t *handle, ch9121_port_t port, uint8_t *timeout)
1384{
1385 uint8_t cmd;
1386
1387 if (handle == NULL) /* check handle */
1388 {
1389 return 2; /* return error */
1390 }
1391 if (handle->inited != 1) /* check handle initialization */
1392 {
1393 return 3; /* return error */
1394 }
1395
1396 if (port == CH9121_PORT1) /* port1 */
1397 {
1398 cmd = CH9121_CMD_PORT1_GET_TIMEOUT; /* get port1 timeout */
1399 }
1400 else /* port2 */
1401 {
1402 cmd = CH9121_CMD_PORT2_GET_TIMEOUT; /* get port2 timeout */
1403 }
1404 if (a_ch9121_write_read(handle, &cmd, 1, timeout, 1,
1405 CH9121_UART_PRE_DELAY, 1000) != 0) /* get uart timeout */
1406 {
1407 return 1; /* return error */
1408 }
1409
1410 return 0; /* success return 0 */
1411}
1412
1424uint8_t ch9121_uart_timeout_convert_to_register(ch9121_handle_t *handle, uint16_t ms, uint8_t *reg)
1425{
1426 if (handle == NULL) /* check handle */
1427 {
1428 return 2; /* return error */
1429 }
1430 if (handle->inited != 1) /* check handle initialization */
1431 {
1432 return 3; /* return error */
1433 }
1434
1435 *reg = (uint8_t)(ms / 5); /* convert real data to register data */
1436
1437 return 0; /* success return 0 */
1438}
1439
1451uint8_t ch9121_uart_timeout_convert_to_data(ch9121_handle_t *handle, uint8_t reg, uint16_t *ms)
1452{
1453 if (handle == NULL) /* check handle */
1454 {
1455 return 2; /* return error */
1456 }
1457 if (handle->inited != 1) /* check handle initialization */
1458 {
1459 return 3; /* return error */
1460 }
1461
1462 *ms = reg * 5; /* convert raw data to real data */
1463
1464 return 0; /* success return 0 */
1465}
1466
1479uint8_t ch9121_set_source_port_random(ch9121_handle_t *handle, ch9121_port_t port, ch9121_bool_t enable)
1480{
1481 uint8_t cmd[2];
1482
1483 if (handle == NULL) /* check handle */
1484 {
1485 return 2; /* return error */
1486 }
1487 if (handle->inited != 1) /* check handle initialization */
1488 {
1489 return 3; /* return error */
1490 }
1491
1492 if (port == CH9121_PORT1) /* port1 */
1493 {
1494 cmd[0] = CH9121_CMD_PORT1_RANDOM_PORT; /* set port1 random */
1495 }
1496 else /* port2 */
1497 {
1498 cmd[0] = CH9121_CMD_PORT2_RANDOM_PORT ; /* set port2 random */
1499 }
1500 cmd[1] = enable; /* set bool */
1501 if (a_ch9121_write_check(handle, cmd, 2,
1502 CH9121_UART_PRE_DELAY, 1000) != 0) /* write source port random */
1503 {
1504 return 1; /* return error */
1505 }
1506
1507 return 0; /* success return 0 */
1508}
1509
1522uint8_t ch9121_set_uart_buffer_length(ch9121_handle_t *handle, ch9121_port_t port, uint32_t len)
1523{
1524 uint8_t cmd[5];
1525
1526 if (handle == NULL) /* check handle */
1527 {
1528 return 2; /* return error */
1529 }
1530 if (handle->inited != 1) /* check handle initialization */
1531 {
1532 return 3; /* return error */
1533 }
1534
1535 if (port == CH9121_PORT1) /* port1 */
1536 {
1537 cmd[0] = CH9121_CMD_PORT1_LEN; /* set port1 uart buffer */
1538 }
1539 else /* port2 */
1540 {
1541 cmd[0] = CH9121_CMD_PORT2_LEN ; /* set port2 uart buffer */
1542 }
1543 cmd[1] = (len >> 0) & 0xFF; /* set len[0] */
1544 cmd[2] = (len >> 8) & 0xFF; /* set len[8] */
1545 cmd[3] = (len >> 16) & 0xFF; /* set len[16] */
1546 cmd[4] = (len >> 24) & 0xFF; /* set len[24] */
1547 if (a_ch9121_write_check(handle, cmd, 5,
1548 CH9121_UART_PRE_DELAY, 1000) != 0) /* write uart buffer */
1549 {
1550 return 1; /* return error */
1551 }
1552
1553 return 0; /* success return 0 */
1554}
1555
1568uint8_t ch9121_set_uart_flush(ch9121_handle_t *handle, ch9121_port_t port, ch9121_bool_t enable)
1569{
1570 uint8_t cmd[2];
1571
1572 if (handle == NULL) /* check handle */
1573 {
1574 return 2; /* return error */
1575 }
1576 if (handle->inited != 1) /* check handle initialization */
1577 {
1578 return 3; /* return error */
1579 }
1580
1581 if (port == CH9121_PORT1) /* port1 */
1582 {
1583 cmd[0] = CH9121_CMD_PORT1_FLUSH; /* set port1 flush */
1584 }
1585 else /* port2 */
1586 {
1587 cmd[0] = CH9121_CMD_PORT2_FLUSH ; /* set port2 flush */
1588 }
1589 cmd[1] = enable; /* set bool */
1590 if (a_ch9121_write_check(handle, cmd, 2,
1591 CH9121_UART_PRE_DELAY, 1000) != 0) /* write flush */
1592 {
1593 return 1; /* return error */
1594 }
1595
1596 return 0; /* success return 0 */
1597}
1598
1610uint8_t ch9121_set_port2(ch9121_handle_t *handle, ch9121_bool_t enable)
1611{
1612 uint8_t cmd[2];
1613
1614 if (handle == NULL) /* check handle */
1615 {
1616 return 2; /* return error */
1617 }
1618 if (handle->inited != 1) /* check handle initialization */
1619 {
1620 return 3; /* return error */
1621 }
1622
1623 cmd[0] = CH9121_CMD_PORT2_ENABLE; /* enable port2 */
1624 cmd[1] = enable; /* set bool */
1625 if (a_ch9121_write_check(handle, cmd, 2,
1626 CH9121_UART_PRE_DELAY, 1000) != 0) /* write enable */
1627 {
1628 return 1; /* return error */
1629 }
1630
1631 return 0; /* success return 0 */
1632}
1633
1645uint8_t ch9121_set_disconnect_with_no_rj45(ch9121_handle_t *handle, ch9121_bool_t enable)
1646{
1647 uint8_t cmd[2];
1648
1649 if (handle == NULL) /* check handle */
1650 {
1651 return 2; /* return error */
1652 }
1653 if (handle->inited != 1) /* check handle initialization */
1654 {
1655 return 3; /* return error */
1656 }
1657
1658 cmd[0] = CH9121_CMD_DISCONNECT; /* set disconnect */
1659 cmd[1] = enable; /* set bool */
1660 if (a_ch9121_write_check(handle, cmd, 2,
1661 CH9121_UART_PRE_DELAY, 1000) != 0) /* write disconnect */
1662 {
1663 return 1; /* return error */
1664 }
1665
1666 return 0; /* success return 0 */
1667}
1668
1680uint8_t ch9121_set_domain(ch9121_handle_t *handle, char *domain)
1681{
1682 uint8_t cmd[29];
1683
1684 if (handle == NULL) /* check handle */
1685 {
1686 return 2; /* return error */
1687 }
1688 if (handle->inited != 1) /* check handle initialization */
1689 {
1690 return 3; /* return error */
1691 }
1692 if (strlen(domain) > 28) /* check domain */
1693 {
1694 handle->debug_print("ch9121: domain > 28.\n"); /* domain > 28 */
1695
1696 return 4; /* return error */
1697 }
1698
1699 cmd[0] = CH9121_CMD_PORT1_DOMAIN ; /* set domain */
1700 memcpy(&cmd[1], (uint8_t *)domain, strlen(domain));
1701 if (a_ch9121_write_check(handle, cmd,
1702 (uint16_t)(strlen(domain) + 1),
1703 CH9121_UART_PRE_DELAY, 1000) != 0) /* write domain */
1704 {
1705 return 1; /* return error */
1706 }
1707
1708 return 0; /* success return 0 */
1709}
1710
1724uint8_t ch9121_init(ch9121_handle_t *handle)
1725{
1726 if (handle == NULL) /* check handle */
1727 {
1728 return 2; /* return error */
1729 }
1730 if (handle->debug_print == NULL) /* check debug_print */
1731 {
1732 return 3; /* return error */
1733 }
1734 if (handle->uart_init == NULL) /* check uart_init */
1735 {
1736 handle->debug_print("ch9121: uart_init is null.\n"); /* uart_init is null */
1737
1738 return 3; /* return error */
1739 }
1740 if (handle->uart_deinit == NULL) /* check uart_deinit */
1741 {
1742 handle->debug_print("ch9121: uart_deinit is null.\n"); /* uart_deinit is null */
1743
1744 return 3; /* return error */
1745 }
1746 if (handle->uart_read == NULL) /* check uart_read */
1747 {
1748 handle->debug_print("ch9121: uart_read is null.\n"); /* uart_read is null */
1749
1750 return 3; /* return error */
1751 }
1752 if (handle->uart_write == NULL) /* check uart_write */
1753 {
1754 handle->debug_print("ch9121: uart_write is null.\n"); /* uart_write is null */
1755
1756 return 3; /* return error */
1757 }
1758 if (handle->uart_flush == NULL) /* check uart_flush */
1759 {
1760 handle->debug_print("ch9121: uart_flush is null.\n"); /* uart_flush is null */
1761
1762 return 3; /* return error */
1763 }
1764 if (handle->delay_ms == NULL) /* check delay_ms */
1765 {
1766 handle->debug_print("ch9121: delay_ms is null.\n"); /* delay_ms is null */
1767
1768 return 3; /* return error */
1769 }
1770 if (handle->reset_gpio_init == NULL) /* check reset_gpio_init */
1771 {
1772 handle->debug_print("ch9121: reset_gpio_init is null.\n"); /* reset_gpio_init is null */
1773
1774 return 3; /* return error */
1775 }
1776 if (handle->reset_gpio_deinit == NULL) /* check reset_gpio_deinit */
1777 {
1778 handle->debug_print("ch9121: reset_gpio_deinit is null.\n"); /* reset_gpio_deinit is null */
1779
1780 return 3; /* return error */
1781 }
1782 if (handle->reset_gpio_write == NULL) /* check reset_gpio_write */
1783 {
1784 handle->debug_print("ch9121: reset_gpio_write is null.\n"); /* reset_gpio_write is null */
1785
1786 return 3; /* return error */
1787 }
1788 if (handle->cfg_gpio_init == NULL) /* check cfg_gpio_init */
1789 {
1790 handle->debug_print("ch9121: cfg_gpio_init is null.\n"); /* cfg_gpio_init is null */
1791
1792 return 3; /* return error */
1793 }
1794 if (handle->cfg_gpio_deinit == NULL) /* check cfg_gpio_deinit */
1795 {
1796 handle->debug_print("ch9121: cfg_gpio_deinit is null.\n"); /* cfg_gpio_deinit is null */
1797
1798 return 3; /* return error */
1799 }
1800 if (handle->cfg_gpio_write == NULL) /* check cfg_gpio_write */
1801 {
1802 handle->debug_print("ch9121: cfg_gpio_write is null.\n"); /* cfg_gpio_write is null */
1803
1804 return 3; /* return error */
1805 }
1806
1807 if (handle->uart_init() != 0) /* uart init */
1808 {
1809 handle->debug_print("ch9121: uart init failed.\n"); /* uart init failed */
1810
1811 return 1; /* return error */
1812 }
1813 if (handle->reset_gpio_init() != 0) /* reset gpio init */
1814 {
1815 handle->debug_print("ch9121: reset gpio init failed.\n"); /* reset gpio init failed */
1816 (void)handle->uart_deinit(); /* uart deinit */
1817
1818 return 4; /* return error */
1819 }
1820 if (handle->cfg_gpio_init() != 0) /* cfg gpio init */
1821 {
1822 handle->debug_print("ch9121: cfg gpio init failed.\n"); /* cfg gpio init failed */
1823 (void)handle->uart_deinit(); /* uart deinit */
1824 (void)handle->reset_gpio_deinit(); /* reset gpio deinit */
1825
1826 return 5; /* return error */
1827 }
1828 if (handle->reset_gpio_write(0) != 0) /* set low */
1829 {
1830 handle->debug_print("ch9121: cfg gpio write failed.\n"); /* cfg gpio write failed */
1831 (void)handle->uart_deinit(); /* uart deinit */
1832 (void)handle->reset_gpio_deinit(); /* reset gpio deinit */
1833 (void)handle->cfg_gpio_deinit(); /* cfg gpio deinit */
1834
1835 return 6; /* return error */
1836 }
1837 handle->delay_ms(10); /* delay 10ms */
1838 if (handle->reset_gpio_write(1) != 0) /* set high */
1839 {
1840 handle->debug_print("ch9121: cfg gpio write failed.\n"); /* cfg gpio write failed */
1841 (void)handle->uart_deinit(); /* uart deinit */
1842 (void)handle->reset_gpio_deinit(); /* reset gpio deinit */
1843 (void)handle->cfg_gpio_deinit(); /* cfg gpio deinit */
1844
1845 return 6; /* return error */
1846 }
1847 handle->delay_ms(1000); /* delay 1000ms */
1848 handle->inited = 1; /* flag finish initialization */
1849
1850 return 0; /* success return 0 */
1851}
1852
1866uint8_t ch9121_deinit(ch9121_handle_t *handle)
1867{
1868 uint8_t cmd;
1869
1870 if (handle == NULL) /* check handle */
1871 {
1872 return 2; /* return error */
1873 }
1874 if (handle->inited != 1) /* check handle initialization */
1875 {
1876 return 3; /* return error */
1877 }
1878
1879 cmd = CH9121_CMD_RESET; /* set reset */
1880 if (a_ch9121_write_check(handle, &cmd, 1,
1881 CH9121_UART_PRE_DELAY, 1000) != 0) /* reset */
1882 {
1883 return 4; /* return error */
1884 }
1885 handle->delay_ms(10); /* delay 10ms */
1886 if (handle->uart_deinit() != 0) /* uart deinit */
1887 {
1888 handle->debug_print("ch9121: uart deinit failed.\n"); /* uart deinit failed */
1889
1890 return 1; /* return error */
1891 }
1892 if (handle->reset_gpio_deinit() != 0) /* reset gpio deinit */
1893 {
1894 handle->debug_print("ch9121: reset gpio deinit failed.\n"); /* reset gpio deinit failed */
1895
1896 return 5; /* return error */
1897 }
1898 if (handle->cfg_gpio_deinit() != 0) /* cfg gpio deinit */
1899 {
1900 handle->debug_print("ch9121: cfg gpio deinit failed.\n"); /* cfg gpio deinit failed */
1901
1902 return 6; /* return error */
1903 }
1904
1905 return 0; /* success return 0 */
1906}
1907
1920uint8_t ch9121_write(ch9121_handle_t *handle, uint8_t *buf, uint16_t len)
1921{
1922 if (handle == NULL) /* check handle */
1923 {
1924 return 2; /* return error */
1925 }
1926 if (handle->inited != 1) /* check handle initialization */
1927 {
1928 return 3; /* return error */
1929 }
1930
1931 if (handle->cfg_gpio_write(1) != 0) /* cfg gpio write */
1932 {
1933 handle->debug_print("ch9121: cfg gpio write failed.\n"); /* cfg gpio write failed */
1934
1935 return 1; /* return error */
1936 }
1937 if (handle->uart_write(buf, len) != 0) /* uart write */
1938 {
1939 handle->debug_print("ch9121:uart write failed.\n"); /* uart write failed */
1940
1941 return 1; /* return error */
1942 }
1943
1944 return 0; /* success return 0 */
1945}
1946
1959uint8_t ch9121_read(ch9121_handle_t *handle, uint8_t *buf, uint16_t *len)
1960{
1961 uint16_t l;
1962
1963 if (handle == NULL) /* check handle */
1964 {
1965 return 2; /* return error */
1966 }
1967 if (handle->inited != 1) /* check handle initialization */
1968 {
1969 return 3; /* return error */
1970 }
1971
1972 if (handle->cfg_gpio_write(1) != 0) /* cfg gpio write */
1973 {
1974 handle->debug_print("ch9121: cfg gpio write failed.\n"); /* cfg gpio write failed */
1975
1976 return 1; /* return error */
1977 }
1978 l = handle->uart_read(buf, *len); /* uart read */
1979 *len = l; /* set data */
1980
1981 return 0; /* success return 0 */
1982}
1983
2000uint8_t ch9121_set_command(ch9121_handle_t *handle,
2001 uint8_t *param, uint16_t len,
2002 uint8_t *out, uint16_t out_len,
2003 uint16_t pre_delay, uint16_t timeout)
2004{
2005 if (handle == NULL) /* check handle */
2006 {
2007 return 2; /* return error */
2008 }
2009 if (handle->inited != 1) /* check handle initialization */
2010 {
2011 return 3; /* return error */
2012 }
2013
2014 if (a_ch9121_write_read(handle, param, len,
2015 out, out_len,
2016 pre_delay, timeout) != 0) /* set command */
2017 {
2018 return 1; /* return error */
2019 }
2020
2021 return 0; /* success return 0 */
2022}
2023
2032uint8_t ch9121_info(ch9121_info_t *info)
2033{
2034 if (info == NULL) /* check handle */
2035 {
2036 return 2; /* return error */
2037 }
2038
2039 memset(info, 0, sizeof(ch9121_info_t)); /* initialize ch9121 info structure */
2040 strncpy(info->chip_name, CHIP_NAME, 32); /* copy chip name */
2041 strncpy(info->manufacturer_name, MANUFACTURER_NAME, 32); /* copy manufacturer name */
2042 strncpy(info->interface, "UART", 8); /* copy interface name */
2043 info->supply_voltage_min_v = SUPPLY_VOLTAGE_MIN; /* set minimal supply voltage */
2044 info->supply_voltage_max_v = SUPPLY_VOLTAGE_MAX; /* set maximum supply voltage */
2045 info->max_current_ma = MAX_CURRENT; /* set maximum current */
2046 info->temperature_max = TEMPERATURE_MAX; /* set minimal temperature */
2047 info->temperature_min = TEMPERATURE_MIN; /* set maximum temperature */
2048 info->driver_version = DRIVER_VERSION; /* set driver version */
2049
2050 return 0; /* success return 0 */
2051}
CH9121_CMD_PORT2_SET_DST_PORT
#define CH9121_CMD_PORT2_SET_DST_PORT
Definition driver_ch9121.c:91
CH9121_CMD_GET_GATEWAY
#define CH9121_CMD_GET_GATEWAY
Definition driver_ch9121.c:66
CH9121_CMD_PORT2_GET_MODE
#define CH9121_CMD_PORT2_GET_MODE
Definition driver_ch9121.c:95
CH9121_CMD_PORT1_SET_DST_PORT
#define CH9121_CMD_PORT1_SET_DST_PORT
Definition driver_ch9121.c:76
CH9121_CMD_PORT1_SET_TIMEOUT
#define CH9121_CMD_PORT1_SET_TIMEOUT
Definition driver_ch9121.c:79
CH9121_CMD_EXIT
#define CH9121_CMD_EXIT
Definition driver_ch9121.c:58
MAX_CURRENT
#define MAX_CURRENT
Definition driver_ch9121.c:46
CH9121_CMD_PORT1_GET_TIMEOUT
#define CH9121_CMD_PORT1_GET_TIMEOUT
Definition driver_ch9121.c:86
CH9121_CMD_PORT1_GET_MODE
#define CH9121_CMD_PORT1_GET_MODE
Definition driver_ch9121.c:80
CH9121_CMD_GET_NETMASK
#define CH9121_CMD_GET_NETMASK
Definition driver_ch9121.c:65
CH9121_CMD_PORT1_RANDOM_PORT
#define CH9121_CMD_PORT1_RANDOM_PORT
chip port extern command definition
Definition driver_ch9121.c:106
CH9121_CMD_PORT2_GET_CONFIG
#define CH9121_CMD_PORT2_GET_CONFIG
Definition driver_ch9121.c:100
CH9121_CMD_PORT2_RANDOM_PORT
#define CH9121_CMD_PORT2_RANDOM_PORT
Definition driver_ch9121.c:111
CH9121_CMD_MAC
#define CH9121_CMD_MAC
Definition driver_ch9121.c:60
CH9121_CMD_PORT1_SET_BAUD
#define CH9121_CMD_PORT1_SET_BAUD
Definition driver_ch9121.c:77
CH9121_CMD_PORT1_GET_PORT
#define CH9121_CMD_PORT1_GET_PORT
Definition driver_ch9121.c:81
CH9121_CMD_PORT1_GET_CONFIG
#define CH9121_CMD_PORT1_GET_CONFIG
Definition driver_ch9121.c:85
CH9121_CMD_PORT2_SET_BAUD
#define CH9121_CMD_PORT2_SET_BAUD
Definition driver_ch9121.c:92
CH9121_CMD_DHCP
#define CH9121_CMD_DHCP
Definition driver_ch9121.c:59
CH9121_CMD_PORT1_LEN
#define CH9121_CMD_PORT1_LEN
Definition driver_ch9121.c:107
CH9121_CMD_PORT2_GET_STATUS
#define CH9121_CMD_PORT2_GET_STATUS
Definition driver_ch9121.c:87
CH9121_CMD_PORT2_SET_CONFIG
#define CH9121_CMD_PORT2_SET_CONFIG
Definition driver_ch9121.c:93
CH9121_CMD_CHIP_VERSION
#define CH9121_CMD_CHIP_VERSION
chip basic command definition
Definition driver_ch9121.c:54
CH9121_CMD_PORT2_SET_PORT
#define CH9121_CMD_PORT2_SET_PORT
Definition driver_ch9121.c:89
CH9121_CMD_RESET
#define CH9121_CMD_RESET
Definition driver_ch9121.c:55
CH9121_CMD_PORT1_SET_MODE
#define CH9121_CMD_PORT1_SET_MODE
Definition driver_ch9121.c:73
SUPPLY_VOLTAGE_MAX
#define SUPPLY_VOLTAGE_MAX
Definition driver_ch9121.c:45
CH9121_CMD_PORT2_SET_DST_IP
#define CH9121_CMD_PORT2_SET_DST_IP
Definition driver_ch9121.c:90
CH9121_CMD_PORT2_GET_DST_IP
#define CH9121_CMD_PORT2_GET_DST_IP
Definition driver_ch9121.c:97
CH9121_CMD_PORT1_GET_STATUS
#define CH9121_CMD_PORT1_GET_STATUS
chip port command definition
Definition driver_ch9121.c:72
CH9121_CMD_SAVE_TO_EEPROM
#define CH9121_CMD_SAVE_TO_EEPROM
Definition driver_ch9121.c:56
CH9121_CMD_SET_NETMASK
#define CH9121_CMD_SET_NETMASK
Definition driver_ch9121.c:62
CH9121_CMD_PORT2_SET_MODE
#define CH9121_CMD_PORT2_SET_MODE
Definition driver_ch9121.c:88
CH9121_CMD_GET_IP
#define CH9121_CMD_GET_IP
Definition driver_ch9121.c:64
CH9121_CMD_PORT1_FLUSH
#define CH9121_CMD_PORT1_FLUSH
Definition driver_ch9121.c:108
CH9121_CMD_PORT2_GET_DST_PORT
#define CH9121_CMD_PORT2_GET_DST_PORT
Definition driver_ch9121.c:98
CH9121_CMD_SET_IP
#define CH9121_CMD_SET_IP
Definition driver_ch9121.c:61
CH9121_CMD_PORT2_ENABLE
#define CH9121_CMD_PORT2_ENABLE
Definition driver_ch9121.c:110
CH9121_CMD_SET_GATEWAY
#define CH9121_CMD_SET_GATEWAY
Definition driver_ch9121.c:63
TEMPERATURE_MAX
#define TEMPERATURE_MAX
Definition driver_ch9121.c:48
CH9121_CMD_PORT1_GET_DST_IP
#define CH9121_CMD_PORT1_GET_DST_IP
Definition driver_ch9121.c:82
CH9121_CMD_PORT2_GET_BAUD
#define CH9121_CMD_PORT2_GET_BAUD
Definition driver_ch9121.c:99
MANUFACTURER_NAME
#define MANUFACTURER_NAME
Definition driver_ch9121.c:43
TEMPERATURE_MIN
#define TEMPERATURE_MIN
Definition driver_ch9121.c:47
SUPPLY_VOLTAGE_MIN
#define SUPPLY_VOLTAGE_MIN
Definition driver_ch9121.c:44
CH9121_CMD_PORT1_SET_DST_IP
#define CH9121_CMD_PORT1_SET_DST_IP
Definition driver_ch9121.c:75
CH9121_CMD_PORT2_GET_TIMEOUT
#define CH9121_CMD_PORT2_GET_TIMEOUT
Definition driver_ch9121.c:101
CH9121_CMD_RUN_AND_RESET
#define CH9121_CMD_RUN_AND_RESET
Definition driver_ch9121.c:57
CH9121_CMD_PORT1_SET_PORT
#define CH9121_CMD_PORT1_SET_PORT
Definition driver_ch9121.c:74
CHIP_NAME
#define CHIP_NAME
chip information definition
Definition driver_ch9121.c:42
CH9121_CMD_PORT1_SET_CONFIG
#define CH9121_CMD_PORT1_SET_CONFIG
Definition driver_ch9121.c:78
CH9121_CMD_PORT2_LEN
#define CH9121_CMD_PORT2_LEN
Definition driver_ch9121.c:112
CH9121_CMD_PORT1_DOMAIN
#define CH9121_CMD_PORT1_DOMAIN
Definition driver_ch9121.c:109
DRIVER_VERSION
#define DRIVER_VERSION
Definition driver_ch9121.c:49
CH9121_CMD_PORT2_FLUSH
#define CH9121_CMD_PORT2_FLUSH
Definition driver_ch9121.c:113
CH9121_CMD_PORT1_GET_BAUD
#define CH9121_CMD_PORT1_GET_BAUD
Definition driver_ch9121.c:84
CH9121_CMD_DISCONNECT
#define CH9121_CMD_DISCONNECT
Definition driver_ch9121.c:67
CH9121_CMD_PORT2_SET_TIMEOUT
#define CH9121_CMD_PORT2_SET_TIMEOUT
Definition driver_ch9121.c:94
CH9121_CMD_PORT2_GET_PORT
#define CH9121_CMD_PORT2_GET_PORT
Definition driver_ch9121.c:96
CH9121_CMD_PORT1_GET_DST_PORT
#define CH9121_CMD_PORT1_GET_DST_PORT
Definition driver_ch9121.c:83
driver_ch9121.h
driver ch9121 header file
ch9121_parity_t
ch9121_parity_t
ch9121 parity enumeration definition
Definition driver_ch9121.h:108
ch9121_bool_t
ch9121_bool_t
ch9121 bool enumeration definition
Definition driver_ch9121.h:79
ch9121_get_ip
uint8_t ch9121_get_ip(ch9121_handle_t *handle, uint8_t ip[4])
get ip address
Definition driver_ch9121.c:707
ch9121_init
uint8_t ch9121_init(ch9121_handle_t *handle)
initialize the chip
Definition driver_ch9121.c:1724
ch9121_mode_t
ch9121_mode_t
ch9121 mode enumeration definition
Definition driver_ch9121.h:97
ch9121_set_uart_baud
uint8_t ch9121_set_uart_baud(ch9121_handle_t *handle, ch9121_port_t port, uint32_t baud)
set uart baud
Definition driver_ch9121.c:1151
ch9121_set_dhcp
uint8_t ch9121_set_dhcp(ch9121_handle_t *handle, ch9121_bool_t enable)
enable or disable dhcp
Definition driver_ch9121.c:469
ch9121_info
uint8_t ch9121_info(ch9121_info_t *info)
get chip's information
Definition driver_ch9121.c:2032
ch9121_set_ip
uint8_t ch9121_set_ip(ch9121_handle_t *handle, uint8_t ip[4])
set ip address
Definition driver_ch9121.c:669
ch9121_get_gateway
uint8_t ch9121_get_gateway(ch9121_handle_t *handle, uint8_t ip[4])
get gateway
Definition driver_ch9121.c:851
ch9121_config_and_reset
uint8_t ch9121_config_and_reset(ch9121_handle_t *handle)
config and reset the chip
Definition driver_ch9121.c:401
ch9121_set_disconnect_with_no_rj45
uint8_t ch9121_set_disconnect_with_no_rj45(ch9121_handle_t *handle, ch9121_bool_t enable)
enable or disable disconnect with no rj45
Definition driver_ch9121.c:1645
ch9121_set_uart_flush
uint8_t ch9121_set_uart_flush(ch9121_handle_t *handle, ch9121_port_t port, ch9121_bool_t enable)
enable or disable uart auto flush
Definition driver_ch9121.c:1568
ch9121_deinit
uint8_t ch9121_deinit(ch9121_handle_t *handle)
close the chip
Definition driver_ch9121.c:1866
ch9121_read
uint8_t ch9121_read(ch9121_handle_t *handle, uint8_t *buf, uint16_t *len)
read data
Definition driver_ch9121.c:1959
ch9121_reset
uint8_t ch9121_reset(ch9121_handle_t *handle)
reset the chip
Definition driver_ch9121.c:334
ch9121_set_source_port_random
uint8_t ch9121_set_source_port_random(ch9121_handle_t *handle, ch9121_port_t port, ch9121_bool_t enable)
enable or disable random source port number
Definition driver_ch9121.c:1479
ch9121_info_t
struct ch9121_info_s ch9121_info_t
ch9121 information structure definition
ch9121_set_mode
uint8_t ch9121_set_mode(ch9121_handle_t *handle, ch9121_port_t port, ch9121_mode_t mode)
set mode
Definition driver_ch9121.c:583
ch9121_get_uart_timeout
uint8_t ch9121_get_uart_timeout(ch9121_handle_t *handle, ch9121_port_t port, uint8_t *timeout)
get uart timeout
Definition driver_ch9121.c:1383
ch9121_uart_timeout_convert_to_data
uint8_t ch9121_uart_timeout_convert_to_data(ch9121_handle_t *handle, uint8_t reg, uint16_t *ms)
convert the register raw data to the offset
Definition driver_ch9121.c:1451
ch9121_handle_t
struct ch9121_handle_s ch9121_handle_t
ch9121 handle structure definition
ch9121_set_dest_ip
uint8_t ch9121_set_dest_ip(ch9121_handle_t *handle, ch9121_port_t port, uint8_t ip[4])
set dest ip
Definition driver_ch9121.c:974
ch9121_get_dest_port
uint8_t ch9121_get_dest_port(ch9121_handle_t *handle, ch9121_port_t port, uint16_t *num)
get dest port
Definition driver_ch9121.c:1107
ch9121_save_to_eeprom
uint8_t ch9121_save_to_eeprom(ch9121_handle_t *handle)
save to eeprom
Definition driver_ch9121.c:368
ch9121_get_subnet_mask
uint8_t ch9121_get_subnet_mask(ch9121_handle_t *handle, uint8_t mask[4])
get subnet mask
Definition driver_ch9121.c:779
ch9121_set_uart_config
uint8_t ch9121_set_uart_config(ch9121_handle_t *handle, ch9121_port_t port, uint8_t data_bit, ch9121_parity_t parity, uint8_t stop_bit)
set uart config
Definition driver_ch9121.c:1244
ch9121_status_t
ch9121_status_t
ch9121 status enumeration definition
Definition driver_ch9121.h:88
ch9121_get_dest_ip
uint8_t ch9121_get_dest_ip(ch9121_handle_t *handle, ch9121_port_t port, uint8_t ip[4])
get dest ip
Definition driver_ch9121.c:1020
ch9121_get_uart_config
uint8_t ch9121_get_uart_config(ch9121_handle_t *handle, ch9121_port_t port, uint8_t *data_bit, ch9121_parity_t *parity, uint8_t *stop_bit)
get uart config
Definition driver_ch9121.c:1291
ch9121_port_t
ch9121_port_t
ch9121 port enumeration definition
Definition driver_ch9121.h:70
ch9121_uart_timeout_convert_to_register
uint8_t ch9121_uart_timeout_convert_to_register(ch9121_handle_t *handle, uint16_t ms, uint8_t *reg)
convert the uart timeout to the register raw data
Definition driver_ch9121.c:1424
ch9121_set_subnet_mask
uint8_t ch9121_set_subnet_mask(ch9121_handle_t *handle, uint8_t mask[4])
set subnet mask
Definition driver_ch9121.c:741
ch9121_set_domain
uint8_t ch9121_set_domain(ch9121_handle_t *handle, char *domain)
set chip domain
Definition driver_ch9121.c:1680
ch9121_get_uart_baud
uint8_t ch9121_get_uart_baud(ch9121_handle_t *handle, ch9121_port_t port, uint32_t *baud)
get uart baud
Definition driver_ch9121.c:1197
ch9121_set_uart_timeout
uint8_t ch9121_set_uart_timeout(ch9121_handle_t *handle, ch9121_port_t port, uint8_t timeout)
set uart timeout
Definition driver_ch9121.c:1337
ch9121_set_gateway
uint8_t ch9121_set_gateway(ch9121_handle_t *handle, uint8_t ip[4])
set gateway
Definition driver_ch9121.c:813
ch9121_set_source_port
uint8_t ch9121_set_source_port(ch9121_handle_t *handle, ch9121_port_t port, uint16_t num)
set source port
Definition driver_ch9121.c:886
ch9121_set_port2
uint8_t ch9121_set_port2(ch9121_handle_t *handle, ch9121_bool_t enable)
enable or disable uart port2
Definition driver_ch9121.c:1610
ch9121_get_version
uint8_t ch9121_get_version(ch9121_handle_t *handle, uint8_t *version)
get version
Definition driver_ch9121.c:301
ch9121_set_dest_port
uint8_t ch9121_set_dest_port(ch9121_handle_t *handle, ch9121_port_t port, uint16_t num)
set dest port
Definition driver_ch9121.c:1063
ch9121_exit
uint8_t ch9121_exit(ch9121_handle_t *handle)
exit
Definition driver_ch9121.c:435
ch9121_get_mode
uint8_t ch9121_get_mode(ch9121_handle_t *handle, ch9121_port_t port, ch9121_mode_t *mode)
get mode
Definition driver_ch9121.c:626
ch9121_get_status
uint8_t ch9121_get_status(ch9121_handle_t *handle, ch9121_port_t port, ch9121_status_t *status)
get status
Definition driver_ch9121.c:539
ch9121_get_source_port
uint8_t ch9121_get_source_port(ch9121_handle_t *handle, ch9121_port_t port, uint16_t *num)
get source port
Definition driver_ch9121.c:930
ch9121_set_uart_buffer_length
uint8_t ch9121_set_uart_buffer_length(ch9121_handle_t *handle, ch9121_port_t port, uint32_t len)
set uart buffer length
Definition driver_ch9121.c:1522
ch9121_get_mac
uint8_t ch9121_get_mac(ch9121_handle_t *handle, uint8_t mac[6])
get chip mac
Definition driver_ch9121.c:504
CH9121_UART_PRE_DELAY
#define CH9121_UART_PRE_DELAY
ch9121 uart pre delay definition
Definition driver_ch9121.h:63
ch9121_write
uint8_t ch9121_write(ch9121_handle_t *handle, uint8_t *buf, uint16_t len)
write data
Definition driver_ch9121.c:1920
CH9121_PORT1
@ CH9121_PORT1
Definition driver_ch9121.h:71
ch9121_set_command
uint8_t ch9121_set_command(ch9121_handle_t *handle, uint8_t *param, uint16_t len, uint8_t *out, uint16_t out_len, uint16_t pre_delay, uint16_t timeout)
set command
Definition driver_ch9121.c:2000
ch9121_handle_s::uart_flush
uint8_t(* uart_flush)(void)
Definition driver_ch9121.h:124
ch9121_handle_s::inited
uint8_t inited
Definition driver_ch9121.h:134
ch9121_handle_s::cfg_gpio_write
uint8_t(* cfg_gpio_write)(uint8_t data)
Definition driver_ch9121.h:131
ch9121_handle_s::uart_write
uint8_t(* uart_write)(uint8_t *buf, uint16_t len)
Definition driver_ch9121.h:125
ch9121_handle_s::delay_ms
void(* delay_ms)(uint32_t ms)
Definition driver_ch9121.h:132
ch9121_handle_s::cfg_gpio_init
uint8_t(* cfg_gpio_init)(void)
Definition driver_ch9121.h:129
ch9121_handle_s::uart_deinit
uint8_t(* uart_deinit)(void)
Definition driver_ch9121.h:122
ch9121_handle_s::reset_gpio_deinit
uint8_t(* reset_gpio_deinit)(void)
Definition driver_ch9121.h:127
ch9121_handle_s::debug_print
void(* debug_print)(const char *const fmt,...)
Definition driver_ch9121.h:133
ch9121_handle_s::uart_read
uint16_t(* uart_read)(uint8_t *buf, uint16_t len)
Definition driver_ch9121.h:123
ch9121_handle_s::reset_gpio_init
uint8_t(* reset_gpio_init)(void)
Definition driver_ch9121.h:126
ch9121_handle_s::buf
uint8_t buf[128]
Definition driver_ch9121.h:135
ch9121_handle_s::uart_init
uint8_t(* uart_init)(void)
Definition driver_ch9121.h:121
ch9121_handle_s::reset_gpio_write
uint8_t(* reset_gpio_write)(uint8_t data)
Definition driver_ch9121.h:128
ch9121_handle_s::cfg_gpio_deinit
uint8_t(* cfg_gpio_deinit)(void)
Definition driver_ch9121.h:130
ch9121_info_s::temperature_max
float temperature_max
Definition driver_ch9121.h:150
ch9121_info_s::supply_voltage_max_v
float supply_voltage_max_v
Definition driver_ch9121.h:147
ch9121_info_s::driver_version
uint32_t driver_version
Definition driver_ch9121.h:151
ch9121_info_s::temperature_min
float temperature_min
Definition driver_ch9121.h:149
ch9121_info_s::max_current_ma
float max_current_ma
Definition driver_ch9121.h:148
ch9121_info_s::manufacturer_name
char manufacturer_name[32]
Definition driver_ch9121.h:144
ch9121_info_s::supply_voltage_min_v
float supply_voltage_min_v
Definition driver_ch9121.h:146
ch9121_info_s::interface
char interface[8]
Definition driver_ch9121.h:145
ch9121_info_s::chip_name
char chip_name[32]
Definition driver_ch9121.h:143