driver ch9121 header file More...

#include <stdio.h>
#include <stdint.h>
#include <string.h>

Include dependency graph for driver_ch9121.h:

This graph shows which files directly or indirectly include this file:

Data Structures
struct	ch9121_handle_s
	ch9121 handle structure definition More...
struct	ch9121_info_s
	ch9121 information structure definition More...

Macros
#define	CH9121_UART_PRE_DELAY 50
	ch9121 uart pre delay definition
#define	DRIVER_CH9121_LINK_INIT(HANDLE, STRUCTURE)
	initialize ch9121 structure
#define	DRIVER_CH9121_LINK_UART_INIT(HANDLE, FUC)
	link uart_init function
#define	DRIVER_CH9121_LINK_UART_DEINIT(HANDLE, FUC)
	link uart_deinit function
#define	DRIVER_CH9121_LINK_UART_READ(HANDLE, FUC)
	link uart_read function
#define	DRIVER_CH9121_LINK_UART_WRITE(HANDLE, FUC)
	link uart_write function
#define	DRIVER_CH9121_LINK_UART_FLUSH(HANDLE, FUC)
	link uart_flush function
#define	DRIVER_CH9121_LINK_RESET_GPIO_INIT(HANDLE, FUC)
	link reset_gpio_init function
#define	DRIVER_CH9121_LINK_RESET_GPIO_DEINIT(HANDLE, FUC)
	link reset_gpio_deinit function
#define	DRIVER_CH9121_LINK_RESET_GPIO_WRITE(HANDLE, FUC)
	link reset_gpio_write function
#define	DRIVER_CH9121_LINK_CFG_GPIO_INIT(HANDLE, FUC)
	link cfg_gpio_init function
#define	DRIVER_CH9121_LINK_CFG_GPIO_DEINIT(HANDLE, FUC)
	link cfg_gpio_deinit function
#define	DRIVER_CH9121_LINK_CFG_GPIO_WRITE(HANDLE, FUC)
	link cfg_gpio_write function
#define	DRIVER_CH9121_LINK_DELAY_MS(HANDLE, FUC)
	link delay_ms function
#define	DRIVER_CH9121_LINK_DEBUG_PRINT(HANDLE, FUC)
	link debug_print function

Typedefs
typedef struct ch9121_handle_s	ch9121_handle_t
	ch9121 handle structure definition
typedef struct ch9121_info_s	ch9121_info_t
	ch9121 information structure definition

Enumerations
enum	ch9121_port_t { CH9121_PORT1 = 0x00 , CH9121_PORT2 = 0x01 }
	ch9121 port enumeration definition More...
enum	ch9121_bool_t { CH9121_BOOL_FALSE = 0x00 , CH9121_BOOL_TRUE = 0x01 }
	ch9121 bool enumeration definition More...
enum	ch9121_status_t { CH9121_STATUS_DISCONNECT = 0x00 , CH9121_STATUS_CONNECT = 0x01 }
	ch9121 status enumeration definition More...
enum	ch9121_mode_t { CH9121_MODE_TCP_SERVER = 0x00 , CH9121_MODE_TCP_CLIENT = 0x01 , CH9121_MODE_UDP_SERVER = 0x02 , CH9121_MODE_UDP_CLIENT = 0x03 }
	ch9121 mode enumeration definition More...
enum	ch9121_parity_t { CH9121_PARITY_EVEN = 0x00 , CH9121_PARITY_ODD = 0x01 , CH9121_PARITY_MARK = 0x02 , CH9121_PARITY_SPACE = 0x03 , CH9121_PARITY_NONE = 0x04 }
	ch9121 parity enumeration definition More...

Functions
uint8_t	ch9121_info (ch9121_info_t *info)
	get chip's information
uint8_t	ch9121_init (ch9121_handle_t *handle)
	initialize the chip
uint8_t	ch9121_deinit (ch9121_handle_t *handle)
	close the chip
uint8_t	ch9121_read (ch9121_handle_t handle, uint8_t buf, uint16_t *len)
	read data
uint8_t	ch9121_write (ch9121_handle_t handle, uint8_t buf, uint16_t len)
	write data
uint8_t	ch9121_get_version (ch9121_handle_t handle, uint8_t version)
	get version
uint8_t	ch9121_reset (ch9121_handle_t *handle)
	reset the chip
uint8_t	ch9121_save_to_eeprom (ch9121_handle_t *handle)
	save to eeprom
uint8_t	ch9121_config_and_reset (ch9121_handle_t *handle)
	config and reset the chip
uint8_t	ch9121_exit (ch9121_handle_t *handle)
	exit
uint8_t	ch9121_set_dhcp (ch9121_handle_t *handle, ch9121_bool_t enable)
	enable or disable dhcp
uint8_t	ch9121_get_mac (ch9121_handle_t *handle, uint8_t mac[6])
	get chip mac
uint8_t	ch9121_set_ip (ch9121_handle_t *handle, uint8_t ip[4])
	set ip address
uint8_t	ch9121_get_ip (ch9121_handle_t *handle, uint8_t ip[4])
	get ip address
uint8_t	ch9121_set_subnet_mask (ch9121_handle_t *handle, uint8_t mask[4])
	set subnet mask
uint8_t	ch9121_get_subnet_mask (ch9121_handle_t *handle, uint8_t mask[4])
	get subnet mask
uint8_t	ch9121_set_gateway (ch9121_handle_t *handle, uint8_t ip[4])
	set gateway
uint8_t	ch9121_get_gateway (ch9121_handle_t *handle, uint8_t ip[4])
	get gateway
uint8_t	ch9121_get_status (ch9121_handle_t handle, ch9121_port_t port, ch9121_status_t status)
	get status
uint8_t	ch9121_set_mode (ch9121_handle_t *handle, ch9121_port_t port, ch9121_mode_t mode)
	set mode
uint8_t	ch9121_get_mode (ch9121_handle_t handle, ch9121_port_t port, ch9121_mode_t mode)
	get mode
uint8_t	ch9121_set_source_port (ch9121_handle_t *handle, ch9121_port_t port, uint16_t num)
	set source port
uint8_t	ch9121_get_source_port (ch9121_handle_t handle, ch9121_port_t port, uint16_t num)
	get source port
uint8_t	ch9121_set_dest_ip (ch9121_handle_t *handle, ch9121_port_t port, uint8_t ip[4])
	set dest ip
uint8_t	ch9121_get_dest_ip (ch9121_handle_t *handle, ch9121_port_t port, uint8_t ip[4])
	get dest ip
uint8_t	ch9121_set_dest_port (ch9121_handle_t *handle, ch9121_port_t port, uint16_t num)
	set dest port
uint8_t	ch9121_get_dest_port (ch9121_handle_t handle, ch9121_port_t port, uint16_t num)
	get dest port
uint8_t	ch9121_set_uart_baud (ch9121_handle_t *handle, ch9121_port_t port, uint32_t baud)
	set uart baud
uint8_t	ch9121_get_uart_baud (ch9121_handle_t handle, ch9121_port_t port, uint32_t baud)
	get uart baud
uint8_t	ch9121_set_uart_config (ch9121_handle_t *handle, ch9121_port_t port, uint8_t data_bit, ch9121_parity_t parity, uint8_t stop_bit)
	set uart config
uint8_t	ch9121_get_uart_config (ch9121_handle_t handle, ch9121_port_t port, uint8_t data_bit, ch9121_parity_t parity, uint8_t stop_bit)
	get uart config
uint8_t	ch9121_set_uart_timeout (ch9121_handle_t *handle, ch9121_port_t port, uint8_t timeout)
	set uart timeout
uint8_t	ch9121_get_uart_timeout (ch9121_handle_t handle, ch9121_port_t port, uint8_t timeout)
	get uart timeout
uint8_t	ch9121_uart_timeout_convert_to_register (ch9121_handle_t handle, uint16_t ms, uint8_t reg)
	convert the uart timeout to the register raw data
uint8_t	ch9121_uart_timeout_convert_to_data (ch9121_handle_t handle, uint8_t reg, uint16_t ms)
	convert the register raw data to the offset
uint8_t	ch9121_set_source_port_random (ch9121_handle_t *handle, ch9121_port_t port, ch9121_bool_t enable)
	enable or disable random source port number
uint8_t	ch9121_set_uart_buffer_length (ch9121_handle_t *handle, ch9121_port_t port, uint32_t len)
	set uart buffer length
uint8_t	ch9121_set_uart_flush (ch9121_handle_t *handle, ch9121_port_t port, ch9121_bool_t enable)
	enable or disable uart auto flush
uint8_t	ch9121_set_port2 (ch9121_handle_t *handle, ch9121_bool_t enable)
	enable or disable uart port2
uint8_t	ch9121_set_disconnect_with_no_rj45 (ch9121_handle_t *handle, ch9121_bool_t enable)
	enable or disable disconnect with no rj45
uint8_t	ch9121_set_domain (ch9121_handle_t handle, char domain)
	set chip domain
uint8_t	ch9121_set_command (ch9121_handle_t handle, uint8_t param, uint16_t len, uint8_t *out, uint16_t out_len, uint16_t pre_delay, uint16_t timeout)
	set command

Detailed Description

driver ch9121 header file

The MIT License (MIT)

Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:

The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

Version: 1.0.0

Author: Shifeng Li

Date: 2023-04-15

history

Date	Version	Author	Description
2023/04/15	1.0	Shifeng Li	first upload

Definition in file driver_ch9121.h.

Data Structures

Macros

Typedefs

Enumerations

Functions

Detailed Description

history