96 uint8_t ip[4], uint16_t port,
97 uint8_t mask[4], uint8_t gateway[4],
98 uint8_t dest_ip[4], uint16_t dest_port)
driver ch9121 basic header file
uint8_t ch9121_init(ch9121_handle_t *handle)
initialize the chip
ch9121_mode_t
ch9121 mode enumeration definition
uint8_t ch9121_set_uart_baud(ch9121_handle_t *handle, ch9121_port_t port, uint32_t baud)
set uart baud
uint8_t ch9121_set_dhcp(ch9121_handle_t *handle, ch9121_bool_t enable)
enable or disable dhcp
uint8_t ch9121_set_ip(ch9121_handle_t *handle, uint8_t ip[4])
set ip address
uint8_t ch9121_config_and_reset(ch9121_handle_t *handle)
config and reset the chip
uint8_t ch9121_set_disconnect_with_no_rj45(ch9121_handle_t *handle, ch9121_bool_t enable)
enable or disable disconnect with no rj45
uint8_t ch9121_set_uart_flush(ch9121_handle_t *handle, ch9121_port_t port, ch9121_bool_t enable)
enable or disable uart auto flush
uint8_t ch9121_deinit(ch9121_handle_t *handle)
close the chip
uint8_t ch9121_read(ch9121_handle_t *handle, uint8_t *buf, uint16_t *len)
read data
uint8_t ch9121_set_source_port_random(ch9121_handle_t *handle, ch9121_port_t port, ch9121_bool_t enable)
enable or disable random source port number
uint8_t ch9121_set_mode(ch9121_handle_t *handle, ch9121_port_t port, ch9121_mode_t mode)
set mode
struct ch9121_handle_s ch9121_handle_t
ch9121 handle structure definition
uint8_t ch9121_set_dest_ip(ch9121_handle_t *handle, ch9121_port_t port, uint8_t ip[4])
set dest ip
uint8_t ch9121_save_to_eeprom(ch9121_handle_t *handle)
save to eeprom
uint8_t ch9121_set_uart_config(ch9121_handle_t *handle, ch9121_port_t port, uint8_t data_bit, ch9121_parity_t parity, uint8_t stop_bit)
set uart config
ch9121_port_t
ch9121 port enumeration definition
uint8_t ch9121_uart_timeout_convert_to_register(ch9121_handle_t *handle, uint16_t ms, uint8_t *reg)
convert the uart timeout to the register raw data
uint8_t ch9121_set_subnet_mask(ch9121_handle_t *handle, uint8_t mask[4])
set subnet mask
uint8_t ch9121_set_uart_timeout(ch9121_handle_t *handle, ch9121_port_t port, uint8_t timeout)
set uart timeout
uint8_t ch9121_set_gateway(ch9121_handle_t *handle, uint8_t ip[4])
set gateway
uint8_t ch9121_set_source_port(ch9121_handle_t *handle, ch9121_port_t port, uint16_t num)
set source port
uint8_t ch9121_set_port2(ch9121_handle_t *handle, ch9121_bool_t enable)
enable or disable uart port2
uint8_t ch9121_set_dest_port(ch9121_handle_t *handle, ch9121_port_t port, uint16_t num)
set dest port
uint8_t ch9121_set_uart_buffer_length(ch9121_handle_t *handle, ch9121_port_t port, uint32_t len)
set uart buffer length
uint8_t ch9121_write(ch9121_handle_t *handle, uint8_t *buf, uint16_t len)
write data
#define CH9121_BASIC_DEFAULT_UART_SOURCE_PORT_RANDOM
#define CH9121_BASIC_DEFAULT_UART_FLUSH
#define CH9121_BASIC_DEFAULT_UART_TIMEOUT
uint8_t ch9121_basic_read(uint8_t *buf, uint16_t *len)
basic example read data
#define CH9121_BASIC_DEFAULT_UART_PORT2
#define CH9121_BASIC_DEFAULT_UART_BUFFER_LENGTH
#define CH9121_BASIC_DEFAULT_UART_PORT
uint8_t ch9121_basic_deinit(void)
basic example deinit
uint8_t ch9121_basic_config(ch9121_port_t uart_port, ch9121_mode_t mode, uint8_t ip[4], uint16_t port, uint8_t mask[4], uint8_t gateway[4], uint8_t dest_ip[4], uint16_t dest_port)
basic example config
#define CH9121_BASIC_DEFAULT_UART_PARITY
uint8_t ch9121_basic_init(void)
basic example init
#define CH9121_BASIC_DEFAULT_UART_STOP_BIT
#define CH9121_BASIC_DEFAULT_DHCP
ch9121 basic example default definition
#define CH9121_BASIC_DEFAULT_UART_DATA_BIT
uint8_t ch9121_basic_write(uint8_t *buf, uint16_t len)
basic example write data
#define CH9121_BASIC_DEFAULT_DISCONNECT_WITH_NO_RJ45
uint8_t ch9121_interface_cfg_gpio_deinit(void)
interface cfg gpio deinit
void ch9121_interface_delay_ms(uint32_t ms)
interface delay ms
uint8_t ch9121_interface_cfg_gpio_write(uint8_t data)
interface cfg gpio write
uint16_t ch9121_interface_uart_read(uint8_t *buf, uint16_t len)
interface uart read
uint8_t ch9121_interface_uart_deinit(void)
interface uart deinit
uint8_t ch9121_interface_uart_flush(void)
interface uart flush
uint8_t ch9121_interface_uart_write(uint8_t *buf, uint16_t len)
interface uart write
uint8_t ch9121_interface_uart_init(void)
interface uart init
void ch9121_interface_debug_print(const char *const fmt,...)
interface print format data
uint8_t ch9121_interface_cfg_gpio_init(void)
interface cfg gpio init
uint8_t ch9121_interface_reset_gpio_init(void)
interface reset gpio init
uint8_t ch9121_interface_reset_gpio_write(uint8_t data)
interface reset gpio write
uint8_t ch9121_interface_reset_gpio_deinit(void)
interface reset gpio deinit
#define DRIVER_CH9121_LINK_RESET_GPIO_WRITE(HANDLE, FUC)
link reset_gpio_write function
#define DRIVER_CH9121_LINK_DEBUG_PRINT(HANDLE, FUC)
link debug_print function
#define DRIVER_CH9121_LINK_INIT(HANDLE, STRUCTURE)
initialize ch9121 structure
#define DRIVER_CH9121_LINK_RESET_GPIO_INIT(HANDLE, FUC)
link reset_gpio_init function
#define DRIVER_CH9121_LINK_UART_DEINIT(HANDLE, FUC)
link uart_deinit function
#define DRIVER_CH9121_LINK_UART_WRITE(HANDLE, FUC)
link uart_write function
#define DRIVER_CH9121_LINK_UART_INIT(HANDLE, FUC)
link uart_init function
#define DRIVER_CH9121_LINK_CFG_GPIO_WRITE(HANDLE, FUC)
link cfg_gpio_write function
#define DRIVER_CH9121_LINK_DELAY_MS(HANDLE, FUC)
link delay_ms function
#define DRIVER_CH9121_LINK_UART_READ(HANDLE, FUC)
link uart_read function
#define DRIVER_CH9121_LINK_RESET_GPIO_DEINIT(HANDLE, FUC)
link reset_gpio_deinit function
#define DRIVER_CH9121_LINK_CFG_GPIO_DEINIT(HANDLE, FUC)
link cfg_gpio_deinit function
#define DRIVER_CH9121_LINK_UART_FLUSH(HANDLE, FUC)
link uart_flush function
#define DRIVER_CH9121_LINK_CFG_GPIO_INIT(HANDLE, FUC)
link cfg_gpio_init function