LibDriver CH9121
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driver_ch9121_net_test.c
Go to the documentation of this file.
1
36
38
39static ch9121_handle_t gs_handle;
40
50uint8_t ch9121_net_test(ch9121_mode_t mode, uint32_t timeout)
51{
52 uint8_t res;
53 uint8_t reg;
54 uint8_t ip[4] = CH9121_NET_TEST_IP;
55 uint8_t dst_ip[4] = CH9121_NET_TEST_DST_IP;
56 uint8_t mask[4] = CH9121_NET_TEST_MASK;
57 uint8_t gateway[4] = CH9121_NET_TEST_GATEWAY;
58 char str[] = "LibDriver";
59 ch9121_info_t info;
60
61 /* link interface function */
76
77 /* get ch9121 information */
78 res = ch9121_info(&info);
79 if (res != 0)
80 {
81 ch9121_interface_debug_print("ch9121: get info failed.\n");
82
83 return 1;
84 }
85 else
86 {
87 /* print chip information */
88 ch9121_interface_debug_print("ch9121: chip is %s.\n", info.chip_name);
89 ch9121_interface_debug_print("ch9121: manufacturer is %s.\n", info.manufacturer_name);
90 ch9121_interface_debug_print("ch9121: interface is %s.\n", info.interface);
91 ch9121_interface_debug_print("ch9121: driver version is %d.%d.\n", info.driver_version / 1000, (info.driver_version % 1000) / 100);
92 ch9121_interface_debug_print("ch9121: min supply voltage is %0.1fV.\n", info.supply_voltage_min_v);
93 ch9121_interface_debug_print("ch9121: max supply voltage is %0.1fV.\n", info.supply_voltage_max_v);
94 ch9121_interface_debug_print("ch9121: max current is %0.2fmA.\n", info.max_current_ma);
95 ch9121_interface_debug_print("ch9121: max temperature is %0.1fC.\n", info.temperature_max);
96 ch9121_interface_debug_print("ch9121: min temperature is %0.1fC.\n", info.temperature_min);
97 }
98
99 /* start net test */
100 ch9121_interface_debug_print("ch9121: start net test.\n");
101
102 /* ch9121 init */
103 res = ch9121_init(&gs_handle);
104 if (res != 0)
105 {
106 ch9121_interface_debug_print("ch9121: init failed.\n");
107
108 return 1;
109 }
110
111 /* disable dhcp */
112 res = ch9121_set_dhcp(&gs_handle, CH9121_BOOL_FALSE);
113 if (res != 0)
114 {
115 ch9121_interface_debug_print("ch9121: set dhcp failed.\n");
116 (void)ch9121_deinit(&gs_handle);
117
118 return 1;
119 }
120
121 /* set ip */
122 res = ch9121_set_ip(&gs_handle, ip);
123 if (res != 0)
124 {
125 ch9121_interface_debug_print("ch9121: set ip failed.\n");
126 (void)ch9121_deinit(&gs_handle);
127
128 return 1;
129 }
130
131 /* set subnet mask */
132 res = ch9121_set_subnet_mask(&gs_handle, mask);
133 if (res != 0)
134 {
135 ch9121_interface_debug_print("ch9121: set subnet mask failed.\n");
136 (void)ch9121_deinit(&gs_handle);
137
138 return 1;
139 }
140
141 /* set gateway */
142 res = ch9121_set_gateway(&gs_handle, gateway);
143 if (res != 0)
144 {
145 ch9121_interface_debug_print("ch9121: set gateway failed.\n");
146 (void)ch9121_deinit(&gs_handle);
147
148 return 1;
149 }
150
151 /* set source port */
153 if (res != 0)
154 {
155 ch9121_interface_debug_print("ch9121: set source port failed.\n");
156 (void)ch9121_deinit(&gs_handle);
157
158 return 1;
159 }
160
161 /* set dest ip */
162 res = ch9121_set_dest_ip(&gs_handle, CH9121_PORT1, dst_ip);
163 if (res != 0)
164 {
165 ch9121_interface_debug_print("ch9121: set dest ip failed.\n");
166 (void)ch9121_deinit(&gs_handle);
167
168 return 1;
169 }
170
171 /* set dest port */
173 if (res != 0)
174 {
175 ch9121_interface_debug_print("ch9121: set dest port failed.\n");
176 (void)ch9121_deinit(&gs_handle);
177
178 return 1;
179 }
180
181 /* set 9600 */
182 res = ch9121_set_uart_baud(&gs_handle, CH9121_PORT1, 9600);
183 if (res != 0)
184 {
185 ch9121_interface_debug_print("ch9121: set uart baud failed.\n");
186 (void)ch9121_deinit(&gs_handle);
187
188 return 1;
189 }
190
191 /* set uart 8 data bit, parity none, 1 stop bit */
193 if (res != 0)
194 {
195 ch9121_interface_debug_print("ch9121: set uart config failed.\n");
196 (void)ch9121_deinit(&gs_handle);
197
198 return 1;
199 }
200
201 /* 10ms */
202 res = ch9121_uart_timeout_convert_to_register(&gs_handle, 10, &reg);
203 if (res != 0)
204 {
205 ch9121_interface_debug_print("ch9121: uart timeout convert to register failed.\n");
206 (void)ch9121_deinit(&gs_handle);
207
208 return 1;
209 }
210
211 /* set uart timeout */
212 res = ch9121_set_uart_timeout(&gs_handle, CH9121_PORT1, reg);
213 if (res != 0)
214 {
215 ch9121_interface_debug_print("ch9121: set uart timeout failed.\n");
216 (void)ch9121_deinit(&gs_handle);
217
218 return 1;
219 }
220
221 /* disable source port random */
223 if (res != 0)
224 {
225 ch9121_interface_debug_print("ch9121: set source port random failed.\n");
226 (void)ch9121_deinit(&gs_handle);
227
228 return 1;
229 }
230
231 /* set uart buffer length */
232 res = ch9121_set_uart_buffer_length(&gs_handle, CH9121_PORT1, 1024);
233 if (res != 0)
234 {
235 ch9121_interface_debug_print("ch9121: set uart buffer length failed.\n");
236 (void)ch9121_deinit(&gs_handle);
237
238 return 1;
239 }
240
241 /* false uart flush */
243 if (res != 0)
244 {
245 ch9121_interface_debug_print("ch9121: set uart flush failed.\n");
246 (void)ch9121_deinit(&gs_handle);
247
248 return 1;
249 }
250
251 /* disable port2 */
252 res = ch9121_set_port2(&gs_handle, CH9121_BOOL_FALSE);
253 if (res != 0)
254 {
255 ch9121_interface_debug_print("ch9121: set port2 failed.\n");
256 (void)ch9121_deinit(&gs_handle);
257
258 return 1;
259 }
260
261 /* enable disconnect with no rj45 */
263 if (res != 0)
264 {
265 ch9121_interface_debug_print("ch9121: set disconnect with no rj45 failed.\n");
266 (void)ch9121_deinit(&gs_handle);
267
268 return 1;
269 }
270
271 /* set mode */
272 res = ch9121_set_mode(&gs_handle, CH9121_PORT1, mode);
273 if (res != 0)
274 {
275 ch9121_interface_debug_print("ch9121: set mode failed.\n");
276 (void)ch9121_deinit(&gs_handle);
277
278 return 1;
279 }
280
281 /* save to eeprom */
282 res = ch9121_save_to_eeprom(&gs_handle);
283 if (res != 0)
284 {
285 ch9121_interface_debug_print("ch9121: save to eeprom failed.\n");
286 (void)ch9121_deinit(&gs_handle);
287
288 return 1;
289 }
290
291 /* config and reset */
292 res = ch9121_config_and_reset(&gs_handle);
293 if (res != 0)
294 {
295 ch9121_interface_debug_print("ch9121: config and reset failed.\n");
296 (void)ch9121_deinit(&gs_handle);
297
298 return 1;
299 }
300
301 /* tcp server */
302 if (mode == CH9121_MODE_TCP_SERVER)
303 {
304 uint8_t ip_tmp[4];
305 uint16_t num;
306 uint32_t t = timeout;
307
308 /* get ip */
309 res = ch9121_get_ip(&gs_handle, ip_tmp);
310 if (res != 0)
311 {
312 ch9121_interface_debug_print("ch9121: get ip failed.\n");
313 (void)ch9121_deinit(&gs_handle);
314
315 return 1;
316 }
317
318 /* get source port */
319 res = ch9121_get_source_port(&gs_handle, CH9121_PORT1, &num);
320 if (res != 0)
321 {
322 ch9121_interface_debug_print("ch9121: get source port failed.\n");
323 (void)ch9121_deinit(&gs_handle);
324
325 return 1;
326 }
327
328 /* output */
329 ch9121_interface_debug_print("ch9121: tcp server src port %d, src ip %d.%d.%d.%d.\n", num, ip_tmp[0], ip_tmp[1], ip_tmp[2], ip_tmp[3]);
330
331 /* loop */
332 while (t != 0)
333 {
334 uint8_t buf[16];
335 uint16_t l;
336
337 /* init */
338 memset(buf, 0, sizeof(uint8_t) * 16);
339 l = 16;
340
341 /* read data */
342 res = ch9121_read(&gs_handle, buf, &l);
343 if (res != 0)
344 {
345 ch9121_interface_debug_print("ch9121: read failed.\n");
346 (void)ch9121_deinit(&gs_handle);
347
348 return 1;
349 }
350
351 if (l != 0)
352 {
353 /* output */
354 ch9121_interface_debug_print("ch9121: read %s.\n", buf);
355
356 break;
357 }
358
359 /* delay 1ms */
361 t--;
362 }
363
364 /* check timeout */
365 if (t == 0)
366 {
367 ch9121_interface_debug_print("ch9121: timeout.\n");
368 (void)ch9121_deinit(&gs_handle);
369
370 return 1;
371 }
372 }
373 /* tcp client */
374 else if (mode == CH9121_MODE_TCP_CLIENT)
375 {
376 uint8_t ip_tmp[4];
377 uint16_t num;
378
379 /* get ip */
380 res = ch9121_get_dest_ip(&gs_handle, CH9121_PORT1, ip_tmp);
381 if (res != 0)
382 {
383 ch9121_interface_debug_print("ch9121: get ip failed.\n");
384 (void)ch9121_deinit(&gs_handle);
385
386 return 1;
387 }
388
389 /* get dest port */
390 res = ch9121_get_dest_port(&gs_handle, CH9121_PORT1, &num);
391 if (res != 0)
392 {
393 ch9121_interface_debug_print("ch9121: get dest port failed.\n");
394 (void)ch9121_deinit(&gs_handle);
395
396 return 1;
397 }
398
399 /* output */
400 ch9121_interface_debug_print("ch9121: tcp client dest port %d, dest ip %d.%d.%d.%d.\n", num, ip_tmp[0], ip_tmp[1], ip_tmp[2], ip_tmp[3]);
401
402 /* write data */
403 res = ch9121_write(&gs_handle, (uint8_t *)str, (uint16_t)strlen(str));
404 if (res != 0)
405 {
406 ch9121_interface_debug_print("ch9121: write failed.\n");
407 (void)ch9121_deinit(&gs_handle);
408
409 return 1;
410 }
411
412 /* output */
413 ch9121_interface_debug_print("ch9121: write %s.\n", str);
414 }
415 /* udp server */
416 else if (mode == CH9121_MODE_UDP_SERVER)
417 {
418 uint8_t ip_tmp[4];
419 uint16_t num;
420 uint32_t t = timeout;
421
422 /* get ip */
423 res = ch9121_get_ip(&gs_handle, ip_tmp);
424 if (res != 0)
425 {
426 ch9121_interface_debug_print("ch9121: get ip failed.\n");
427 (void)ch9121_deinit(&gs_handle);
428
429 return 1;
430 }
431
432 /* get source port */
433 res = ch9121_get_source_port(&gs_handle, CH9121_PORT1, &num);
434 if (res != 0)
435 {
436 ch9121_interface_debug_print("ch9121: get source port failed.\n");
437 (void)ch9121_deinit(&gs_handle);
438
439 return 1;
440 }
441
442 /* output */
443 ch9121_interface_debug_print("ch9121: udp server src port %d, src ip %d.%d.%d.%d.\n", num, ip_tmp[0], ip_tmp[1], ip_tmp[2], ip_tmp[3]);
444
445 /* loop */
446 while (t != 0)
447 {
448 uint8_t buf[16];
449 uint16_t l;
450
451 /* init */
452 memset(buf, 0, sizeof(uint8_t) * 16);
453 l = 16;
454
455 /* read data */
456 res = ch9121_read(&gs_handle, buf, &l);
457 if (res != 0)
458 {
459 ch9121_interface_debug_print("ch9121: read failed.\n");
460 (void)ch9121_deinit(&gs_handle);
461
462 return 1;
463 }
464
465 if (l != 0)
466 {
467 /* output */
468 ch9121_interface_debug_print("ch9121: read %s.\n", buf);
469
470 break;
471 }
472
473 /* delay 1ms */
475 t--;
476 }
477
478 /* check timeout */
479 if (t == 0)
480 {
481 ch9121_interface_debug_print("ch9121: timeout.\n");
482 (void)ch9121_deinit(&gs_handle);
483
484 return 1;
485 }
486 }
487 /* udp client */
488 else
489 {
490 uint8_t ip_tmp[4];
491 uint16_t i;
492 uint16_t num;
493
494 /* get ip */
495 res = ch9121_get_dest_ip(&gs_handle, CH9121_PORT1, ip_tmp);
496 if (res != 0)
497 {
498 ch9121_interface_debug_print("ch9121: get ip failed.\n");
499 (void)ch9121_deinit(&gs_handle);
500
501 return 1;
502 }
503
504 /* get dest port */
505 res = ch9121_get_dest_port(&gs_handle, CH9121_PORT1, &num);
506 if (res != 0)
507 {
508 ch9121_interface_debug_print("ch9121: get dest port failed.\n");
509 (void)ch9121_deinit(&gs_handle);
510
511 return 1;
512 }
513
514 /* output */
515 ch9121_interface_debug_print("ch9121: udp client dest port %d, dest ip %d.%d.%d.%d.\n", num, ip_tmp[0], ip_tmp[1], ip_tmp[2], ip_tmp[3]);
516
517 /* run 10 times */
518 for (i = 0; i < 10; i++)
519 {
520 /* write data */
521 res = ch9121_write(&gs_handle, (uint8_t *)str, (uint16_t)strlen(str));
522 if (res != 0)
523 {
524 ch9121_interface_debug_print("ch9121: write failed.\n");
525 (void)ch9121_deinit(&gs_handle);
526
527 return 1;
528 }
529
530 /* output */
531 ch9121_interface_debug_print("ch9121: write %s.\n", str);
532
533 /* delay 1000ms */
535 }
536 }
537
538 /* finish net test */
539 ch9121_interface_debug_print("ch9121: finish net test.\n");
540
541 return 0;
542}
driver ch9121 net test header file
uint8_t ch9121_get_ip(ch9121_handle_t *handle, uint8_t ip[4])
get ip address
uint8_t ch9121_init(ch9121_handle_t *handle)
initialize the chip
ch9121_mode_t
ch9121 mode enumeration definition
uint8_t ch9121_set_uart_baud(ch9121_handle_t *handle, ch9121_port_t port, uint32_t baud)
set uart baud
uint8_t ch9121_set_dhcp(ch9121_handle_t *handle, ch9121_bool_t enable)
enable or disable dhcp
uint8_t ch9121_info(ch9121_info_t *info)
get chip's information
uint8_t ch9121_set_ip(ch9121_handle_t *handle, uint8_t ip[4])
set ip address
uint8_t ch9121_config_and_reset(ch9121_handle_t *handle)
config and reset the chip
uint8_t ch9121_set_disconnect_with_no_rj45(ch9121_handle_t *handle, ch9121_bool_t enable)
enable or disable disconnect with no rj45
uint8_t ch9121_set_uart_flush(ch9121_handle_t *handle, ch9121_port_t port, ch9121_bool_t enable)
enable or disable uart auto flush
uint8_t ch9121_deinit(ch9121_handle_t *handle)
close the chip
uint8_t ch9121_read(ch9121_handle_t *handle, uint8_t *buf, uint16_t *len)
read data
uint8_t ch9121_set_source_port_random(ch9121_handle_t *handle, ch9121_port_t port, ch9121_bool_t enable)
enable or disable random source port number
struct ch9121_info_s ch9121_info_t
ch9121 information structure definition
uint8_t ch9121_set_mode(ch9121_handle_t *handle, ch9121_port_t port, ch9121_mode_t mode)
set mode
struct ch9121_handle_s ch9121_handle_t
ch9121 handle structure definition
uint8_t ch9121_set_dest_ip(ch9121_handle_t *handle, ch9121_port_t port, uint8_t ip[4])
set dest ip
uint8_t ch9121_get_dest_port(ch9121_handle_t *handle, ch9121_port_t port, uint16_t *num)
get dest port
uint8_t ch9121_save_to_eeprom(ch9121_handle_t *handle)
save to eeprom
uint8_t ch9121_set_uart_config(ch9121_handle_t *handle, ch9121_port_t port, uint8_t data_bit, ch9121_parity_t parity, uint8_t stop_bit)
set uart config
uint8_t ch9121_get_dest_ip(ch9121_handle_t *handle, ch9121_port_t port, uint8_t ip[4])
get dest ip
uint8_t ch9121_uart_timeout_convert_to_register(ch9121_handle_t *handle, uint16_t ms, uint8_t *reg)
convert the uart timeout to the register raw data
uint8_t ch9121_set_subnet_mask(ch9121_handle_t *handle, uint8_t mask[4])
set subnet mask
uint8_t ch9121_set_uart_timeout(ch9121_handle_t *handle, ch9121_port_t port, uint8_t timeout)
set uart timeout
uint8_t ch9121_set_gateway(ch9121_handle_t *handle, uint8_t ip[4])
set gateway
uint8_t ch9121_set_source_port(ch9121_handle_t *handle, ch9121_port_t port, uint16_t num)
set source port
uint8_t ch9121_set_port2(ch9121_handle_t *handle, ch9121_bool_t enable)
enable or disable uart port2
uint8_t ch9121_set_dest_port(ch9121_handle_t *handle, ch9121_port_t port, uint16_t num)
set dest port
uint8_t ch9121_get_source_port(ch9121_handle_t *handle, ch9121_port_t port, uint16_t *num)
get source port
uint8_t ch9121_set_uart_buffer_length(ch9121_handle_t *handle, ch9121_port_t port, uint32_t len)
set uart buffer length
uint8_t ch9121_write(ch9121_handle_t *handle, uint8_t *buf, uint16_t len)
write data
@ CH9121_PARITY_NONE
@ CH9121_BOOL_FALSE
@ CH9121_BOOL_TRUE
@ CH9121_MODE_UDP_SERVER
@ CH9121_MODE_TCP_SERVER
@ CH9121_MODE_TCP_CLIENT
@ CH9121_PORT1
uint8_t ch9121_interface_cfg_gpio_deinit(void)
interface cfg gpio deinit
void ch9121_interface_delay_ms(uint32_t ms)
interface delay ms
uint8_t ch9121_interface_cfg_gpio_write(uint8_t data)
interface cfg gpio write
uint16_t ch9121_interface_uart_read(uint8_t *buf, uint16_t len)
interface uart read
uint8_t ch9121_interface_uart_deinit(void)
interface uart deinit
uint8_t ch9121_interface_uart_flush(void)
interface uart flush
uint8_t ch9121_interface_uart_write(uint8_t *buf, uint16_t len)
interface uart write
uint8_t ch9121_interface_uart_init(void)
interface uart init
void ch9121_interface_debug_print(const char *const fmt,...)
interface print format data
uint8_t ch9121_interface_cfg_gpio_init(void)
interface cfg gpio init
uint8_t ch9121_interface_reset_gpio_init(void)
interface reset gpio init
uint8_t ch9121_interface_reset_gpio_write(uint8_t data)
interface reset gpio write
uint8_t ch9121_interface_reset_gpio_deinit(void)
interface reset gpio deinit
#define CH9121_NET_TEST_GATEWAY
ch9121 net test gateway definition
uint8_t ch9121_net_test(ch9121_mode_t mode, uint32_t timeout)
net test
#define CH9121_NET_TEST_IP
ch9121 net test ip definition
#define CH9121_NET_TEST_PORT
ch9121 net test port definition
#define CH9121_NET_TEST_DST_PORT
ch9121 net test dest port definition
#define CH9121_NET_TEST_MASK
ch9121 net test subnet mask definition
#define CH9121_NET_TEST_DST_IP
ch9121 net test dest ip definition
float supply_voltage_max_v
uint32_t driver_version
char manufacturer_name[32]
float supply_voltage_min_v
char chip_name[32]