LibDriver CH9121
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driver_ch9121_register_test.c
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1
36
37#include "driver_ch9121_register_test.h"
38#include <stdlib.h>
39
40static ch9121_handle_t gs_handle;
41
49uint8_t ch9121_register_test(void)
50{
51 uint8_t res;
52 uint8_t version;
53 uint8_t timeout;
54 uint8_t timeout_check;
55 uint8_t mac[6];
56 uint8_t ip[4];
57 uint8_t ip_check[4];
58 uint8_t mask[4];
59 uint8_t mask_check[4];
60 uint16_t num;
61 uint16_t num_check;
62 uint32_t baud;
63 uint32_t baud_check;
64 uint32_t len;
65 uint8_t data_bit;
66 uint8_t stop_bit;
67 uint16_t ms;
68 uint16_t ms_check;
69 uint8_t reg;
70 ch9121_parity_t parity;
71 ch9121_info_t info;
72 ch9121_status_t status;
73 ch9121_mode_t mode;
74 char domain[] = "www.ch9121.com";
75
76 /* link interface function */
77 DRIVER_CH9121_LINK_INIT(&gs_handle, ch9121_handle_t);
78 DRIVER_CH9121_LINK_UART_INIT(&gs_handle, ch9121_interface_uart_init);
79 DRIVER_CH9121_LINK_UART_DEINIT(&gs_handle, ch9121_interface_uart_deinit);
80 DRIVER_CH9121_LINK_UART_READ(&gs_handle, ch9121_interface_uart_read);
81 DRIVER_CH9121_LINK_UART_WRITE(&gs_handle, ch9121_interface_uart_write);
82 DRIVER_CH9121_LINK_UART_FLUSH(&gs_handle, ch9121_interface_uart_flush);
83 DRIVER_CH9121_LINK_RESET_GPIO_INIT(&gs_handle, ch9121_interface_reset_gpio_init);
84 DRIVER_CH9121_LINK_RESET_GPIO_DEINIT(&gs_handle, ch9121_interface_reset_gpio_deinit);
85 DRIVER_CH9121_LINK_RESET_GPIO_WRITE(&gs_handle, ch9121_interface_reset_gpio_write);
86 DRIVER_CH9121_LINK_CFG_GPIO_INIT(&gs_handle, ch9121_interface_cfg_gpio_init);
87 DRIVER_CH9121_LINK_CFG_GPIO_DEINIT(&gs_handle, ch9121_interface_cfg_gpio_deinit);
88 DRIVER_CH9121_LINK_CFG_GPIO_WRITE(&gs_handle, ch9121_interface_cfg_gpio_write);
89 DRIVER_CH9121_LINK_DELAY_MS(&gs_handle, ch9121_interface_delay_ms);
90 DRIVER_CH9121_LINK_DEBUG_PRINT(&gs_handle, ch9121_interface_debug_print);
91
92 /* get ch9121 information */
93 res = ch9121_info(&info);
94 if (res != 0)
95 {
96 ch9121_interface_debug_print("ch9121: get info failed.\n");
97
98 return 1;
99 }
100 else
101 {
102 /* print chip information */
103 ch9121_interface_debug_print("ch9121: chip is %s.\n", info.chip_name);
104 ch9121_interface_debug_print("ch9121: manufacturer is %s.\n", info.manufacturer_name);
105 ch9121_interface_debug_print("ch9121: interface is %s.\n", info.interface);
106 ch9121_interface_debug_print("ch9121: driver version is %d.%d.\n", info.driver_version / 1000, (info.driver_version % 1000) / 100);
107 ch9121_interface_debug_print("ch9121: min supply voltage is %0.1fV.\n", info.supply_voltage_min_v);
108 ch9121_interface_debug_print("ch9121: max supply voltage is %0.1fV.\n", info.supply_voltage_max_v);
109 ch9121_interface_debug_print("ch9121: max current is %0.2fmA.\n", info.max_current_ma);
110 ch9121_interface_debug_print("ch9121: max temperature is %0.1fC.\n", info.temperature_max);
111 ch9121_interface_debug_print("ch9121: min temperature is %0.1fC.\n", info.temperature_min);
112 }
113
114 /* start register test */
115 ch9121_interface_debug_print("ch9121: start register test.\n");
116
117 /* ch9121 init */
118 res = ch9121_init(&gs_handle);
119 if (res != 0)
120 {
121 ch9121_interface_debug_print("ch9121: init failed.\n");
122
123 return 1;
124 }
125
126 /* ch9121_get_version test */
127 ch9121_interface_debug_print("ch9121: ch9121_get_version test.\n");
128
129 /* get version */
130 res = ch9121_get_version(&gs_handle, &version);
131 if (res != 0)
132 {
133 ch9121_interface_debug_print("ch9121: get version failed.\n");
134 (void)ch9121_deinit(&gs_handle);
135
136 return 1;
137 }
138
139 /* output */
140 ch9121_interface_debug_print("ch9121: version is 0x%02X.\n", version);
141
142 /* ch9121_save_to_eeprom test */
143 ch9121_interface_debug_print("ch9121: ch9121_save_to_eeprom test.\n");
144
145 /* save to eeprom */
146 res = ch9121_save_to_eeprom(&gs_handle);
147 if (res != 0)
148 {
149 ch9121_interface_debug_print("ch9121: save to eeprom failed.\n");
150 (void)ch9121_deinit(&gs_handle);
151
152 return 1;
153 }
154
155 /* output */
156 ch9121_interface_debug_print("ch9121: check save to eeprom %s.\n", res == 0 ? "ok" : "error");
157
158 /* ch9121_exit test */
159 ch9121_interface_debug_print("ch9121: ch9121_exit test.\n");
160
161 /* exit */
162 res = ch9121_exit(&gs_handle);
163 if (res != 0)
164 {
165 ch9121_interface_debug_print("ch9121: exit failed.\n");
166 (void)ch9121_deinit(&gs_handle);
167
168 return 1;
169 }
170
171 /* output */
172 ch9121_interface_debug_print("ch9121: check exit %s.\n", res == 0 ? "ok" : "error");
173
174 /* ch9121_set_port2 test */
175 ch9121_interface_debug_print("ch9121: ch9121_set_port2 test.\n");
176
177 /* disable port2 */
178 res = ch9121_set_port2(&gs_handle, CH9121_BOOL_FALSE);
179 if (res != 0)
180 {
181 ch9121_interface_debug_print("ch9121: set port2 failed.\n");
182 (void)ch9121_deinit(&gs_handle);
183
184 return 1;
185 }
186
187 /* disable port2 */
188 ch9121_interface_debug_print("ch9121: disable port2.\n");
189
190 /* output */
191 ch9121_interface_debug_print("ch9121: check port2 %s.\n", res == 0 ? "ok" : "error");
192
193 /* enable port2 */
194 res = ch9121_set_port2(&gs_handle, CH9121_BOOL_TRUE);
195 if (res != 0)
196 {
197 ch9121_interface_debug_print("ch9121: set port2 failed.\n");
198 (void)ch9121_deinit(&gs_handle);
199
200 return 1;
201 }
202
203 /* enable port2 */
204 ch9121_interface_debug_print("ch9121: enable port2.\n");
205
206 /* output */
207 ch9121_interface_debug_print("ch9121: check port2 %s.\n", res == 0 ? "ok" : "error");
208
209 /* ch9121_set_disconnect_with_no_rj45 test */
210 ch9121_interface_debug_print("ch9121: ch9121_set_disconnect_with_no_rj45 test.\n");
211
212 /* disable */
213 res = ch9121_set_disconnect_with_no_rj45(&gs_handle, CH9121_BOOL_FALSE);
214 if (res != 0)
215 {
216 ch9121_interface_debug_print("ch9121: set disconnect with no rj45 failed.\n");
217 (void)ch9121_deinit(&gs_handle);
218
219 return 1;
220 }
221
222 /* disable disconnect with no rj45 */
223 ch9121_interface_debug_print("ch9121: disable disconnect with no rj45.\n");
224
225 /* output */
226 ch9121_interface_debug_print("ch9121: check disconnect with no rj45 %s.\n", res == 0 ? "ok" : "error");
227
228 /* enable */
229 res = ch9121_set_disconnect_with_no_rj45(&gs_handle, CH9121_BOOL_TRUE);
230 if (res != 0)
231 {
232 ch9121_interface_debug_print("ch9121: set disconnect with no rj45 failed.\n");
233 (void)ch9121_deinit(&gs_handle);
234
235 return 1;
236 }
237
238 /* enable disconnect with no rj45 */
239 ch9121_interface_debug_print("ch9121: enable disconnect with no rj45.\n");
240
241 /* output */
242 ch9121_interface_debug_print("ch9121: check disconnect with no rj45 %s.\n", res == 0 ? "ok" : "error");
243
244 /* ch9121_set_domain test */
245 ch9121_interface_debug_print("ch9121: ch9121_set_domain test.\n");
246
247 /* set domain */
248 res = ch9121_set_domain(&gs_handle, domain);
249 if (res != 0)
250 {
251 ch9121_interface_debug_print("ch9121: set domain failed.\n");
252 (void)ch9121_deinit(&gs_handle);
253
254 return 1;
255 }
256
257 /* set domain */
258 ch9121_interface_debug_print("ch9121: set domain %s.\n", domain);
259
260 /* output */
261 ch9121_interface_debug_print("ch9121: check domain %s.\n", res == 0 ? "ok" : "error");
262
263 /* ch9121_set_dhcp test */
264 ch9121_interface_debug_print("ch9121: ch9121_set_dhcp test.\n");
265
266 /* disable dhcp */
267 res = ch9121_set_dhcp(&gs_handle, CH9121_BOOL_FALSE);
268 if (res != 0)
269 {
270 ch9121_interface_debug_print("ch9121: set dhcp failed.\n");
271 (void)ch9121_deinit(&gs_handle);
272
273 return 1;
274 }
275
276 /* disable dhcp */
277 ch9121_interface_debug_print("ch9121: disable dhcp.\n");
278
279 /* output */
280 ch9121_interface_debug_print("ch9121: check dhcp %s.\n", res == 0 ? "ok" : "error");
281
282 /* enable dhcp */
283 res = ch9121_set_dhcp(&gs_handle, CH9121_BOOL_TRUE);
284 if (res != 0)
285 {
286 ch9121_interface_debug_print("ch9121: set dhcp failed.\n");
287 (void)ch9121_deinit(&gs_handle);
288
289 return 1;
290 }
291
292 /* enable dhcp */
293 ch9121_interface_debug_print("ch9121: enable dhcp.\n");
294
295 /* output */
296 ch9121_interface_debug_print("ch9121: check dhcp %s.\n", res == 0 ? "ok" : "error");
297
298 /* ch9121_get_mac test */
299 ch9121_interface_debug_print("ch9121: ch9121_get_mac test.\n");
300
301 /* get mac */
302 res = ch9121_get_mac(&gs_handle, mac);
303 if (res != 0)
304 {
305 ch9121_interface_debug_print("ch9121: get mac failed.\n");
306 (void)ch9121_deinit(&gs_handle);
307
308 return 1;
309 }
310
311 /* output */
312 ch9121_interface_debug_print("ch9121: mac is 0x%02X 0x%02X 0x%02X 0x%02X 0x%02X 0x%02X.\n",
313 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
314
315 /* ch9121_set_ip/ch9121_get_ip test */
316 ch9121_interface_debug_print("ch9121: ch9121_set_ip/ch9121_get_ip test.\n");
317
318 /* random ip */
319 ip[0] = rand() % 0xFF;
320 ip[1] = rand() % 0xFF;
321 ip[2] = rand() % 0xFF;
322 ip[3] = rand() % 0xFF;
323
324 /* set ip */
325 res = ch9121_set_ip(&gs_handle, ip);
326 if (res != 0)
327 {
328 ch9121_interface_debug_print("ch9121: set ip failed.\n");
329 (void)ch9121_deinit(&gs_handle);
330
331 return 1;
332 }
333
334 /* output */
335 ch9121_interface_debug_print("ch9121: set ip %d.%d.%d.%d.\n",
336 ip[0], ip[1], ip[2], ip[3]);
337
338 /* get ip */
339 res = ch9121_get_ip(&gs_handle, ip_check);
340 if (res != 0)
341 {
342 ch9121_interface_debug_print("ch9121: get ip failed.\n");
343 (void)ch9121_deinit(&gs_handle);
344
345 return 1;
346 }
347
348 /* output */
349 ch9121_interface_debug_print("ch9121: check ip %s.\n", memcmp(ip, ip_check, 4) == 0 ? "ok" : "error");
350
351 /* ch9121_set_subnet_mask/ch9121_get_subnet_mask test */
352 ch9121_interface_debug_print("ch9121: ch9121_set_subnet_mask/ch9121_get_subnet_mask test.\n");
353
354 /* random mask */
355 mask[0] = rand() % 0xFF;
356 mask[1] = rand() % 0xFF;
357 mask[2] = rand() % 0xFF;
358 mask[3] = rand() % 0xFF;
359
360 /* set subnet mask */
361 res = ch9121_set_subnet_mask(&gs_handle, mask);
362 if (res != 0)
363 {
364 ch9121_interface_debug_print("ch9121: set subnet mask failed.\n");
365 (void)ch9121_deinit(&gs_handle);
366
367 return 1;
368 }
369
370 /* output */
371 ch9121_interface_debug_print("ch9121: set subnet mask %d.%d.%d.%d.\n",
372 mask[0], mask[1], mask[2], mask[3]);
373
374 /* get subnet mask */
375 res = ch9121_get_subnet_mask(&gs_handle, mask_check);
376 if (res != 0)
377 {
378 ch9121_interface_debug_print("ch9121: get subnet mask failed.\n");
379 (void)ch9121_deinit(&gs_handle);
380
381 return 1;
382 }
383
384 /* output */
385 ch9121_interface_debug_print("ch9121: check subnet mask %s.\n", memcmp(mask, mask_check, 4) == 0 ? "ok" : "error");
386
387 /* ch9121_set_gateway/ch9121_get_gateway test */
388 ch9121_interface_debug_print("ch9121: ch9121_set_gateway/ch9121_get_gateway test.\n");
389
390 /* random ip */
391 ip[0] = rand() % 0xFF;
392 ip[1] = rand() % 0xFF;
393 ip[2] = rand() % 0xFF;
394 ip[3] = rand() % 0xFF;
395
396 /* set gateway */
397 res = ch9121_set_gateway(&gs_handle, ip);
398 if (res != 0)
399 {
400 ch9121_interface_debug_print("ch9121: set gateway failed.\n");
401 (void)ch9121_deinit(&gs_handle);
402
403 return 1;
404 }
405
406 /* output */
407 ch9121_interface_debug_print("ch9121: set gateway %d.%d.%d.%d.\n",
408 ip[0], ip[1], ip[2], ip[3]);
409
410 /* get gateway */
411 res = ch9121_get_gateway(&gs_handle, ip_check);
412 if (res != 0)
413 {
414 ch9121_interface_debug_print("ch9121: get gateway failed.\n");
415 (void)ch9121_deinit(&gs_handle);
416
417 return 1;
418 }
419
420 /* output */
421 ch9121_interface_debug_print("ch9121: check gateway %s.\n", memcmp(ip, ip_check, 4) == 0 ? "ok" : "error");
422
423 /* ch9121_get_status test */
424 ch9121_interface_debug_print("ch9121: ch9121_get_status test.\n");
425
426 /* port1 */
427 res = ch9121_get_status(&gs_handle, CH9121_PORT1, &status);
428 if (res != 0)
429 {
430 ch9121_interface_debug_print("ch9121: get status failed.\n");
431 (void)ch9121_deinit(&gs_handle);
432
433 return 1;
434 }
435
436 /* output */
437 ch9121_interface_debug_print("ch9121: get port1 status %s.\n", status == CH9121_STATUS_CONNECT ? "connect" : "disconnect");
438
439 /* port2 */
440 res = ch9121_get_status(&gs_handle, CH9121_PORT2, &status);
441 if (res != 0)
442 {
443 ch9121_interface_debug_print("ch9121: get status failed.\n");
444 (void)ch9121_deinit(&gs_handle);
445
446 return 1;
447 }
448
449 /* output */
450 ch9121_interface_debug_print("ch9121: get port2 status %s.\n", status == CH9121_STATUS_CONNECT ? "connect" : "disconnect");
451
452 /* ch9121_set_mode/ch9121_get_mode test */
453 ch9121_interface_debug_print("ch9121: ch9121_set_mode/ch9121_get_mode test.\n");
454
455 /* tcp server */
456 res = ch9121_set_mode(&gs_handle, CH9121_PORT1, CH9121_MODE_TCP_SERVER);
457 if (res != 0)
458 {
459 ch9121_interface_debug_print("ch9121: set mode failed.\n");
460 (void)ch9121_deinit(&gs_handle);
461
462 return 1;
463 }
464
465 /* output */
466 ch9121_interface_debug_print("ch9121: set port1 tcp server mode.\n");
467
468 res = ch9121_get_mode(&gs_handle, CH9121_PORT1, &mode);
469 if (res != 0)
470 {
471 ch9121_interface_debug_print("ch9121: get mode failed.\n");
472 (void)ch9121_deinit(&gs_handle);
473
474 return 1;
475 }
476
477 /* output */
478 ch9121_interface_debug_print("ch9121: check mode %s.\n", mode == CH9121_MODE_TCP_SERVER ? "ok" : "error");
479
480 /* tcp client */
481 res = ch9121_set_mode(&gs_handle, CH9121_PORT1, CH9121_MODE_TCP_CLIENT);
482 if (res != 0)
483 {
484 ch9121_interface_debug_print("ch9121: set mode failed.\n");
485 (void)ch9121_deinit(&gs_handle);
486
487 return 1;
488 }
489
490 /* output */
491 ch9121_interface_debug_print("ch9121: set port1 tcp client mode.\n");
492
493 res = ch9121_get_mode(&gs_handle, CH9121_PORT1, &mode);
494 if (res != 0)
495 {
496 ch9121_interface_debug_print("ch9121: get mode failed.\n");
497 (void)ch9121_deinit(&gs_handle);
498
499 return 1;
500 }
501
502 /* output */
503 ch9121_interface_debug_print("ch9121: check mode %s.\n", mode == CH9121_MODE_TCP_CLIENT ? "ok" : "error");
504
505 /* udp server */
506 res = ch9121_set_mode(&gs_handle, CH9121_PORT1, CH9121_MODE_UDP_SERVER);
507 if (res != 0)
508 {
509 ch9121_interface_debug_print("ch9121: set mode failed.\n");
510 (void)ch9121_deinit(&gs_handle);
511
512 return 1;
513 }
514
515 /* output */
516 ch9121_interface_debug_print("ch9121: set port1 udp server mode.\n");
517
518 res = ch9121_get_mode(&gs_handle, CH9121_PORT1, &mode);
519 if (res != 0)
520 {
521 ch9121_interface_debug_print("ch9121: get mode failed.\n");
522 (void)ch9121_deinit(&gs_handle);
523
524 return 1;
525 }
526
527 /* output */
528 ch9121_interface_debug_print("ch9121: check mode %s.\n", mode == CH9121_MODE_UDP_SERVER ? "ok" : "error");
529
530 /* udp client */
531 res = ch9121_set_mode(&gs_handle, CH9121_PORT1, CH9121_MODE_UDP_CLIENT);
532 if (res != 0)
533 {
534 ch9121_interface_debug_print("ch9121: set mode failed.\n");
535 (void)ch9121_deinit(&gs_handle);
536
537 return 1;
538 }
539
540 /* output */
541 ch9121_interface_debug_print("ch9121: set port1 udp client mode.\n");
542
543 res = ch9121_get_mode(&gs_handle, CH9121_PORT1, &mode);
544 if (res != 0)
545 {
546 ch9121_interface_debug_print("ch9121: get mode failed.\n");
547 (void)ch9121_deinit(&gs_handle);
548
549 return 1;
550 }
551
552 /* output */
553 ch9121_interface_debug_print("ch9121: check mode %s.\n", mode == CH9121_MODE_UDP_CLIENT ? "ok" : "error");
554
555 /* tcp server */
556 res = ch9121_set_mode(&gs_handle, CH9121_PORT2, CH9121_MODE_TCP_SERVER);
557 if (res != 0)
558 {
559 ch9121_interface_debug_print("ch9121: set mode failed.\n");
560 (void)ch9121_deinit(&gs_handle);
561
562 return 1;
563 }
564
565 /* output */
566 ch9121_interface_debug_print("ch9121: set port2 tcp server mode.\n");
567
568 res = ch9121_get_mode(&gs_handle, CH9121_PORT2, &mode);
569 if (res != 0)
570 {
571 ch9121_interface_debug_print("ch9121: get mode failed.\n");
572 (void)ch9121_deinit(&gs_handle);
573
574 return 1;
575 }
576
577 /* output */
578 ch9121_interface_debug_print("ch9121: check mode %s.\n", mode == CH9121_MODE_TCP_SERVER ? "ok" : "error");
579
580 /* tcp client */
581 res = ch9121_set_mode(&gs_handle, CH9121_PORT2, CH9121_MODE_TCP_CLIENT);
582 if (res != 0)
583 {
584 ch9121_interface_debug_print("ch9121: set mode failed.\n");
585 (void)ch9121_deinit(&gs_handle);
586
587 return 1;
588 }
589
590 /* output */
591 ch9121_interface_debug_print("ch9121: set port2 tcp client mode.\n");
592
593 res = ch9121_get_mode(&gs_handle, CH9121_PORT2, &mode);
594 if (res != 0)
595 {
596 ch9121_interface_debug_print("ch9121: get mode failed.\n");
597 (void)ch9121_deinit(&gs_handle);
598
599 return 1;
600 }
601
602 /* output */
603 ch9121_interface_debug_print("ch9121: check mode %s.\n", mode == CH9121_MODE_TCP_CLIENT ? "ok" : "error");
604
605 /* udp server */
606 res = ch9121_set_mode(&gs_handle, CH9121_PORT2, CH9121_MODE_UDP_SERVER);
607 if (res != 0)
608 {
609 ch9121_interface_debug_print("ch9121: set mode failed.\n");
610 (void)ch9121_deinit(&gs_handle);
611
612 return 1;
613 }
614
615 /* output */
616 ch9121_interface_debug_print("ch9121: set port2 udp server mode.\n");
617
618 res = ch9121_get_mode(&gs_handle, CH9121_PORT2, &mode);
619 if (res != 0)
620 {
621 ch9121_interface_debug_print("ch9121: get mode failed.\n");
622 (void)ch9121_deinit(&gs_handle);
623
624 return 1;
625 }
626
627 /* output */
628 ch9121_interface_debug_print("ch9121: check mode %s.\n", mode == CH9121_MODE_UDP_SERVER ? "ok" : "error");
629
630 /* udp client */
631 res = ch9121_set_mode(&gs_handle, CH9121_PORT2, CH9121_MODE_UDP_CLIENT);
632 if (res != 0)
633 {
634 ch9121_interface_debug_print("ch9121: set mode failed.\n");
635 (void)ch9121_deinit(&gs_handle);
636
637 return 1;
638 }
639
640 /* output */
641 ch9121_interface_debug_print("ch9121: set port2 udp client mode.\n");
642
643 res = ch9121_get_mode(&gs_handle, CH9121_PORT2, &mode);
644 if (res != 0)
645 {
646 ch9121_interface_debug_print("ch9121: get mode failed.\n");
647 (void)ch9121_deinit(&gs_handle);
648
649 return 1;
650 }
651
652 /* output */
653 ch9121_interface_debug_print("ch9121: check mode %s.\n", mode == CH9121_MODE_UDP_CLIENT ? "ok" : "error");
654
655 /* ch9121_set_source_port/ch9121_get_source_port test */
656 ch9121_interface_debug_print("ch9121: ch9121_set_source_port/ch9121_get_source_port test.\n");
657
658 /* random */
659 num = rand() % 0xFFFFU;
660
661 /* port1 */
662 res = ch9121_set_source_port(&gs_handle, CH9121_PORT1, num);
663 if (res != 0)
664 {
665 ch9121_interface_debug_print("ch9121: set source port failed.\n");
666 (void)ch9121_deinit(&gs_handle);
667
668 return 1;
669 }
670
671 /* output */
672 ch9121_interface_debug_print("ch9121: set source port1 %d.\n", num);
673
674 /* get source port */
675 res = ch9121_get_source_port(&gs_handle, CH9121_PORT1, &num_check);
676 if (res != 0)
677 {
678 ch9121_interface_debug_print("ch9121: get source port failed.\n");
679 (void)ch9121_deinit(&gs_handle);
680
681 return 1;
682 }
683
684 /* output */
685 ch9121_interface_debug_print("ch9121: check source port %s.\n", num_check == num ? "ok" : "error");
686
687 /* random */
688 num = rand() % 0xFFFFU;
689
690 /* port2 */
691 res = ch9121_set_source_port(&gs_handle, CH9121_PORT2, num);
692 if (res != 0)
693 {
694 ch9121_interface_debug_print("ch9121: set source port failed.\n");
695 (void)ch9121_deinit(&gs_handle);
696
697 return 1;
698 }
699
700 /* output */
701 ch9121_interface_debug_print("ch9121: set source port2 %d.\n", num);
702
703 /* get source port */
704 res = ch9121_get_source_port(&gs_handle, CH9121_PORT2, &num_check);
705 if (res != 0)
706 {
707 ch9121_interface_debug_print("ch9121: get source port failed.\n");
708 (void)ch9121_deinit(&gs_handle);
709
710 return 1;
711 }
712
713 /* output */
714 ch9121_interface_debug_print("ch9121: check source port %s.\n", num_check == num ? "ok" : "error");
715
716 /* ch9121_set_dest_ip/ch9121_get_dest_ip test */
717 ch9121_interface_debug_print("ch9121: ch9121_set_dest_ip/ch9121_get_dest_ip test.\n");
718
719 /* random ip */
720 ip[0] = rand() % 0xFF;
721 ip[1] = rand() % 0xFF;
722 ip[2] = rand() % 0xFF;
723 ip[3] = rand() % 0xFF;
724
725 /* port1 */
726 res = ch9121_set_dest_ip(&gs_handle, CH9121_PORT1, ip);
727 if (res != 0)
728 {
729 ch9121_interface_debug_print("ch9121: set dest ip failed.\n");
730 (void)ch9121_deinit(&gs_handle);
731
732 return 1;
733 }
734
735 /* output */
736 ch9121_interface_debug_print("ch9121: set port1 dest ip %d.%d.%d.%d.\n", ip[0], ip[1], ip[2], ip[3]);
737
738 /* get dest ip */
739 res = ch9121_get_dest_ip(&gs_handle, CH9121_PORT1, ip_check);
740 if (res != 0)
741 {
742 ch9121_interface_debug_print("ch9121: get dest ip failed.\n");
743 (void)ch9121_deinit(&gs_handle);
744
745 return 1;
746 }
747
748 /* output */
749 ch9121_interface_debug_print("ch9121: check dest ip %s.\n", memcmp(ip, ip_check, 4) == 0 ? "ok" : "error");
750
751 /* random ip */
752 ip[0] = rand() % 0xFF;
753 ip[1] = rand() % 0xFF;
754 ip[2] = rand() % 0xFF;
755 ip[3] = rand() % 0xFF;
756
757 /* port2 */
758 res = ch9121_set_dest_ip(&gs_handle, CH9121_PORT2, ip);
759 if (res != 0)
760 {
761 ch9121_interface_debug_print("ch9121: set dest ip failed.\n");
762 (void)ch9121_deinit(&gs_handle);
763
764 return 1;
765 }
766
767 /* output */
768 ch9121_interface_debug_print("ch9121: set port2 dest ip %d.%d.%d.%d.\n", ip[0], ip[1], ip[2], ip[3]);
769
770 /* get dest ip */
771 res = ch9121_get_dest_ip(&gs_handle, CH9121_PORT2, ip_check);
772 if (res != 0)
773 {
774 ch9121_interface_debug_print("ch9121: get dest ip failed.\n");
775 (void)ch9121_deinit(&gs_handle);
776
777 return 1;
778 }
779
780 /* output */
781 ch9121_interface_debug_print("ch9121: check dest ip %s.\n", memcmp(ip, ip_check, 4) == 0 ? "ok" : "error");
782
783 /* ch9121_set_dest_port/ch9121_get_dest_port test */
784 ch9121_interface_debug_print("ch9121: ch9121_set_dest_port/ch9121_get_dest_port test.\n");
785
786 /* random */
787 num = rand() % 0xFFFFU;
788
789 /* port1 */
790 res = ch9121_set_dest_port(&gs_handle, CH9121_PORT1, num);
791 if (res != 0)
792 {
793 ch9121_interface_debug_print("ch9121: set dest port failed.\n");
794 (void)ch9121_deinit(&gs_handle);
795
796 return 1;
797 }
798
799 /* output */
800 ch9121_interface_debug_print("ch9121: set dest port1 %d.\n", num);
801
802 /* get dest port */
803 res = ch9121_get_dest_port(&gs_handle, CH9121_PORT1, &num_check);
804 if (res != 0)
805 {
806 ch9121_interface_debug_print("ch9121: get dest port failed.\n");
807 (void)ch9121_deinit(&gs_handle);
808
809 return 1;
810 }
811
812 /* output */
813 ch9121_interface_debug_print("ch9121: check dest port %s.\n", num_check == num ? "ok" : "error");
814
815 /* random */
816 num = rand() % 0xFFFFU;
817
818 /* port2 */
819 res = ch9121_set_dest_port(&gs_handle, CH9121_PORT2, num);
820 if (res != 0)
821 {
822 ch9121_interface_debug_print("ch9121: set dest port failed.\n");
823 (void)ch9121_deinit(&gs_handle);
824
825 return 1;
826 }
827
828 /* output */
829 ch9121_interface_debug_print("ch9121: set dest port2 %d.\n", num);
830
831 /* get dest port */
832 res = ch9121_get_dest_port(&gs_handle, CH9121_PORT2, &num_check);
833 if (res != 0)
834 {
835 ch9121_interface_debug_print("ch9121: get dest port failed.\n");
836 (void)ch9121_deinit(&gs_handle);
837
838 return 1;
839 }
840
841 /* output */
842 ch9121_interface_debug_print("ch9121: check dest port %s.\n", num_check == num ? "ok" : "error");
843
844 /* ch9121_set_uart_baud/ch9121_get_uart_baud test */
845 ch9121_interface_debug_print("ch9121: ch9121_set_uart_baud/ch9121_get_uart_baud test.\n");
846
847 /* 9600 */
848 baud = 9600;
849
850 /* port1 */
851 res = ch9121_set_uart_baud(&gs_handle, CH9121_PORT1, baud);
852 if (res != 0)
853 {
854 ch9121_interface_debug_print("ch9121: set uart baud failed.\n");
855 (void)ch9121_deinit(&gs_handle);
856
857 return 1;
858 }
859
860 /* output */
861 ch9121_interface_debug_print("ch9121: set port1 uart baud %d.\n", baud);
862
863 /* get uart baud */
864 res = ch9121_get_uart_baud(&gs_handle, CH9121_PORT1, &baud_check);
865 if (res != 0)
866 {
867 ch9121_interface_debug_print("ch9121: get uart baud failed.\n");
868 (void)ch9121_deinit(&gs_handle);
869
870 return 1;
871 }
872
873 /* output */
874 ch9121_interface_debug_print("ch9121: check uart baud %s.\n", baud_check == baud ? "ok" : "error");
875
876 /* 9600 */
877 baud = 9600;
878
879 /* port2 */
880 res = ch9121_set_uart_baud(&gs_handle, CH9121_PORT2, baud);
881 if (res != 0)
882 {
883 ch9121_interface_debug_print("ch9121: set uart baud failed.\n");
884 (void)ch9121_deinit(&gs_handle);
885
886 return 1;
887 }
888
889 /* output */
890 ch9121_interface_debug_print("ch9121: set port2 uart baud %d.\n", baud);
891
892 /* get uart baud */
893 res = ch9121_get_uart_baud(&gs_handle, CH9121_PORT2, &baud_check);
894 if (res != 0)
895 {
896 ch9121_interface_debug_print("ch9121: get uart baud failed.\n");
897 (void)ch9121_deinit(&gs_handle);
898
899 return 1;
900 }
901
902 /* output */
903 ch9121_interface_debug_print("ch9121: check uart baud %s.\n", baud_check == baud ? "ok" : "error");
904
905 /* ch9121_set_uart_config/ch9121_get_uart_config test */
906 ch9121_interface_debug_print("ch9121: ch9121_set_uart_config/ch9121_get_uart_config test.\n");
907
908 /* set uart config */
909 res = ch9121_set_uart_config(&gs_handle, CH9121_PORT1, 8, CH9121_PARITY_NONE, 1);
910 if (res != 0)
911 {
912 ch9121_interface_debug_print("ch9121: set uart config failed.\n");
913 (void)ch9121_deinit(&gs_handle);
914
915 return 1;
916 }
917
918 /* output */
919 ch9121_interface_debug_print("ch9121: set port1 data_bit 8, parity none, stop_bit 1.\n");
920
921 /* get uart config */
922 res = ch9121_get_uart_config(&gs_handle, CH9121_PORT1, &data_bit, &parity, &stop_bit);
923 if (res != 0)
924 {
925 ch9121_interface_debug_print("ch9121: get uart config failed.\n");
926 (void)ch9121_deinit(&gs_handle);
927
928 return 1;
929 }
930
931 /* output */
932 ch9121_interface_debug_print("ch9121: check uart data bit %s.\n", data_bit == 8 ? "ok" : "error");
933 ch9121_interface_debug_print("ch9121: check uart parity %s.\n", parity == CH9121_PARITY_NONE ? "ok" : "error");
934 ch9121_interface_debug_print("ch9121: check uart stop bit %s.\n", stop_bit == 1 ? "ok" : "error");
935
936 /* set uart config */
937 res = ch9121_set_uart_config(&gs_handle, CH9121_PORT2, 8, CH9121_PARITY_NONE, 1);
938 if (res != 0)
939 {
940 ch9121_interface_debug_print("ch9121: set uart config failed.\n");
941 (void)ch9121_deinit(&gs_handle);
942
943 return 1;
944 }
945
946 /* output */
947 ch9121_interface_debug_print("ch9121: set port2 data_bit 8, parity none, stop_bit 1.\n");
948
949 /* get uart config */
950 res = ch9121_get_uart_config(&gs_handle, CH9121_PORT2, &data_bit, &parity, &stop_bit);
951 if (res != 0)
952 {
953 ch9121_interface_debug_print("ch9121: get uart config failed.\n");
954 (void)ch9121_deinit(&gs_handle);
955
956 return 1;
957 }
958
959 /* output */
960 ch9121_interface_debug_print("ch9121: check uart data bit %s.\n", data_bit == 8 ? "ok" : "error");
961 ch9121_interface_debug_print("ch9121: check uart parity %s.\n", parity == CH9121_PARITY_NONE ? "ok" : "error");
962 ch9121_interface_debug_print("ch9121: check uart stop bit %s.\n", stop_bit == 1 ? "ok" : "error");
963
964 /* ch9121_set_uart_timeout/ch9121_get_uart_timeout test */
965 ch9121_interface_debug_print("ch9121: ch9121_set_uart_timeout/ch9121_get_uart_timeout test.\n");
966
967 /* random timeout */
968 timeout = rand() % 0xFF;
969
970 /* set uart timeout */
971 res = ch9121_set_uart_timeout(&gs_handle, CH9121_PORT1, timeout);
972 if (res != 0)
973 {
974 ch9121_interface_debug_print("ch9121: set uart timeout failed.\n");
975 (void)ch9121_deinit(&gs_handle);
976
977 return 1;
978 }
979
980 /* output */
981 ch9121_interface_debug_print("ch9121: set port1 uart timeout %d.\n", timeout);
982
983 /* get uart timeout */
984 res = ch9121_get_uart_timeout(&gs_handle, CH9121_PORT1, &timeout_check);
985 if (res != 0)
986 {
987 ch9121_interface_debug_print("ch9121: get uart timeout failed.\n");
988 (void)ch9121_deinit(&gs_handle);
989
990 return 1;
991 }
992
993 /* output */
994 ch9121_interface_debug_print("ch9121: check uart timeout %s.\n", timeout_check == timeout ? "ok" : "error");
995
996 /* random timeout */
997 timeout = rand() % 0xFF;
998
999 /* set uart timeout */
1000 res = ch9121_set_uart_timeout(&gs_handle, CH9121_PORT2, timeout);
1001 if (res != 0)
1002 {
1003 ch9121_interface_debug_print("ch9121: set uart timeout failed.\n");
1004 (void)ch9121_deinit(&gs_handle);
1005
1006 return 1;
1007 }
1008
1009 /* output */
1010 ch9121_interface_debug_print("ch9121: set port2 uart timeout %d.\n", timeout);
1011
1012 /* get uart timeout */
1013 res = ch9121_get_uart_timeout(&gs_handle, CH9121_PORT2, &timeout_check);
1014 if (res != 0)
1015 {
1016 ch9121_interface_debug_print("ch9121: get uart timeout failed.\n");
1017 (void)ch9121_deinit(&gs_handle);
1018
1019 return 1;
1020 }
1021
1022 /* output */
1023 ch9121_interface_debug_print("ch9121: check uart timeout %s.\n", timeout_check == timeout ? "ok" : "error");
1024
1025 /* ch9121_set_source_port_random test */
1026 ch9121_interface_debug_print("ch9121: ch9121_set_source_port_random test.\n");
1027
1028 /* port1 */
1029 res = ch9121_set_source_port_random(&gs_handle, CH9121_PORT1, CH9121_BOOL_TRUE);
1030 if (res != 0)
1031 {
1032 ch9121_interface_debug_print("ch9121: set source port random failed.\n");
1033 (void)ch9121_deinit(&gs_handle);
1034
1035 return 1;
1036 }
1037
1038 /* output */
1039 ch9121_interface_debug_print("ch9121: enable port1 source port random.\n");
1040
1041 /* output */
1042 ch9121_interface_debug_print("ch9121: check source port random %s.\n", res == 0 ? "ok" : "error");
1043
1044 /* port1 */
1045 res = ch9121_set_source_port_random(&gs_handle, CH9121_PORT1, CH9121_BOOL_FALSE);
1046 if (res != 0)
1047 {
1048 ch9121_interface_debug_print("ch9121: set source port random failed.\n");
1049 (void)ch9121_deinit(&gs_handle);
1050
1051 return 1;
1052 }
1053
1054 /* output */
1055 ch9121_interface_debug_print("ch9121: disable port1 source port random.\n");
1056
1057 /* output */
1058 ch9121_interface_debug_print("ch9121: check source port random %s.\n", res == 0 ? "ok" : "error");
1059
1060 /* port2 */
1061 res = ch9121_set_source_port_random(&gs_handle, CH9121_PORT2, CH9121_BOOL_TRUE);
1062 if (res != 0)
1063 {
1064 ch9121_interface_debug_print("ch9121: set source port random failed.\n");
1065 (void)ch9121_deinit(&gs_handle);
1066
1067 return 1;
1068 }
1069
1070 /* output */
1071 ch9121_interface_debug_print("ch9121: enable port2 source port random.\n");
1072
1073 /* output */
1074 ch9121_interface_debug_print("ch9121: check source port random %s.\n", res == 0 ? "ok" : "error");
1075
1076 /* port2 */
1077 res = ch9121_set_source_port_random(&gs_handle, CH9121_PORT2, CH9121_BOOL_FALSE);
1078 if (res != 0)
1079 {
1080 ch9121_interface_debug_print("ch9121: set source port random failed.\n");
1081 (void)ch9121_deinit(&gs_handle);
1082
1083 return 1;
1084 }
1085
1086 /* output */
1087 ch9121_interface_debug_print("ch9121: disable port2 source port random.\n");
1088
1089 /* output */
1090 ch9121_interface_debug_print("ch9121: check source port random %s.\n", res == 0 ? "ok" : "error");
1091
1092 /* ch9121_set_uart_buffer_length test */
1093 ch9121_interface_debug_print("ch9121: ch9121_set_uart_buffer_length test.\n");
1094
1095 /* random len */
1096 len = 128 + rand() % 50;
1097
1098 /* set_uart_buffer_length */
1099 res = ch9121_set_uart_buffer_length(&gs_handle, CH9121_PORT1, len);
1100 if (res != 0)
1101 {
1102 ch9121_interface_debug_print("ch9121: set uart buffer length failed.\n");
1103 (void)ch9121_deinit(&gs_handle);
1104
1105 return 1;
1106 }
1107
1108 /* output */
1109 ch9121_interface_debug_print("ch9121: set port1 uart buffer length %d.\n", len);
1110
1111 /* output */
1112 ch9121_interface_debug_print("ch9121: check uart buffer length %s.\n", res == 0 ? "ok" : "error");
1113
1114 /* random len */
1115 len = 128 + rand() % 50;
1116
1117 /* set_uart_buffer_length */
1118 res = ch9121_set_uart_buffer_length(&gs_handle, CH9121_PORT2, len);
1119 if (res != 0)
1120 {
1121 ch9121_interface_debug_print("ch9121: set uart buffer length failed.\n");
1122 (void)ch9121_deinit(&gs_handle);
1123
1124 return 1;
1125 }
1126
1127 /* output */
1128 ch9121_interface_debug_print("ch9121: set port2 uart buffer length %d.\n", len);
1129
1130 /* output */
1131 ch9121_interface_debug_print("ch9121: check uart buffer length %s.\n", res == 0 ? "ok" : "error");
1132
1133 /* ch9121_set_uart_flush test */
1134 ch9121_interface_debug_print("ch9121: ch9121_set_uart_flush test.\n");
1135
1136 /* enable uart flush */
1137 res = ch9121_set_uart_flush(&gs_handle, CH9121_PORT1, CH9121_BOOL_TRUE);
1138 if (res != 0)
1139 {
1140 ch9121_interface_debug_print("ch9121: set uart flush failed.\n");
1141 (void)ch9121_deinit(&gs_handle);
1142
1143 return 1;
1144 }
1145
1146 /* output */
1147 ch9121_interface_debug_print("ch9121: enable port1 uart flush.\n");
1148
1149 /* output */
1150 ch9121_interface_debug_print("ch9121: check uart flush %s.\n", res == 0 ? "ok" : "error");
1151
1152 /* enable uart flush */
1153 res = ch9121_set_uart_flush(&gs_handle, CH9121_PORT2, CH9121_BOOL_TRUE);
1154 if (res != 0)
1155 {
1156 ch9121_interface_debug_print("ch9121: set uart flush failed.\n");
1157 (void)ch9121_deinit(&gs_handle);
1158
1159 return 1;
1160 }
1161
1162 /* output */
1163 ch9121_interface_debug_print("ch9121: enable port2 uart flush.\n");
1164
1165 /* output */
1166 ch9121_interface_debug_print("ch9121: check uart flush %s.\n", res == 0 ? "ok" : "error");
1167
1168 /* ch9121_uart_timeout_convert_to_register/ch9121_uart_timeout_convert_to_data test */
1169 ch9121_interface_debug_print("ch9121: ch9121_uart_timeout_convert_to_register/ch9121_uart_timeout_convert_to_data test.\n");
1170
1171 /* random ms */
1172 ms = (rand() % 10) * 5;
1173
1174 /* uart timeout convert to register */
1175 res = ch9121_uart_timeout_convert_to_register(&gs_handle, ms, &reg);
1176 if (res != 0)
1177 {
1178 ch9121_interface_debug_print("ch9121: uart timeout convert to register failed.\n");
1179 (void)ch9121_deinit(&gs_handle);
1180
1181 return 1;
1182 }
1183
1184 /* output */
1185 ch9121_interface_debug_print("ch9121: uart timeout convert to register %d.\n", ms);
1186
1187 /* uart timeout convert to data */
1188 res = ch9121_uart_timeout_convert_to_data(&gs_handle, reg, &ms_check);
1189 if (res != 0)
1190 {
1191 ch9121_interface_debug_print("ch9121: uart timeout convert to data failed.\n");
1192 (void)ch9121_deinit(&gs_handle);
1193
1194 return 1;
1195 }
1196
1197 /* output */
1198 ch9121_interface_debug_print("ch9121: check uart timeout convert %s.\n", ms == ms_check ? "ok" : "error");
1199
1200 /* finish register test */
1201 ch9121_interface_debug_print("ch9121: finish register test.\n");
1202 (void)ch9121_deinit(&gs_handle);
1203
1204 return 0;
1205}
driver_ch9121_register_test.h
driver ch9121 register test header file
ch9121_parity_t
ch9121_parity_t
ch9121 parity enumeration definition
Definition driver_ch9121.h:108
ch9121_get_ip
uint8_t ch9121_get_ip(ch9121_handle_t *handle, uint8_t ip[4])
get ip address
Definition driver_ch9121.c:707
ch9121_init
uint8_t ch9121_init(ch9121_handle_t *handle)
initialize the chip
Definition driver_ch9121.c:1724
ch9121_mode_t
ch9121_mode_t
ch9121 mode enumeration definition
Definition driver_ch9121.h:97
ch9121_set_uart_baud
uint8_t ch9121_set_uart_baud(ch9121_handle_t *handle, ch9121_port_t port, uint32_t baud)
set uart baud
Definition driver_ch9121.c:1151
ch9121_set_dhcp
uint8_t ch9121_set_dhcp(ch9121_handle_t *handle, ch9121_bool_t enable)
enable or disable dhcp
Definition driver_ch9121.c:469
ch9121_info
uint8_t ch9121_info(ch9121_info_t *info)
get chip's information
Definition driver_ch9121.c:2032
ch9121_set_ip
uint8_t ch9121_set_ip(ch9121_handle_t *handle, uint8_t ip[4])
set ip address
Definition driver_ch9121.c:669
ch9121_get_gateway
uint8_t ch9121_get_gateway(ch9121_handle_t *handle, uint8_t ip[4])
get gateway
Definition driver_ch9121.c:851
ch9121_set_disconnect_with_no_rj45
uint8_t ch9121_set_disconnect_with_no_rj45(ch9121_handle_t *handle, ch9121_bool_t enable)
enable or disable disconnect with no rj45
Definition driver_ch9121.c:1645
ch9121_set_uart_flush
uint8_t ch9121_set_uart_flush(ch9121_handle_t *handle, ch9121_port_t port, ch9121_bool_t enable)
enable or disable uart auto flush
Definition driver_ch9121.c:1568
ch9121_deinit
uint8_t ch9121_deinit(ch9121_handle_t *handle)
close the chip
Definition driver_ch9121.c:1866
ch9121_set_source_port_random
uint8_t ch9121_set_source_port_random(ch9121_handle_t *handle, ch9121_port_t port, ch9121_bool_t enable)
enable or disable random source port number
Definition driver_ch9121.c:1479
ch9121_info_t
struct ch9121_info_s ch9121_info_t
ch9121 information structure definition
ch9121_set_mode
uint8_t ch9121_set_mode(ch9121_handle_t *handle, ch9121_port_t port, ch9121_mode_t mode)
set mode
Definition driver_ch9121.c:583
ch9121_get_uart_timeout
uint8_t ch9121_get_uart_timeout(ch9121_handle_t *handle, ch9121_port_t port, uint8_t *timeout)
get uart timeout
Definition driver_ch9121.c:1383
ch9121_uart_timeout_convert_to_data
uint8_t ch9121_uart_timeout_convert_to_data(ch9121_handle_t *handle, uint8_t reg, uint16_t *ms)
convert the register raw data to the offset
Definition driver_ch9121.c:1451
ch9121_handle_t
struct ch9121_handle_s ch9121_handle_t
ch9121 handle structure definition
ch9121_set_dest_ip
uint8_t ch9121_set_dest_ip(ch9121_handle_t *handle, ch9121_port_t port, uint8_t ip[4])
set dest ip
Definition driver_ch9121.c:974
ch9121_get_dest_port
uint8_t ch9121_get_dest_port(ch9121_handle_t *handle, ch9121_port_t port, uint16_t *num)
get dest port
Definition driver_ch9121.c:1107
ch9121_save_to_eeprom
uint8_t ch9121_save_to_eeprom(ch9121_handle_t *handle)
save to eeprom
Definition driver_ch9121.c:368
ch9121_get_subnet_mask
uint8_t ch9121_get_subnet_mask(ch9121_handle_t *handle, uint8_t mask[4])
get subnet mask
Definition driver_ch9121.c:779
ch9121_set_uart_config
uint8_t ch9121_set_uart_config(ch9121_handle_t *handle, ch9121_port_t port, uint8_t data_bit, ch9121_parity_t parity, uint8_t stop_bit)
set uart config
Definition driver_ch9121.c:1244
ch9121_status_t
ch9121_status_t
ch9121 status enumeration definition
Definition driver_ch9121.h:88
ch9121_get_dest_ip
uint8_t ch9121_get_dest_ip(ch9121_handle_t *handle, ch9121_port_t port, uint8_t ip[4])
get dest ip
Definition driver_ch9121.c:1020
ch9121_get_uart_config
uint8_t ch9121_get_uart_config(ch9121_handle_t *handle, ch9121_port_t port, uint8_t *data_bit, ch9121_parity_t *parity, uint8_t *stop_bit)
get uart config
Definition driver_ch9121.c:1291
ch9121_uart_timeout_convert_to_register
uint8_t ch9121_uart_timeout_convert_to_register(ch9121_handle_t *handle, uint16_t ms, uint8_t *reg)
convert the uart timeout to the register raw data
Definition driver_ch9121.c:1424
ch9121_set_subnet_mask
uint8_t ch9121_set_subnet_mask(ch9121_handle_t *handle, uint8_t mask[4])
set subnet mask
Definition driver_ch9121.c:741
ch9121_set_domain
uint8_t ch9121_set_domain(ch9121_handle_t *handle, char *domain)
set chip domain
Definition driver_ch9121.c:1680
ch9121_get_uart_baud
uint8_t ch9121_get_uart_baud(ch9121_handle_t *handle, ch9121_port_t port, uint32_t *baud)
get uart baud
Definition driver_ch9121.c:1197
ch9121_set_uart_timeout
uint8_t ch9121_set_uart_timeout(ch9121_handle_t *handle, ch9121_port_t port, uint8_t timeout)
set uart timeout
Definition driver_ch9121.c:1337
ch9121_set_gateway
uint8_t ch9121_set_gateway(ch9121_handle_t *handle, uint8_t ip[4])
set gateway
Definition driver_ch9121.c:813
ch9121_set_source_port
uint8_t ch9121_set_source_port(ch9121_handle_t *handle, ch9121_port_t port, uint16_t num)
set source port
Definition driver_ch9121.c:886
ch9121_set_port2
uint8_t ch9121_set_port2(ch9121_handle_t *handle, ch9121_bool_t enable)
enable or disable uart port2
Definition driver_ch9121.c:1610
ch9121_get_version
uint8_t ch9121_get_version(ch9121_handle_t *handle, uint8_t *version)
get version
Definition driver_ch9121.c:301
ch9121_set_dest_port
uint8_t ch9121_set_dest_port(ch9121_handle_t *handle, ch9121_port_t port, uint16_t num)
set dest port
Definition driver_ch9121.c:1063
ch9121_exit
uint8_t ch9121_exit(ch9121_handle_t *handle)
exit
Definition driver_ch9121.c:435
ch9121_get_mode
uint8_t ch9121_get_mode(ch9121_handle_t *handle, ch9121_port_t port, ch9121_mode_t *mode)
get mode
Definition driver_ch9121.c:626
ch9121_get_status
uint8_t ch9121_get_status(ch9121_handle_t *handle, ch9121_port_t port, ch9121_status_t *status)
get status
Definition driver_ch9121.c:539
ch9121_get_source_port
uint8_t ch9121_get_source_port(ch9121_handle_t *handle, ch9121_port_t port, uint16_t *num)
get source port
Definition driver_ch9121.c:930
ch9121_set_uart_buffer_length
uint8_t ch9121_set_uart_buffer_length(ch9121_handle_t *handle, ch9121_port_t port, uint32_t len)
set uart buffer length
Definition driver_ch9121.c:1522
ch9121_get_mac
uint8_t ch9121_get_mac(ch9121_handle_t *handle, uint8_t mac[6])
get chip mac
Definition driver_ch9121.c:504
CH9121_PARITY_NONE
@ CH9121_PARITY_NONE
Definition driver_ch9121.h:113
CH9121_BOOL_FALSE
@ CH9121_BOOL_FALSE
Definition driver_ch9121.h:80
CH9121_BOOL_TRUE
@ CH9121_BOOL_TRUE
Definition driver_ch9121.h:81
CH9121_MODE_UDP_SERVER
@ CH9121_MODE_UDP_SERVER
Definition driver_ch9121.h:100
CH9121_MODE_TCP_SERVER
@ CH9121_MODE_TCP_SERVER
Definition driver_ch9121.h:98
CH9121_MODE_TCP_CLIENT
@ CH9121_MODE_TCP_CLIENT
Definition driver_ch9121.h:99
CH9121_MODE_UDP_CLIENT
@ CH9121_MODE_UDP_CLIENT
Definition driver_ch9121.h:101
CH9121_STATUS_CONNECT
@ CH9121_STATUS_CONNECT
Definition driver_ch9121.h:90
CH9121_PORT2
@ CH9121_PORT2
Definition driver_ch9121.h:72
CH9121_PORT1
@ CH9121_PORT1
Definition driver_ch9121.h:71
ch9121_interface_cfg_gpio_deinit
uint8_t ch9121_interface_cfg_gpio_deinit(void)
interface cfg gpio deinit
Definition driver_ch9121_interface_template.c:159
ch9121_interface_delay_ms
void ch9121_interface_delay_ms(uint32_t ms)
interface delay ms
Definition driver_ch9121_interface_template.c:182
ch9121_interface_cfg_gpio_write
uint8_t ch9121_interface_cfg_gpio_write(uint8_t data)
interface cfg gpio write
Definition driver_ch9121_interface_template.c:172
ch9121_interface_uart_read
uint16_t ch9121_interface_uart_read(uint8_t *buf, uint16_t len)
interface uart read
Definition driver_ch9121_interface_template.c:72
ch9121_interface_uart_deinit
uint8_t ch9121_interface_uart_deinit(void)
interface uart deinit
Definition driver_ch9121_interface_template.c:58
ch9121_interface_uart_flush
uint8_t ch9121_interface_uart_flush(void)
interface uart flush
Definition driver_ch9121_interface_template.c:84
ch9121_interface_uart_write
uint8_t ch9121_interface_uart_write(uint8_t *buf, uint16_t len)
interface uart write
Definition driver_ch9121_interface_template.c:98
ch9121_interface_uart_init
uint8_t ch9121_interface_uart_init(void)
interface uart init
Definition driver_ch9121_interface_template.c:46
ch9121_interface_debug_print
void ch9121_interface_debug_print(const char *const fmt,...)
interface print format data
Definition driver_ch9121_interface_template.c:192
ch9121_interface_cfg_gpio_init
uint8_t ch9121_interface_cfg_gpio_init(void)
interface cfg gpio init
Definition driver_ch9121_interface_template.c:147
ch9121_interface_reset_gpio_init
uint8_t ch9121_interface_reset_gpio_init(void)
interface reset gpio init
Definition driver_ch9121_interface_template.c:110
ch9121_interface_reset_gpio_write
uint8_t ch9121_interface_reset_gpio_write(uint8_t data)
interface reset gpio write
Definition driver_ch9121_interface_template.c:135
ch9121_interface_reset_gpio_deinit
uint8_t ch9121_interface_reset_gpio_deinit(void)
interface reset gpio deinit
Definition driver_ch9121_interface_template.c:122
DRIVER_CH9121_LINK_RESET_GPIO_WRITE
#define DRIVER_CH9121_LINK_RESET_GPIO_WRITE(HANDLE, FUC)
link reset_gpio_write function
Definition driver_ch9121.h:235
DRIVER_CH9121_LINK_DEBUG_PRINT
#define DRIVER_CH9121_LINK_DEBUG_PRINT(HANDLE, FUC)
link debug_print function
Definition driver_ch9121.h:275
DRIVER_CH9121_LINK_INIT
#define DRIVER_CH9121_LINK_INIT(HANDLE, STRUCTURE)
initialize ch9121 structure
Definition driver_ch9121.h:171
DRIVER_CH9121_LINK_RESET_GPIO_INIT
#define DRIVER_CH9121_LINK_RESET_GPIO_INIT(HANDLE, FUC)
link reset_gpio_init function
Definition driver_ch9121.h:219
DRIVER_CH9121_LINK_UART_DEINIT
#define DRIVER_CH9121_LINK_UART_DEINIT(HANDLE, FUC)
link uart_deinit function
Definition driver_ch9121.h:187
DRIVER_CH9121_LINK_UART_WRITE
#define DRIVER_CH9121_LINK_UART_WRITE(HANDLE, FUC)
link uart_write function
Definition driver_ch9121.h:203
DRIVER_CH9121_LINK_UART_INIT
#define DRIVER_CH9121_LINK_UART_INIT(HANDLE, FUC)
link uart_init function
Definition driver_ch9121.h:179
DRIVER_CH9121_LINK_CFG_GPIO_WRITE
#define DRIVER_CH9121_LINK_CFG_GPIO_WRITE(HANDLE, FUC)
link cfg_gpio_write function
Definition driver_ch9121.h:259
DRIVER_CH9121_LINK_DELAY_MS
#define DRIVER_CH9121_LINK_DELAY_MS(HANDLE, FUC)
link delay_ms function
Definition driver_ch9121.h:267
DRIVER_CH9121_LINK_UART_READ
#define DRIVER_CH9121_LINK_UART_READ(HANDLE, FUC)
link uart_read function
Definition driver_ch9121.h:195
DRIVER_CH9121_LINK_RESET_GPIO_DEINIT
#define DRIVER_CH9121_LINK_RESET_GPIO_DEINIT(HANDLE, FUC)
link reset_gpio_deinit function
Definition driver_ch9121.h:227
DRIVER_CH9121_LINK_CFG_GPIO_DEINIT
#define DRIVER_CH9121_LINK_CFG_GPIO_DEINIT(HANDLE, FUC)
link cfg_gpio_deinit function
Definition driver_ch9121.h:251
DRIVER_CH9121_LINK_UART_FLUSH
#define DRIVER_CH9121_LINK_UART_FLUSH(HANDLE, FUC)
link uart_flush function
Definition driver_ch9121.h:211
DRIVER_CH9121_LINK_CFG_GPIO_INIT
#define DRIVER_CH9121_LINK_CFG_GPIO_INIT(HANDLE, FUC)
link cfg_gpio_init function
Definition driver_ch9121.h:243
ch9121_register_test
uint8_t ch9121_register_test(void)
register test
Definition driver_ch9121_register_test.c:49
ch9121_info_s::temperature_max
float temperature_max
Definition driver_ch9121.h:150
ch9121_info_s::supply_voltage_max_v
float supply_voltage_max_v
Definition driver_ch9121.h:147
ch9121_info_s::driver_version
uint32_t driver_version
Definition driver_ch9121.h:151
ch9121_info_s::temperature_min
float temperature_min
Definition driver_ch9121.h:149
ch9121_info_s::max_current_ma
float max_current_ma
Definition driver_ch9121.h:148
ch9121_info_s::manufacturer_name
char manufacturer_name[32]
Definition driver_ch9121.h:144
ch9121_info_s::supply_voltage_min_v
float supply_voltage_min_v
Definition driver_ch9121.h:146
ch9121_info_s::interface
char interface[8]
Definition driver_ch9121.h:145
ch9121_info_s::chip_name
char chip_name[32]
Definition driver_ch9121.h:143