driver_ch9121x.h

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#ifndef DRIVER_CH9121X_H
#define DRIVER_CH9121X_H
 
#include <stdio.h>
#include <stdint.h>
#include <string.h>
 
#ifdef __cplusplus
extern "C"{
#endif



#ifndef CH9121X_UART_PRE_DELAY
    #define CH9121X_UART_PRE_DELAY    50        
#endif

typedef enum
{
    CH9121X_PORT1 = 0x00,        
    CH9121X_PORT2 = 0x01,        
} ch9121x_port_t;

typedef enum
{
    CH9121X_BOOL_FALSE = 0x00,        
    CH9121X_BOOL_TRUE  = 0x01,        
} ch9121x_bool_t;

typedef enum
{
    CH9121X_STATUS_DISCONNECT = 0x00,        
    CH9121X_STATUS_CONNECT    = 0x01,        
} ch9121x_status_t;

typedef enum
{
    CH9121X_UART_CLOCK_MODE_DEFAULT   = 0x00,        
    CH9121X_UART_CLOCK_MODE_CLASSICAL = 0x01,        
} ch9121x_uart_clock_mode_t;

typedef enum
{
    CH9121X_PHY_STATUS_UNKNOWN          = 0x00,        
    CH9121X_PHY_STATUS_DISCONNECTED     = 0x01,        
    CH9121X_PHY_STATUS_10M_FULL_DUPLEX  = 0x02,        
    CH9121X_PHY_STATUS_10M_HALF_DUPLEX  = 0x04,        
    CH9121X_PHY_STATUS_100M_FULL_DUPLEX = 0x08,        
    CH9121X_PHY_STATUS_100M_HALF_DUPLEX = 0x10,        
} ch9121x_phy_status_t;

typedef enum
{
    CH9121X_MODE_TCP_SERVER = 0x00,        
    CH9121X_MODE_TCP_CLIENT = 0x01,        
    CH9121X_MODE_UDP_SERVER = 0x02,        
    CH9121X_MODE_UDP_CLIENT = 0x03,        
} ch9121x_mode_t;

typedef enum
{
    CH9121X_PARITY_EVEN  = 0x00,        
    CH9121X_PARITY_ODD   = 0x01,        
    CH9121X_PARITY_MARK  = 0x02,        
    CH9121X_PARITY_SPACE = 0x03,        
    CH9121X_PARITY_NONE  = 0x04,        
} ch9121x_parity_t;

typedef struct ch9121x_handle_s
{
    uint8_t (*uart_init)(void);                               
    uint8_t (*uart_deinit)(void);                             
    uint16_t (*uart_read)(uint8_t *buf, uint16_t len);        
    uint8_t (*uart_flush)(void);                              
    uint8_t (*uart_write)(uint8_t *buf, uint16_t len);        
    uint8_t (*reset_gpio_init)(void);                         
    uint8_t (*reset_gpio_deinit)(void);                       
    uint8_t (*reset_gpio_write)(uint8_t data);                
    uint8_t (*cfg_gpio_init)(void);                           
    uint8_t (*cfg_gpio_deinit)(void);                         
    uint8_t (*cfg_gpio_write)(uint8_t data);                  
    void (*delay_ms)(uint32_t ms);                            
    void (*debug_print)(const char *const fmt, ...);          
    uint8_t inited;                                           
    uint8_t buf[128];                                         
} ch9121x_handle_t;

typedef struct ch9121x_info_s
{
    char chip_name[32];                
    char manufacturer_name[32];        
    char interface[8];                 
    float supply_voltage_min_v;        
    float supply_voltage_max_v;        
    float max_current_ma;              
    float temperature_min;             
    float temperature_max;             
    uint32_t driver_version;           
} ch9121x_info_t;



#define DRIVER_CH9121X_LINK_INIT(HANDLE, STRUCTURE)          memset(HANDLE, 0, sizeof(STRUCTURE))

#define DRIVER_CH9121X_LINK_UART_INIT(HANDLE, FUC)           (HANDLE)->uart_init = FUC

#define DRIVER_CH9121X_LINK_UART_DEINIT(HANDLE, FUC)         (HANDLE)->uart_deinit = FUC

#define DRIVER_CH9121X_LINK_UART_READ(HANDLE, FUC)           (HANDLE)->uart_read = FUC

#define DRIVER_CH9121X_LINK_UART_WRITE(HANDLE, FUC)          (HANDLE)->uart_write = FUC

#define DRIVER_CH9121X_LINK_UART_FLUSH(HANDLE, FUC)          (HANDLE)->uart_flush = FUC

#define DRIVER_CH9121X_LINK_RESET_GPIO_INIT(HANDLE, FUC)     (HANDLE)->reset_gpio_init = FUC

#define DRIVER_CH9121X_LINK_RESET_GPIO_DEINIT(HANDLE, FUC)   (HANDLE)->reset_gpio_deinit = FUC

#define DRIVER_CH9121X_LINK_RESET_GPIO_WRITE(HANDLE, FUC)    (HANDLE)->reset_gpio_write = FUC

#define DRIVER_CH9121X_LINK_CFG_GPIO_INIT(HANDLE, FUC)       (HANDLE)->cfg_gpio_init = FUC

#define DRIVER_CH9121X_LINK_CFG_GPIO_DEINIT(HANDLE, FUC)     (HANDLE)->cfg_gpio_deinit = FUC

#define DRIVER_CH9121X_LINK_CFG_GPIO_WRITE(HANDLE, FUC)      (HANDLE)->cfg_gpio_write = FUC

#define DRIVER_CH9121X_LINK_DELAY_MS(HANDLE, FUC)            (HANDLE)->delay_ms = FUC

#define DRIVER_CH9121X_LINK_DEBUG_PRINT(HANDLE, FUC)         (HANDLE)->debug_print = FUC



uint8_t ch9121x_info(ch9121x_info_t *info);

uint8_t ch9121x_init(ch9121x_handle_t *handle);

uint8_t ch9121x_deinit(ch9121x_handle_t *handle);

uint8_t ch9121x_read(ch9121x_handle_t *handle, uint8_t *buf, uint16_t *len);

uint8_t ch9121x_write(ch9121x_handle_t *handle, uint8_t *buf, uint16_t len);

uint8_t ch9121x_get_version(ch9121x_handle_t *handle, uint8_t *version);

uint8_t ch9121x_reset(ch9121x_handle_t *handle);

uint8_t ch9121x_save_to_eeprom(ch9121x_handle_t *handle);

uint8_t ch9121x_config_and_reset(ch9121x_handle_t *handle);

uint8_t ch9121x_exit(ch9121x_handle_t *handle);

uint8_t ch9121x_set_dhcp(ch9121x_handle_t *handle, ch9121x_bool_t enable);

uint8_t ch9121x_get_dhcp(ch9121x_handle_t *handle, ch9121x_bool_t *enable);

uint8_t ch9121x_set_mac(ch9121x_handle_t *handle, uint8_t mac[6]);

uint8_t ch9121x_get_mac(ch9121x_handle_t *handle, uint8_t mac[6]);

uint8_t ch9121x_clear_mac(ch9121x_handle_t *handle);

uint8_t ch9121x_set_ip(ch9121x_handle_t *handle, uint8_t ip[4]);

uint8_t ch9121x_get_ip(ch9121x_handle_t *handle, uint8_t ip[4]);

uint8_t ch9121x_set_subnet_mask(ch9121x_handle_t *handle, uint8_t mask[4]);

uint8_t ch9121x_get_subnet_mask(ch9121x_handle_t *handle, uint8_t mask[4]);

uint8_t ch9121x_set_gateway(ch9121x_handle_t *handle, uint8_t ip[4]);

uint8_t ch9121x_get_gateway(ch9121x_handle_t *handle, uint8_t ip[4]);

uint8_t ch9121x_get_status(ch9121x_handle_t *handle, ch9121x_port_t port, ch9121x_status_t *status);

uint8_t ch9121x_set_mode(ch9121x_handle_t *handle, ch9121x_port_t port, ch9121x_mode_t mode);

uint8_t ch9121x_get_mode(ch9121x_handle_t *handle, ch9121x_port_t port, ch9121x_mode_t *mode);

uint8_t ch9121x_set_source_port(ch9121x_handle_t *handle, ch9121x_port_t port, uint16_t num);

uint8_t ch9121x_get_source_port(ch9121x_handle_t *handle, ch9121x_port_t port, uint16_t *num);

uint8_t ch9121x_set_dest_ip(ch9121x_handle_t *handle, ch9121x_port_t port, uint8_t ip[4]);

uint8_t ch9121x_get_dest_ip(ch9121x_handle_t *handle, ch9121x_port_t port, uint8_t ip[4]);

uint8_t ch9121x_set_dest_port(ch9121x_handle_t *handle, ch9121x_port_t port, uint16_t num);

uint8_t ch9121x_get_dest_port(ch9121x_handle_t *handle, ch9121x_port_t port, uint16_t *num);

uint8_t ch9121x_set_uart_baud(ch9121x_handle_t *handle, ch9121x_port_t port, uint32_t baud);

uint8_t ch9121x_get_uart_baud(ch9121x_handle_t *handle, ch9121x_port_t port, uint32_t *baud);

uint8_t ch9121x_set_uart_config(ch9121x_handle_t *handle, ch9121x_port_t port, uint8_t data_bit, ch9121x_parity_t parity, uint8_t stop_bit);

uint8_t ch9121x_get_uart_config(ch9121x_handle_t *handle, ch9121x_port_t port, uint8_t *data_bit, ch9121x_parity_t *parity, uint8_t *stop_bit);

uint8_t ch9121x_set_uart_timeout(ch9121x_handle_t *handle, ch9121x_port_t port, uint8_t timeout);

uint8_t ch9121x_get_uart_timeout(ch9121x_handle_t *handle, ch9121x_port_t port, uint8_t *timeout);

uint8_t ch9121x_uart_timeout_convert_to_register(ch9121x_handle_t *handle, uint16_t ms, uint8_t *reg);

uint8_t ch9121x_uart_timeout_convert_to_data(ch9121x_handle_t *handle, uint8_t reg, uint16_t *ms);

uint8_t ch9121x_set_source_port_random(ch9121x_handle_t *handle, ch9121x_port_t port, ch9121x_bool_t enable);

uint8_t ch9121x_get_source_port_random(ch9121x_handle_t *handle, ch9121x_port_t port, ch9121x_bool_t *enable);

uint8_t ch9121x_set_uart_buffer_length(ch9121x_handle_t *handle, ch9121x_port_t port, uint32_t len);

uint8_t ch9121x_get_uart_buffer_length(ch9121x_handle_t *handle, ch9121x_port_t port, uint32_t *len);

uint8_t ch9121x_set_uart_flush(ch9121x_handle_t *handle, ch9121x_port_t port, ch9121x_bool_t enable);

uint8_t ch9121x_get_uart_flush(ch9121x_handle_t *handle, ch9121x_port_t port, ch9121x_bool_t *enable);

uint8_t ch9121x_set_port2(ch9121x_handle_t *handle, ch9121x_bool_t enable);

uint8_t ch9121x_set_disconnect_with_no_rj45(ch9121x_handle_t *handle, ch9121x_bool_t enable);

uint8_t ch9121x_get_disconnect_with_no_rj45(ch9121x_handle_t *handle, ch9121x_bool_t *enable);

uint8_t ch9121x_set_domain(ch9121x_handle_t *handle, char *domain);

uint8_t ch9121x_set_eth_cfg(ch9121x_handle_t *handle, ch9121x_bool_t enable);

uint8_t ch9121x_get_eth_cfg(ch9121x_handle_t *handle, ch9121x_bool_t *enable);

uint8_t ch9121x_set_uart_clock_mode(ch9121x_handle_t *handle, ch9121x_uart_clock_mode_t mode);

uint8_t ch9121x_get_uart_clock_mode(ch9121x_handle_t *handle, ch9121x_uart_clock_mode_t *mode);

uint8_t ch9121x_get_phy_status(ch9121x_handle_t *handle, ch9121x_phy_status_t *status);

uint8_t ch9121x_set_tcp_retry_mode(ch9121x_handle_t *handle, uint8_t t);

uint8_t ch9121x_get_tcp_retry_mode(ch9121x_handle_t *handle, uint8_t *t);

uint8_t ch9121x_set_flow_control(ch9121x_handle_t *handle, ch9121x_bool_t enable);

uint8_t ch9121x_get_flow_control(ch9121x_handle_t *handle, ch9121x_bool_t *enable);

uint8_t ch9121x_set_arp_retry(ch9121x_handle_t *handle, uint8_t period, uint8_t times);

uint8_t ch9121x_tcp_retry_time_convert_to_register(ch9121x_handle_t *handle, uint16_t ms, uint8_t *reg);

uint8_t ch9121x_tcp_retry_time_convert_to_data(ch9121x_handle_t *handle, uint8_t reg, uint16_t *ms);

uint8_t ch9121x_arp_retry_period_convert_to_register(ch9121x_handle_t *handle, uint16_t ms, uint8_t *reg);

uint8_t ch9121x_arp_retry_period_convert_to_data(ch9121x_handle_t *handle, uint8_t reg, uint16_t *ms);



uint8_t ch9121x_set_command(ch9121x_handle_t *handle,
                            uint8_t *param, uint16_t len,
                            uint8_t *out, uint16_t out_len,
                            uint16_t pre_delay, uint16_t timeout);


 
#ifdef __cplusplus
}
#endif
 
#endif