42#define CHIP_NAME "WCH CH9121X"
43#define MANUFACTURER_NAME "WCH"
44#define SUPPLY_VOLTAGE_MIN 3.2f
45#define SUPPLY_VOLTAGE_MAX 3.4f
46#define MAX_CURRENT 76.2f
47#define TEMPERATURE_MIN -40.0f
48#define TEMPERATURE_MAX 85.0f
49#define DRIVER_VERSION 1000
54#define CH9121X_CMD_CHIP_VERSION 0x01
55#define CH9121X_CMD_RESET 0x02
56#define CH9121X_CMD_SAVE_TO_EEPROM 0x0D
57#define CH9121X_CMD_RUN_AND_RESET 0x0E
58#define CH9121X_CMD_EXIT 0x5E
59#define CH9121X_CMD_DHCP 0x33
60#define CH9121X_CMD_MAC 0x81
61#define CH9121X_CMD_SET_IP 0x11
62#define CH9121X_CMD_SET_NETMASK 0x12
63#define CH9121X_CMD_SET_GATEWAY 0x13
64#define CH9121X_CMD_GET_IP 0x61
65#define CH9121X_CMD_GET_NETMASK 0x62
66#define CH9121X_CMD_GET_GATEWAY 0x63
67#define CH9121X_CMD_DISCONNECT 0x24
68#define CH9121X_CMD_SET_MAC_ADDR 0x31
69#define CH9121X_CMD_CLEAR_MAC_ADDR 0x51
70#define CH9121X_CMD_SET_ETH_CFG_ENABLE 0x52
71#define CH9121X_CMD_GET_ETH_CFG_STATUS 0x53
72#define CH9121X_CMD_SET_UART_CLOCK_MODE 0x54
73#define CH9121X_CMD_GET_UART_CLOCK_MODE 0x55
74#define CH9121X_CMD_GET_PHY_STATUS 0x69
75#define CH9121X_CMD_GET_PORT1_2_LINKDOWN 0x74
76#define CH9121X_CMD_GET_DHCP_ENABLE 0x83
81#define CH9121X_CMD_PORT1_GET_STATUS 0x03
82#define CH9121X_CMD_PORT1_SET_MODE 0x10
83#define CH9121X_CMD_PORT1_SET_PORT 0x14
84#define CH9121X_CMD_PORT1_SET_DST_IP 0x15
85#define CH9121X_CMD_PORT1_SET_DST_PORT 0x16
86#define CH9121X_CMD_PORT1_SET_BAUD 0x21
87#define CH9121X_CMD_PORT1_SET_CONFIG 0x22
88#define CH9121X_CMD_PORT1_SET_TIMEOUT 0x23
89#define CH9121X_CMD_PORT1_GET_MODE 0x60
90#define CH9121X_CMD_PORT1_GET_PORT 0x64
91#define CH9121X_CMD_PORT1_GET_DST_IP 0x65
92#define CH9121X_CMD_PORT1_GET_DST_PORT 0x66
93#define CH9121X_CMD_PORT1_GET_BAUD 0x71
94#define CH9121X_CMD_PORT1_GET_CONFIG 0x72
95#define CH9121X_CMD_PORT1_GET_TIMEOUT 0x73
96#define CH9121X_CMD_PORT1_GET_RANDOM 0x67
97#define CH9121X_CMD_PORT1_GET_UART_PACK_LEN 0x75
98#define CH9121X_CMD_PORT1_GET_EMPTY 0x76
99#define CH9121X_CMD_PORT2_GET_STATUS 0x04
100#define CH9121X_CMD_PORT2_SET_MODE 0x40
101#define CH9121X_CMD_PORT2_SET_PORT 0x41
102#define CH9121X_CMD_PORT2_SET_DST_IP 0x42
103#define CH9121X_CMD_PORT2_SET_DST_PORT 0x43
104#define CH9121X_CMD_PORT2_SET_BAUD 0x44
105#define CH9121X_CMD_PORT2_SET_CONFIG 0x45
106#define CH9121X_CMD_PORT2_SET_TIMEOUT 0x46
107#define CH9121X_CMD_PORT2_GET_MODE 0x90
108#define CH9121X_CMD_PORT2_GET_PORT 0x91
109#define CH9121X_CMD_PORT2_GET_DST_IP 0x92
110#define CH9121X_CMD_PORT2_GET_DST_PORT 0x93
111#define CH9121X_CMD_PORT2_GET_BAUD 0x94
112#define CH9121X_CMD_PORT2_GET_CONFIG 0x95
113#define CH9121X_CMD_PORT2_GET_TIMEOUT 0x96
114#define CH9121X_CMD_PORT2_GET_RANDOM 0x97
115#define CH9121X_CMD_PORT2_GET_UART_PACK_LEN 0x98
116#define CH9121X_CMD_PORT2_GET_EMPTY 0x99
121#define CH9121X_CMD_PORT1_RANDOM_PORT 0x17
122#define CH9121X_CMD_PORT1_LEN 0x25
123#define CH9121X_CMD_PORT1_FLUSH 0x26
124#define CH9121X_CMD_PORT1_DOMAIN 0x34
125#define CH9121X_CMD_PORT2_ENABLE 0x39
126#define CH9121X_CMD_PORT2_RANDOM_PORT 0x47
127#define CH9121X_CMD_PORT2_LEN 0x48
128#define CH9121X_CMD_PORT2_FLUSH 0x49
133#define CH9121X_CMD2_SET_TCP_RETRY_MODE 0xA104U
134#define CH9121X_CMD2_FLOW_CONTROL_ENABLE 0xA107U
135#define CH9121X_CMD2_SET_ARP_RETRY 0xA108U
136#define CH9121X_CMD2_GET_TCP_RETRY_MODE 0xA204U
137#define CH9121X_CMD2_GET_FLOW_CONTROL_ENABLE 0xA207U
155 uint8_t *param, uint16_t len,
156 uint16_t pre_delay, uint16_t timeout)
168 handle->
buf[0] = 0x57;
169 handle->
buf[1] = 0xAB;
170 memcpy(&handle->
buf[2], param, len);
243 uint8_t *param, uint16_t len,
244 uint8_t *out, uint16_t out_len,
245 uint16_t pre_delay, uint16_t timeout)
258 handle->
buf[0] = 0x57;
259 handle->
buf[1] = 0xAB;
260 memcpy(&handle->
buf[2], param, len);
289 l = handle->
uart_read(&out[point], out_len - point);
293 if (point >= out_len)
339 if (a_ch9121x_write_read(handle, &cmd, 1, version, 1,
372 if (a_ch9121x_write_check(handle, &cmd, 1,
406 if (a_ch9121x_write_check(handle, &cmd, 1,
439 if (a_ch9121x_write_check(handle, &cmd, 1,
473 if (a_ch9121x_write_check(handle, &cmd, 1,
508 if (a_ch9121x_write_check(handle, cmd, 2,
542 if (a_ch9121x_write_read(handle, &cmd, 1, mac, 6,
585 if (a_ch9121x_write_read(handle, &cmd, 1, ¶m, 1,
629 if (a_ch9121x_write_check(handle, cmd, 2,
672 if (a_ch9121x_write_read(handle, &cmd, 1, ¶m, 1,
711 if (a_ch9121x_write_check(handle, cmd, 5,
745 if (a_ch9121x_write_read(handle, &cmd, 1, ip, 4,
783 if (a_ch9121x_write_check(handle, cmd, 5,
817 if (a_ch9121x_write_read(handle, &cmd, 1, mask, 4,
855 if (a_ch9121x_write_check(handle, cmd, 5,
889 if (a_ch9121x_write_read(handle, &cmd, 1, ip, 4,
931 cmd[1] = (num >> 0) & 0xFF;
932 cmd[2] = (num >> 8) & 0xFF;
933 if (a_ch9121x_write_check(handle, cmd, 3,
976 if (a_ch9121x_write_read(handle, &cmd, 1, buf, 2,
981 *num= (uint16_t)((uint16_t)buf[1] << 8 | buf[0]);
1023 if (a_ch9121x_write_check(handle, cmd, 5,
1065 if (a_ch9121x_write_read(handle, &cmd, 1, ip, 4,
1107 cmd[1] = (num >> 0) & 0xFF;
1108 cmd[2] = (num >> 8) & 0xFF;
1109 if (a_ch9121x_write_check(handle, cmd, 3,
1152 if (a_ch9121x_write_read(handle, &cmd, 1, buf, 2,
1157 *num= (uint16_t)((uint16_t)buf[1] << 8 | buf[0]);
1195 cmd[1] = (baud >> 0) & 0xFF;
1196 cmd[2] = (baud >> 8) & 0xFF;
1197 cmd[3] = (baud >> 16) & 0xFF;
1198 cmd[4] = (baud >> 24) & 0xFF;
1199 if (a_ch9121x_write_check(handle, cmd, 5,
1242 if (a_ch9121x_write_read(handle, &cmd, 1, buf, 4,
1247 *baud = (uint32_t)(((uint32_t)buf[0] << 0) | ((uint32_t)buf[1] << 8) |
1248 ((uint32_t)buf[2] << 16) | ((uint32_t)buf[3] << 24));
1291 if (a_ch9121x_write_check(handle, cmd, 4,
1336 if (a_ch9121x_write_read(handle, &cmd, 1, buf, 3,
1385 if (a_ch9121x_write_check(handle, cmd, 5,
1427 if (a_ch9121x_write_read(handle, &cmd, 1, timeout, 1,
1458 *reg = (uint8_t)(ms / 5);
1524 if (a_ch9121x_write_check(handle, cmd, 2,
1566 cmd[1] = (len >> 0) & 0xFF;
1567 cmd[2] = (len >> 8) & 0xFF;
1568 cmd[3] = (len >> 16) & 0xFF;
1569 cmd[4] = (len >> 24) & 0xFF;
1570 if (a_ch9121x_write_check(handle, cmd, 5,
1613 if (a_ch9121x_write_check(handle, cmd, 2,
1648 if (a_ch9121x_write_check(handle, cmd, 2,
1683 if (a_ch9121x_write_check(handle, cmd, 2,
1715 if (strlen(domain) > 28)
1723 memcpy(&cmd[1], (uint8_t *)domain, strlen(domain));
1724 if (a_ch9121x_write_check(handle, cmd,
1725 (uint16_t)(strlen(domain) + 1),
1765 if (a_ch9121x_write_check(handle, cmd, 7,
1798 if (a_ch9121x_write_check(handle, cmd, 1,
1832 cmd[1] = (uint8_t)enable;
1833 if (a_ch9121x_write_check(handle, cmd, 2,
1868 if (a_ch9121x_write_read(handle, &cmd, 1, buf, 1,
1903 cmd[1] = (uint8_t)mode;
1904 if (a_ch9121x_write_check(handle, cmd, 2,
1939 if (a_ch9121x_write_read(handle, &cmd, 1, buf, 1,
1983 if (a_ch9121x_write_read(handle, &cmd, 1, buf, 1,
2019 if (a_ch9121x_write_read(handle, &cmd, 1, buf, 1,
2078 if (a_ch9121x_write_read(handle, &cmd, 1, buf, 1,
2122 if (a_ch9121x_write_read(handle, &cmd, 1, buf, 4,
2127 *len = (uint32_t)buf[3] << 24 | (uint32_t)buf[2] << 16 |
2128 (uint32_t)buf[1] << 8 | (uint32_t)buf[0] << 0;
2167 if (a_ch9121x_write_read(handle, &cmd, 1, buf, 1,
2203 if (a_ch9121x_write_read(handle, &cmd, 1, buf, 1,
2246 cmd[2] = (uint8_t)t;
2247 if (a_ch9121x_write_check(handle, cmd, 3,
2283 if (a_ch9121x_write_read(handle, cmd, 2, buf, 1,
2319 cmd[2] = (uint8_t)enable;
2320 if (a_ch9121x_write_check(handle, cmd, 3,
2356 if (a_ch9121x_write_read(handle, cmd, 2, buf, 1,
2395 if (a_ch9121x_write_check(handle, cmd, 4,
2426 *reg = (uint8_t)(ms / 500);
2480 *reg = (uint8_t)(ms / 100);
2537 handle->
debug_print(
"ch9121x: uart_init is null.\n");
2543 handle->
debug_print(
"ch9121x: uart_deinit is null.\n");
2549 handle->
debug_print(
"ch9121x: uart_read is null.\n");
2555 handle->
debug_print(
"ch9121x: uart_write is null.\n");
2561 handle->
debug_print(
"ch9121x: uart_flush is null.\n");
2567 handle->
debug_print(
"ch9121x: delay_ms is null.\n");
2573 handle->
debug_print(
"ch9121x: reset_gpio_init is null.\n");
2579 handle->
debug_print(
"ch9121x: reset_gpio_deinit is null.\n");
2585 handle->
debug_print(
"ch9121x: reset_gpio_write is null.\n");
2591 handle->
debug_print(
"ch9121x: cfg_gpio_init is null.\n");
2597 handle->
debug_print(
"ch9121x: cfg_gpio_deinit is null.\n");
2603 handle->
debug_print(
"ch9121x: cfg_gpio_write is null.\n");
2610 handle->
debug_print(
"ch9121x: uart init failed.\n");
2616 handle->
debug_print(
"ch9121x: reset gpio init failed.\n");
2623 handle->
debug_print(
"ch9121x: cfg gpio init failed.\n");
2631 handle->
debug_print(
"ch9121x: cfg gpio write failed.\n");
2641 handle->
debug_print(
"ch9121x: cfg gpio write failed.\n");
2681 if (a_ch9121x_write_check(handle, &cmd, 1,
2689 handle->
debug_print(
"ch9121x: uart deinit failed.\n");
2695 handle->
debug_print(
"ch9121x: reset gpio deinit failed.\n");
2701 handle->
debug_print(
"ch9121x: cfg gpio deinit failed.\n");
2734 handle->
debug_print(
"ch9121x: cfg gpio write failed.\n");
2740 handle->
debug_print(
"ch9121x:uart write failed.\n");
2775 handle->
debug_print(
"ch9121x: cfg gpio write failed.\n");
2802 uint8_t *param, uint16_t len,
2803 uint8_t *out, uint16_t out_len,
2804 uint16_t pre_delay, uint16_t timeout)
2815 if (a_ch9121x_write_read(handle, param, len,
2817 pre_delay, timeout) != 0)
#define CH9121X_CMD_PORT1_SET_DST_PORT
#define CH9121X_CMD_SET_MAC_ADDR
#define CH9121X_CMD_PORT1_DOMAIN
#define CH9121X_CMD_PORT1_SET_CONFIG
#define CH9121X_CMD_GET_NETMASK
#define CH9121X_CMD2_FLOW_CONTROL_ENABLE
#define CH9121X_CMD_PORT1_RANDOM_PORT
chip port extern command definition
#define CH9121X_CMD_GET_GATEWAY
#define CH9121X_CMD_SAVE_TO_EEPROM
#define CH9121X_CMD_PORT2_LEN
#define CH9121X_CMD_PORT1_SET_DST_IP
#define CH9121X_CMD2_GET_TCP_RETRY_MODE
#define CH9121X_CMD_SET_GATEWAY
#define CH9121X_CMD_PORT1_GET_RANDOM
#define CH9121X_CMD_PORT1_GET_UART_PACK_LEN
#define CH9121X_CMD_PORT2_GET_BAUD
#define CH9121X_CMD_CHIP_VERSION
chip basic command definition
#define CH9121X_CMD_SET_ETH_CFG_ENABLE
#define CH9121X_CMD_PORT1_GET_STATUS
chip port command definition
#define CH9121X_CMD_PORT2_GET_UART_PACK_LEN
#define CH9121X_CMD_PORT1_GET_DST_PORT
#define CH9121X_CMD_PORT2_GET_RANDOM
#define CH9121X_CMD_PORT2_GET_TIMEOUT
#define CH9121X_CMD_PORT2_FLUSH
#define SUPPLY_VOLTAGE_MAX
#define CH9121X_CMD_PORT1_SET_MODE
#define CH9121X_CMD_PORT1_SET_BAUD
#define CH9121X_CMD_GET_ETH_CFG_STATUS
#define CH9121X_CMD_GET_UART_CLOCK_MODE
#define CH9121X_CMD_PORT2_GET_DST_IP
#define CH9121X_CMD_PORT2_GET_DST_PORT
#define CH9121X_CMD_PORT2_SET_PORT
#define CH9121X_CMD_PORT2_SET_TIMEOUT
#define CH9121X_CMD_PORT1_FLUSH
#define CH9121X_CMD2_SET_TCP_RETRY_MODE
chip port two bytes extern command definition
#define CH9121X_CMD2_SET_ARP_RETRY
#define CH9121X_CMD_GET_DHCP_ENABLE
#define CH9121X_CMD_PORT2_RANDOM_PORT
#define CH9121X_CMD_PORT1_GET_BAUD
#define CH9121X_CMD_PORT1_SET_TIMEOUT
#define CH9121X_CMD_PORT2_SET_DST_PORT
#define CH9121X_CMD_PORT2_SET_BAUD
#define CH9121X_CMD_PORT1_GET_DST_IP
#define MANUFACTURER_NAME
#define CH9121X_CMD_PORT2_GET_STATUS
#define CH9121X_CMD_RESET
#define SUPPLY_VOLTAGE_MIN
#define CH9121X_CMD_PORT2_SET_MODE
#define CH9121X_CMD_PORT1_SET_PORT
#define CH9121X_CMD_PORT1_GET_TIMEOUT
#define CH9121X_CMD_GET_IP
#define CH9121X_CMD_PORT1_GET_EMPTY
#define CH9121X_CMD_PORT2_SET_CONFIG
#define CH9121X_CMD_GET_PHY_STATUS
#define CH9121X_CMD_PORT2_GET_EMPTY
#define CH9121X_CMD_DISCONNECT
#define CH9121X_CMD_SET_IP
#define CH9121X_CMD_PORT2_GET_PORT
#define CH9121X_CMD_PORT2_SET_DST_IP
#define CHIP_NAME
chip information definition
#define CH9121X_CMD2_GET_FLOW_CONTROL_ENABLE
#define CH9121X_CMD_PORT1_GET_PORT
#define CH9121X_CMD_PORT2_GET_CONFIG
#define CH9121X_CMD_GET_PORT1_2_LINKDOWN
#define CH9121X_CMD_PORT1_GET_CONFIG
#define CH9121X_CMD_RUN_AND_RESET
#define CH9121X_CMD_SET_UART_CLOCK_MODE
#define CH9121X_CMD_SET_NETMASK
#define CH9121X_CMD_PORT1_LEN
#define CH9121X_CMD_PORT1_GET_MODE
#define CH9121X_CMD_PORT2_ENABLE
#define CH9121X_CMD_PORT2_GET_MODE
#define CH9121X_CMD_CLEAR_MAC_ADDR
driver ch9121x header file
ch9121x_port_t
ch9121x port enumeration definition
uint8_t ch9121x_set_dest_port(ch9121x_handle_t *handle, ch9121x_port_t port, uint16_t num)
set dest port
uint8_t ch9121x_set_uart_baud(ch9121x_handle_t *handle, ch9121x_port_t port, uint32_t baud)
set uart baud
uint8_t ch9121x_read(ch9121x_handle_t *handle, uint8_t *buf, uint16_t *len)
read data
uint8_t ch9121x_set_dest_ip(ch9121x_handle_t *handle, ch9121x_port_t port, uint8_t ip[4])
set dest ip
uint8_t ch9121x_get_mode(ch9121x_handle_t *handle, ch9121x_port_t port, ch9121x_mode_t *mode)
get mode
uint8_t ch9121x_get_dhcp(ch9121x_handle_t *handle, ch9121x_bool_t *enable)
get dhcp status
uint8_t ch9121x_get_eth_cfg(ch9121x_handle_t *handle, ch9121x_bool_t *enable)
get eth cfg
uint8_t ch9121x_get_dest_port(ch9121x_handle_t *handle, ch9121x_port_t port, uint16_t *num)
get dest port
struct ch9121x_info_s ch9121x_info_t
ch9121x information structure definition
uint8_t ch9121x_get_flow_control(ch9121x_handle_t *handle, ch9121x_bool_t *enable)
get flow control status
uint8_t ch9121x_get_uart_baud(ch9121x_handle_t *handle, ch9121x_port_t port, uint32_t *baud)
get uart baud
uint8_t ch9121x_set_uart_flush(ch9121x_handle_t *handle, ch9121x_port_t port, ch9121x_bool_t enable)
enable or disable uart auto flush
uint8_t ch9121x_get_version(ch9121x_handle_t *handle, uint8_t *version)
get version
uint8_t ch9121x_config_and_reset(ch9121x_handle_t *handle)
config and reset the chip
uint8_t ch9121x_get_source_port_random(ch9121x_handle_t *handle, ch9121x_port_t port, ch9121x_bool_t *enable)
get random source port number status
uint8_t ch9121x_clear_mac(ch9121x_handle_t *handle)
clear mac address
uint8_t ch9121x_set_uart_clock_mode(ch9121x_handle_t *handle, ch9121x_uart_clock_mode_t mode)
set uart clock mode
uint8_t ch9121x_get_uart_config(ch9121x_handle_t *handle, ch9121x_port_t port, uint8_t *data_bit, ch9121x_parity_t *parity, uint8_t *stop_bit)
get uart config
uint8_t ch9121x_set_uart_timeout(ch9121x_handle_t *handle, ch9121x_port_t port, uint8_t timeout)
set uart timeout
uint8_t ch9121x_get_dest_ip(ch9121x_handle_t *handle, ch9121x_port_t port, uint8_t ip[4])
get dest ip
uint8_t ch9121x_get_ip(ch9121x_handle_t *handle, uint8_t ip[4])
get ip address
uint8_t ch9121x_get_uart_buffer_length(ch9121x_handle_t *handle, ch9121x_port_t port, uint32_t *len)
get uart buffer length
ch9121x_phy_status_t
ch9121x phy status enumeration definition
uint8_t ch9121x_get_source_port(ch9121x_handle_t *handle, ch9121x_port_t port, uint16_t *num)
get source port
uint8_t ch9121x_set_mode(ch9121x_handle_t *handle, ch9121x_port_t port, ch9121x_mode_t mode)
set mode
ch9121x_mode_t
ch9121x mode enumeration definition
uint8_t ch9121x_set_subnet_mask(ch9121x_handle_t *handle, uint8_t mask[4])
set subnet mask
uint8_t ch9121x_uart_timeout_convert_to_register(ch9121x_handle_t *handle, uint16_t ms, uint8_t *reg)
convert the uart timeout to the register raw data
uint8_t ch9121x_write(ch9121x_handle_t *handle, uint8_t *buf, uint16_t len)
write data
uint8_t ch9121x_set_port2(ch9121x_handle_t *handle, ch9121x_bool_t enable)
enable or disable uart port2
uint8_t ch9121x_get_uart_flush(ch9121x_handle_t *handle, ch9121x_port_t port, ch9121x_bool_t *enable)
get uart auto flush status
uint8_t ch9121x_info(ch9121x_info_t *info)
get chip's information
uint8_t ch9121x_reset(ch9121x_handle_t *handle)
reset the chip
uint8_t ch9121x_arp_retry_period_convert_to_register(ch9121x_handle_t *handle, uint16_t ms, uint8_t *reg)
convert the arp retry period to the register raw data
uint8_t ch9121x_get_mac(ch9121x_handle_t *handle, uint8_t mac[6])
get chip mac
uint8_t ch9121x_set_source_port(ch9121x_handle_t *handle, ch9121x_port_t port, uint16_t num)
set source port
#define CH9121X_UART_PRE_DELAY
ch9121x uart pre delay definition
uint8_t ch9121x_set_tcp_retry_mode(ch9121x_handle_t *handle, uint8_t t)
set tcp retry mode
uint8_t ch9121x_exit(ch9121x_handle_t *handle)
exit
ch9121x_uart_clock_mode_t
ch9121x uart clock mode enumeration definition
uint8_t ch9121x_deinit(ch9121x_handle_t *handle)
close the chip
uint8_t ch9121x_set_dhcp(ch9121x_handle_t *handle, ch9121x_bool_t enable)
enable or disable dhcp
uint8_t ch9121x_arp_retry_period_convert_to_data(ch9121x_handle_t *handle, uint8_t reg, uint16_t *ms)
convert the register raw data to the arp retry period
uint8_t ch9121x_set_eth_cfg(ch9121x_handle_t *handle, ch9121x_bool_t enable)
set eth cfg
uint8_t ch9121x_get_phy_status(ch9121x_handle_t *handle, ch9121x_phy_status_t *status)
get phy status
uint8_t ch9121x_uart_timeout_convert_to_data(ch9121x_handle_t *handle, uint8_t reg, uint16_t *ms)
convert the register raw data to the offset
uint8_t ch9121x_set_disconnect_with_no_rj45(ch9121x_handle_t *handle, ch9121x_bool_t enable)
enable or disable disconnect with no rj45
uint8_t ch9121x_set_ip(ch9121x_handle_t *handle, uint8_t ip[4])
set ip address
ch9121x_bool_t
ch9121x bool enumeration definition
uint8_t ch9121x_tcp_retry_time_convert_to_register(ch9121x_handle_t *handle, uint16_t ms, uint8_t *reg)
convert the tcp retry time to the register raw data
uint8_t ch9121x_tcp_retry_time_convert_to_data(ch9121x_handle_t *handle, uint8_t reg, uint16_t *ms)
convert the register raw data to the tcp retry time
uint8_t ch9121x_set_gateway(ch9121x_handle_t *handle, uint8_t ip[4])
set gateway
ch9121x_status_t
ch9121x status enumeration definition
ch9121x_parity_t
ch9121x parity enumeration definition
uint8_t ch9121x_get_status(ch9121x_handle_t *handle, ch9121x_port_t port, ch9121x_status_t *status)
get status
uint8_t ch9121x_set_mac(ch9121x_handle_t *handle, uint8_t mac[6])
set mac address
uint8_t ch9121x_set_domain(ch9121x_handle_t *handle, char *domain)
set chip domain
uint8_t ch9121x_set_flow_control(ch9121x_handle_t *handle, ch9121x_bool_t enable)
enable or disable flow control
uint8_t ch9121x_get_uart_timeout(ch9121x_handle_t *handle, ch9121x_port_t port, uint8_t *timeout)
get uart timeout
uint8_t ch9121x_get_gateway(ch9121x_handle_t *handle, uint8_t ip[4])
get gateway
uint8_t ch9121x_get_subnet_mask(ch9121x_handle_t *handle, uint8_t mask[4])
get subnet mask
uint8_t ch9121x_get_disconnect_with_no_rj45(ch9121x_handle_t *handle, ch9121x_bool_t *enable)
get disconnect with no rj45 status
uint8_t ch9121x_save_to_eeprom(ch9121x_handle_t *handle)
save to eeprom
uint8_t ch9121x_init(ch9121x_handle_t *handle)
initialize the chip
uint8_t ch9121x_get_tcp_retry_mode(ch9121x_handle_t *handle, uint8_t *t)
get tcp retry mode
uint8_t ch9121x_set_arp_retry(ch9121x_handle_t *handle, uint8_t period, uint8_t times)
set arp retry
struct ch9121x_handle_s ch9121x_handle_t
ch9121x handle structure definition
uint8_t ch9121x_set_source_port_random(ch9121x_handle_t *handle, ch9121x_port_t port, ch9121x_bool_t enable)
enable or disable random source port number
uint8_t ch9121x_get_uart_clock_mode(ch9121x_handle_t *handle, ch9121x_uart_clock_mode_t *mode)
get uart clock mode
uint8_t ch9121x_set_uart_buffer_length(ch9121x_handle_t *handle, ch9121x_port_t port, uint32_t len)
set uart buffer length
uint8_t ch9121x_set_uart_config(ch9121x_handle_t *handle, ch9121x_port_t port, uint8_t data_bit, ch9121x_parity_t parity, uint8_t stop_bit)
set uart config
@ CH9121X_PHY_STATUS_UNKNOWN
@ CH9121X_PHY_STATUS_100M_FULL_DUPLEX
@ CH9121X_PHY_STATUS_10M_HALF_DUPLEX
@ CH9121X_PHY_STATUS_DISCONNECTED
@ CH9121X_PHY_STATUS_10M_FULL_DUPLEX
@ CH9121X_PHY_STATUS_100M_HALF_DUPLEX
uint8_t ch9121x_set_command(ch9121x_handle_t *handle, uint8_t *param, uint16_t len, uint8_t *out, uint16_t out_len, uint16_t pre_delay, uint16_t timeout)
set command
uint8_t(* uart_flush)(void)
uint8_t(* cfg_gpio_write)(uint8_t data)
uint8_t(* uart_write)(uint8_t *buf, uint16_t len)
void(* delay_ms)(uint32_t ms)
uint8_t(* cfg_gpio_init)(void)
uint8_t(* uart_deinit)(void)
uint8_t(* reset_gpio_deinit)(void)
void(* debug_print)(const char *const fmt,...)
uint16_t(* uart_read)(uint8_t *buf, uint16_t len)
uint8_t(* reset_gpio_init)(void)
uint8_t(* uart_init)(void)
uint8_t(* reset_gpio_write)(uint8_t data)
uint8_t(* cfg_gpio_deinit)(void)
float supply_voltage_max_v
char manufacturer_name[32]
float supply_voltage_min_v