LibDriver CH9121X
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driver_ch9121x.c
Go to the documentation of this file.
1
36
37#include "driver_ch9121x.h"
38
42#define CHIP_NAME "WCH CH9121X"
43#define MANUFACTURER_NAME "WCH"
44#define SUPPLY_VOLTAGE_MIN 3.2f
45#define SUPPLY_VOLTAGE_MAX 3.4f
46#define MAX_CURRENT 76.2f
47#define TEMPERATURE_MIN -40.0f
48#define TEMPERATURE_MAX 85.0f
49#define DRIVER_VERSION 1000
50
54#define CH9121X_CMD_CHIP_VERSION 0x01
55#define CH9121X_CMD_RESET 0x02
56#define CH9121X_CMD_SAVE_TO_EEPROM 0x0D
57#define CH9121X_CMD_RUN_AND_RESET 0x0E
58#define CH9121X_CMD_EXIT 0x5E
59#define CH9121X_CMD_DHCP 0x33
60#define CH9121X_CMD_MAC 0x81
61#define CH9121X_CMD_SET_IP 0x11
62#define CH9121X_CMD_SET_NETMASK 0x12
63#define CH9121X_CMD_SET_GATEWAY 0x13
64#define CH9121X_CMD_GET_IP 0x61
65#define CH9121X_CMD_GET_NETMASK 0x62
66#define CH9121X_CMD_GET_GATEWAY 0x63
67#define CH9121X_CMD_DISCONNECT 0x24
68#define CH9121X_CMD_SET_MAC_ADDR 0x31
69#define CH9121X_CMD_CLEAR_MAC_ADDR 0x51
70#define CH9121X_CMD_SET_ETH_CFG_ENABLE 0x52
71#define CH9121X_CMD_GET_ETH_CFG_STATUS 0x53
72#define CH9121X_CMD_SET_UART_CLOCK_MODE 0x54
73#define CH9121X_CMD_GET_UART_CLOCK_MODE 0x55
74#define CH9121X_CMD_GET_PHY_STATUS 0x69
75#define CH9121X_CMD_GET_PORT1_2_LINKDOWN 0x74
76#define CH9121X_CMD_GET_DHCP_ENABLE 0x83
77
81#define CH9121X_CMD_PORT1_GET_STATUS 0x03
82#define CH9121X_CMD_PORT1_SET_MODE 0x10
83#define CH9121X_CMD_PORT1_SET_PORT 0x14
84#define CH9121X_CMD_PORT1_SET_DST_IP 0x15
85#define CH9121X_CMD_PORT1_SET_DST_PORT 0x16
86#define CH9121X_CMD_PORT1_SET_BAUD 0x21
87#define CH9121X_CMD_PORT1_SET_CONFIG 0x22
88#define CH9121X_CMD_PORT1_SET_TIMEOUT 0x23
89#define CH9121X_CMD_PORT1_GET_MODE 0x60
90#define CH9121X_CMD_PORT1_GET_PORT 0x64
91#define CH9121X_CMD_PORT1_GET_DST_IP 0x65
92#define CH9121X_CMD_PORT1_GET_DST_PORT 0x66
93#define CH9121X_CMD_PORT1_GET_BAUD 0x71
94#define CH9121X_CMD_PORT1_GET_CONFIG 0x72
95#define CH9121X_CMD_PORT1_GET_TIMEOUT 0x73
96#define CH9121X_CMD_PORT1_GET_RANDOM 0x67
97#define CH9121X_CMD_PORT1_GET_UART_PACK_LEN 0x75
98#define CH9121X_CMD_PORT1_GET_EMPTY 0x76
99#define CH9121X_CMD_PORT2_GET_STATUS 0x04
100#define CH9121X_CMD_PORT2_SET_MODE 0x40
101#define CH9121X_CMD_PORT2_SET_PORT 0x41
102#define CH9121X_CMD_PORT2_SET_DST_IP 0x42
103#define CH9121X_CMD_PORT2_SET_DST_PORT 0x43
104#define CH9121X_CMD_PORT2_SET_BAUD 0x44
105#define CH9121X_CMD_PORT2_SET_CONFIG 0x45
106#define CH9121X_CMD_PORT2_SET_TIMEOUT 0x46
107#define CH9121X_CMD_PORT2_GET_MODE 0x90
108#define CH9121X_CMD_PORT2_GET_PORT 0x91
109#define CH9121X_CMD_PORT2_GET_DST_IP 0x92
110#define CH9121X_CMD_PORT2_GET_DST_PORT 0x93
111#define CH9121X_CMD_PORT2_GET_BAUD 0x94
112#define CH9121X_CMD_PORT2_GET_CONFIG 0x95
113#define CH9121X_CMD_PORT2_GET_TIMEOUT 0x96
114#define CH9121X_CMD_PORT2_GET_RANDOM 0x97
115#define CH9121X_CMD_PORT2_GET_UART_PACK_LEN 0x98
116#define CH9121X_CMD_PORT2_GET_EMPTY 0x99
117
121#define CH9121X_CMD_PORT1_RANDOM_PORT 0x17
122#define CH9121X_CMD_PORT1_LEN 0x25
123#define CH9121X_CMD_PORT1_FLUSH 0x26
124#define CH9121X_CMD_PORT1_DOMAIN 0x34
125#define CH9121X_CMD_PORT2_ENABLE 0x39
126#define CH9121X_CMD_PORT2_RANDOM_PORT 0x47
127#define CH9121X_CMD_PORT2_LEN 0x48
128#define CH9121X_CMD_PORT2_FLUSH 0x49
129
133#define CH9121X_CMD2_SET_TCP_RETRY_MODE 0xA104U
134#define CH9121X_CMD2_FLOW_CONTROL_ENABLE 0xA107U
135#define CH9121X_CMD2_SET_ARP_RETRY 0xA108U
136#define CH9121X_CMD2_GET_TCP_RETRY_MODE 0xA204U
137#define CH9121X_CMD2_GET_FLOW_CONTROL_ENABLE 0xA207U
138
154static uint8_t a_ch9121x_write_check(ch9121x_handle_t *handle,
155 uint8_t *param, uint16_t len,
156 uint16_t pre_delay, uint16_t timeout)
157{
158 uint16_t t;
159 uint8_t res;
160
161 if (len > 126) /* check length */
162 {
163 handle->debug_print("ch9121x: len is invalid.\n"); /* len is invalid */
164
165 return 2; /* return error */
166 }
167
168 handle->buf[0] = 0x57; /* set header 0 */
169 handle->buf[1] = 0xAB; /* set header 1 */
170 memcpy(&handle->buf[2], param, len); /* copy param */
171 res = handle->cfg_gpio_write(0); /* set low */
172 if (res != 0) /* check result */
173 {
174 return 1; /* return error */
175 }
176 res = handle->uart_flush(); /* uart flush */
177 if (res != 0) /* check result */
178 {
179 return 1; /* return error */
180 }
181 if (handle->uart_write(handle->buf, 2 + len) != 0) /* write command */
182 {
183 handle->debug_print("ch9121x: write failed.\n"); /* write failed */
184 (void)handle->cfg_gpio_write(1); /* set high */
185
186 return 1; /* return error */
187 }
188 if (pre_delay != 0) /* check pre_delay */
189 {
190 handle->delay_ms(pre_delay); /* delay pre_delay */
191 }
192
193 t = timeout / 10; /* 10ms */
194 while (t != 0) /* check timeout */
195 {
196 if (handle->uart_read(&res, 1) == 1) /* read data */
197 {
198 if (res == 0xAA) /* check 0xAA */
199 {
200 res = handle->cfg_gpio_write(1); /* set high */
201 if (res != 0) /* check result */
202 {
203 return 1; /* return error */
204 }
205
206 return 0; /* success return 0 */
207 }
208 else
209 {
210 handle->debug_print("ch9121x: error.\n"); /* error */
211 (void)handle->cfg_gpio_write(1); /* set high */
212
213 return 3; /* return error */
214 }
215 }
216 handle->delay_ms(10); /* delay 10ms */
217 t--; /* timeout-- */
218 }
219
220 handle->debug_print("ch9121x: timeout.\n"); /* timeout */
221 (void)handle->cfg_gpio_write(1); /* set high */
222
223 return 4; /* return error */
224}
225
242static uint8_t a_ch9121x_write_read(ch9121x_handle_t *handle,
243 uint8_t *param, uint16_t len,
244 uint8_t *out, uint16_t out_len,
245 uint16_t pre_delay, uint16_t timeout)
246{
247 uint8_t res;
248 uint16_t t;
249 uint16_t point;
250
251 if (len > 126) /* check length */
252 {
253 handle->debug_print("ch9121x: len is invalid.\n"); /* len is invalid */
254
255 return 2; /* return error */
256 }
257
258 handle->buf[0] = 0x57; /* set header 0 */
259 handle->buf[1] = 0xAB; /* set header 1 */
260 memcpy(&handle->buf[2], param, len); /* copy param */
261 res = handle->cfg_gpio_write(0); /* set low */
262 if (res != 0) /* check result */
263 {
264 return 1; /* return error */
265 }
266 res = handle->uart_flush(); /* uart flush */
267 if (res != 0) /* check result */
268 {
269 return 1; /* return error */
270 }
271 if (handle->uart_write(handle->buf, 2 + len) != 0) /* write command */
272 {
273 handle->debug_print("ch9121x: write failed.\n"); /* write failed */
274 (void)handle->cfg_gpio_write(1); /* set high */
275
276 return 1; /* return error */
277 }
278 if (pre_delay != 0) /* check pre_delay */
279 {
280 handle->delay_ms(pre_delay); /* delay pre_delay */
281 }
282
283 point = 0; /* init 0 */
284 t = timeout / 10; /* 10ms */
285 while (t != 0) /* check timeout */
286 {
287 uint16_t l;
288
289 l = handle->uart_read(&out[point], out_len - point); /* read data */
290 if (l != 0)
291 {
292 point += l; /* point += l*/
293 if (point >= out_len) /* check length */
294 {
295 res = handle->cfg_gpio_write(1); /* set high */
296 if (res != 0) /* check result */
297 {
298 return 1; /* return error */
299 }
300
301 return 0; /* success return 0 */
302 }
303 }
304 handle->delay_ms(10); /* delay 10ms */
305 t--; /* timeout-- */
306 }
307
308 handle->debug_print("ch9121x: timeout.\n"); /* timeout */
309 (void)handle->cfg_gpio_write(1); /* set high */
310
311 return 3; /* return error */
312}
313
325uint8_t ch9121x_get_version(ch9121x_handle_t *handle, uint8_t *version)
326{
327 uint8_t cmd;
328
329 if (handle == NULL) /* check handle */
330 {
331 return 2; /* return error */
332 }
333 if (handle->inited != 1) /* check handle initialization */
334 {
335 return 3; /* return error */
336 }
337
338 cmd = CH9121X_CMD_CHIP_VERSION; /* set chip version */
339 if (a_ch9121x_write_read(handle, &cmd, 1, version, 1,
340 CH9121X_UART_PRE_DELAY, 1000) != 0) /* get version */
341 {
342 return 1; /* return error */
343 }
344
345 return 0; /* success return 0 */
346}
347
359{
360 uint8_t cmd;
361
362 if (handle == NULL) /* check handle */
363 {
364 return 2; /* return error */
365 }
366 if (handle->inited != 1) /* check handle initialization */
367 {
368 return 3; /* return error */
369 }
370
371 cmd = CH9121X_CMD_RESET; /* set reset */
372 if (a_ch9121x_write_check(handle, &cmd, 1,
373 CH9121X_UART_PRE_DELAY, 1000) != 0) /* reset */
374 {
375 return 1; /* return error */
376 }
377 handle->delay_ms(1000); /* delay 1000ms */
378
379 return 0; /* success return 0 */
380}
381
393{
394 uint8_t cmd;
395
396 if (handle == NULL) /* check handle */
397 {
398 return 2; /* return error */
399 }
400 if (handle->inited != 1) /* check handle initialization */
401 {
402 return 3; /* return error */
403 }
404
405 cmd = CH9121X_CMD_SAVE_TO_EEPROM; /* set save to eeprom */
406 if (a_ch9121x_write_check(handle, &cmd, 1,
407 CH9121X_UART_PRE_DELAY, 1000) != 0) /* save to eeprom */
408 {
409 return 1; /* return error */
410 }
411
412 return 0; /* success return 0 */
413}
414
426{
427 uint8_t cmd;
428
429 if (handle == NULL) /* check handle */
430 {
431 return 2; /* return error */
432 }
433 if (handle->inited != 1) /* check handle initialization */
434 {
435 return 3; /* return error */
436 }
437
438 cmd = CH9121X_CMD_RUN_AND_RESET; /* set run config reset */
439 if (a_ch9121x_write_check(handle, &cmd, 1,
440 CH9121X_UART_PRE_DELAY, 1000) != 0) /* run config reset */
441 {
442 return 1; /* return error */
443 }
444 handle->delay_ms(1000); /* delay 1000ms */
445
446 return 0; /* success return 0 */
447}
448
460{
461 uint8_t cmd;
462
463 if (handle == NULL) /* check handle */
464 {
465 return 2; /* return error */
466 }
467 if (handle->inited != 1) /* check handle initialization */
468 {
469 return 3; /* return error */
470 }
471
472 cmd = CH9121X_CMD_EXIT; /* set exit */
473 if (a_ch9121x_write_check(handle, &cmd, 1,
474 CH9121X_UART_PRE_DELAY, 1000) != 0) /* exit */
475 {
476 return 1; /* return error */
477 }
478
479 return 0; /* success return 0 */
480}
481
494{
495 uint8_t cmd[2];
496
497 if (handle == NULL) /* check handle */
498 {
499 return 2; /* return error */
500 }
501 if (handle->inited != 1) /* check handle initialization */
502 {
503 return 3; /* return error */
504 }
505
506 cmd[0] = CH9121X_CMD_DHCP; /* set dhcp */
507 cmd[1] = enable; /* set bool */
508 if (a_ch9121x_write_check(handle, cmd, 2,
509 CH9121X_UART_PRE_DELAY, 1000) != 0) /* dhcp */
510 {
511 return 1; /* return error */
512 }
513
514 return 0; /* success return 0 */
515}
516
528uint8_t ch9121x_get_mac(ch9121x_handle_t *handle, uint8_t mac[6])
529{
530 uint8_t cmd;
531
532 if (handle == NULL) /* check handle */
533 {
534 return 2; /* return error */
535 }
536 if (handle->inited != 1) /* check handle initialization */
537 {
538 return 3; /* return error */
539 }
540
541 cmd = CH9121X_CMD_MAC; /* set mac */
542 if (a_ch9121x_write_read(handle, &cmd, 1, mac, 6,
543 CH9121X_UART_PRE_DELAY, 1000) != 0) /* mac*/
544 {
545 return 1; /* return error */
546 }
547
548 return 0; /* success return 0 */
549}
550
564{
565 uint8_t cmd;
566 uint8_t param;
567
568 if (handle == NULL) /* check handle */
569 {
570 return 2; /* return error */
571 }
572 if (handle->inited != 1) /* check handle initialization */
573 {
574 return 3; /* return error */
575 }
576
577 if (port == CH9121X_PORT1) /* port1 */
578 {
579 cmd = CH9121X_CMD_PORT1_GET_STATUS; /* get port1 status */
580 }
581 else /* port2 */
582 {
583 cmd = CH9121X_CMD_PORT2_GET_STATUS; /* get port2 status */
584 }
585 if (a_ch9121x_write_read(handle, &cmd, 1, &param, 1,
586 CH9121X_UART_PRE_DELAY, 1000) != 0) /* get status */
587 {
588 return 1; /* return error */
589 }
590 *status = (ch9121x_status_t)(param); /* get the status */
591
592 return 0; /* success return 0 */
593}
594
608{
609 uint8_t cmd[2];
610
611 if (handle == NULL) /* check handle */
612 {
613 return 2; /* return error */
614 }
615 if (handle->inited != 1) /* check handle initialization */
616 {
617 return 3; /* return error */
618 }
619
620 if (port == CH9121X_PORT1) /* port1 */
621 {
622 cmd[0] = CH9121X_CMD_PORT1_SET_MODE; /* set port1 mode */
623 }
624 else /* port2 */
625 {
626 cmd[0] = CH9121X_CMD_PORT2_SET_MODE; /* set port2 mode */
627 }
628 cmd[1] = mode; /* set mode */
629 if (a_ch9121x_write_check(handle, cmd, 2,
630 CH9121X_UART_PRE_DELAY, 1000) != 0) /* write mode */
631 {
632 return 1; /* return error */
633 }
634
635 return 0; /* success return 0 */
636}
637
651{
652 uint8_t cmd;
653 uint8_t param;
654
655 if (handle == NULL) /* check handle */
656 {
657 return 2; /* return error */
658 }
659 if (handle->inited != 1) /* check handle initialization */
660 {
661 return 3; /* return error */
662 }
663
664 if (port == CH9121X_PORT1) /* port1 */
665 {
666 cmd = CH9121X_CMD_PORT1_GET_MODE; /* get port1 mode */
667 }
668 else /* port2 */
669 {
670 cmd = CH9121X_CMD_PORT2_GET_MODE; /* get port2 mode */
671 }
672 if (a_ch9121x_write_read(handle, &cmd, 1, &param, 1,
673 CH9121X_UART_PRE_DELAY, 1000) != 0) /* get mode */
674 {
675 return 1; /* return error */
676 }
677 *mode = (ch9121x_mode_t)(param); /* get mode */
678
679 return 0; /* success return 0 */
680}
681
693uint8_t ch9121x_set_ip(ch9121x_handle_t *handle, uint8_t ip[4])
694{
695 uint8_t cmd[5];
696
697 if (handle == NULL) /* check handle */
698 {
699 return 2; /* return error */
700 }
701 if (handle->inited != 1) /* check handle initialization */
702 {
703 return 3; /* return error */
704 }
705
706 cmd[0] = CH9121X_CMD_SET_IP; /* set ip */
707 cmd[1] = ip[0]; /* set ip[0] */
708 cmd[2] = ip[1]; /* set ip[1] */
709 cmd[3] = ip[2]; /* set ip[2] */
710 cmd[4] = ip[3]; /* set ip[3] */
711 if (a_ch9121x_write_check(handle, cmd, 5,
712 CH9121X_UART_PRE_DELAY, 1000) != 0) /* write ip */
713 {
714 return 1; /* return error */
715 }
716
717 return 0; /* success return 0 */
718}
719
731uint8_t ch9121x_get_ip(ch9121x_handle_t *handle, uint8_t ip[4])
732{
733 uint8_t cmd;
734
735 if (handle == NULL) /* check handle */
736 {
737 return 2; /* return error */
738 }
739 if (handle->inited != 1) /* check handle initialization */
740 {
741 return 3; /* return error */
742 }
743
744 cmd = CH9121X_CMD_GET_IP; /* get ip */
745 if (a_ch9121x_write_read(handle, &cmd, 1, ip, 4,
746 CH9121X_UART_PRE_DELAY, 1000) != 0) /* read ip */
747 {
748 return 1; /* return error */
749 }
750
751 return 0; /* success return 0 */
752}
753
765uint8_t ch9121x_set_subnet_mask(ch9121x_handle_t *handle, uint8_t mask[4])
766{
767 uint8_t cmd[5];
768
769 if (handle == NULL) /* check handle */
770 {
771 return 2; /* return error */
772 }
773 if (handle->inited != 1) /* check handle initialization */
774 {
775 return 3; /* return error */
776 }
777
778 cmd[0] = CH9121X_CMD_SET_NETMASK ; /* set sub mask */
779 cmd[1] = mask[0]; /* set mask[0] */
780 cmd[2] = mask[1]; /* set mask[1] */
781 cmd[3] = mask[2]; /* set mask[2] */
782 cmd[4] = mask[3]; /* set mask[3] */
783 if (a_ch9121x_write_check(handle, cmd, 5,
784 CH9121X_UART_PRE_DELAY, 1000) != 0) /* write subnet mask */
785 {
786 return 1; /* return error */
787 }
788
789 return 0; /* success return 0 */
790}
791
803uint8_t ch9121x_get_subnet_mask(ch9121x_handle_t *handle, uint8_t mask[4])
804{
805 uint8_t cmd;
806
807 if (handle == NULL) /* check handle */
808 {
809 return 2; /* return error */
810 }
811 if (handle->inited != 1) /* check handle initialization */
812 {
813 return 3; /* return error */
814 }
815
816 cmd = CH9121X_CMD_GET_NETMASK ; /* get mask */
817 if (a_ch9121x_write_read(handle, &cmd, 1, mask, 4,
818 CH9121X_UART_PRE_DELAY, 1000) != 0) /* read subnet mask */
819 {
820 return 1; /* return error */
821 }
822
823 return 0; /* success return 0 */
824}
825
837uint8_t ch9121x_set_gateway(ch9121x_handle_t *handle, uint8_t ip[4])
838{
839 uint8_t cmd[5];
840
841 if (handle == NULL) /* check handle */
842 {
843 return 2; /* return error */
844 }
845 if (handle->inited != 1) /* check handle initialization */
846 {
847 return 3; /* return error */
848 }
849
850 cmd[0] = CH9121X_CMD_SET_GATEWAY ; /* set gateway */
851 cmd[1] = ip[0]; /* set ip[0] */
852 cmd[2] = ip[1]; /* set ip[1] */
853 cmd[3] = ip[2]; /* set ip[2] */
854 cmd[4] = ip[3]; /* set ip[3] */
855 if (a_ch9121x_write_check(handle, cmd, 5,
856 CH9121X_UART_PRE_DELAY, 1000) != 0) /* write ip */
857 {
858 return 1; /* return error */
859 }
860
861 return 0; /* success return 0 */
862}
863
875uint8_t ch9121x_get_gateway(ch9121x_handle_t *handle, uint8_t ip[4])
876{
877 uint8_t cmd;
878
879 if (handle == NULL) /* check handle */
880 {
881 return 2; /* return error */
882 }
883 if (handle->inited != 1) /* check handle initialization */
884 {
885 return 3; /* return error */
886 }
887
888 cmd = CH9121X_CMD_GET_GATEWAY; /* get gateway */
889 if (a_ch9121x_write_read(handle, &cmd, 1, ip, 4,
890 CH9121X_UART_PRE_DELAY, 1000) != 0) /* read gateway */
891 {
892 return 1; /* return error */
893 }
894
895 return 0; /* success return 0 */
896}
897
910uint8_t ch9121x_set_source_port(ch9121x_handle_t *handle, ch9121x_port_t port, uint16_t num)
911{
912 uint8_t cmd[3];
913
914 if (handle == NULL) /* check handle */
915 {
916 return 2; /* return error */
917 }
918 if (handle->inited != 1) /* check handle initialization */
919 {
920 return 3; /* return error */
921 }
922
923 if (port == CH9121X_PORT1) /* port1 */
924 {
925 cmd[0] = CH9121X_CMD_PORT1_SET_PORT; /* set port1 port */
926 }
927 else /* port2 */
928 {
929 cmd[0] = CH9121X_CMD_PORT2_SET_PORT; /* set port2 port */
930 }
931 cmd[1] = (num >> 0) & 0xFF; /* set port msb */
932 cmd[2] = (num >> 8) & 0xFF; /* set port lsb */
933 if (a_ch9121x_write_check(handle, cmd, 3,
934 CH9121X_UART_PRE_DELAY, 1000) != 0) /* write port */
935 {
936 return 1; /* return error */
937 }
938
939 return 0; /* success return 0 */
940}
941
954uint8_t ch9121x_get_source_port(ch9121x_handle_t *handle, ch9121x_port_t port, uint16_t *num)
955{
956 uint8_t cmd;
957 uint8_t buf[2];
958
959 if (handle == NULL) /* check handle */
960 {
961 return 2; /* return error */
962 }
963 if (handle->inited != 1) /* check handle initialization */
964 {
965 return 3; /* return error */
966 }
967
968 if (port == CH9121X_PORT1) /* port1 */
969 {
970 cmd = CH9121X_CMD_PORT1_GET_PORT; /* get port1 port */
971 }
972 else /* port2 */
973 {
974 cmd = CH9121X_CMD_PORT2_GET_PORT; /* get port2 port */
975 }
976 if (a_ch9121x_write_read(handle, &cmd, 1, buf, 2,
977 CH9121X_UART_PRE_DELAY, 1000) != 0) /* get port */
978 {
979 return 1; /* return error */
980 }
981 *num= (uint16_t)((uint16_t)buf[1] << 8 | buf[0]); /* get port */
982
983 return 0; /* success return 0 */
984}
985
998uint8_t ch9121x_set_dest_ip(ch9121x_handle_t *handle, ch9121x_port_t port, uint8_t ip[4])
999{
1000 uint8_t cmd[5];
1001
1002 if (handle == NULL) /* check handle */
1003 {
1004 return 2; /* return error */
1005 }
1006 if (handle->inited != 1) /* check handle initialization */
1007 {
1008 return 3; /* return error */
1009 }
1010
1011 if (port == CH9121X_PORT1) /* port1 */
1012 {
1013 cmd[0] = CH9121X_CMD_PORT1_SET_DST_IP; /* set port1 dest ip */
1014 }
1015 else /* port2 */
1016 {
1017 cmd[0] = CH9121X_CMD_PORT2_SET_DST_IP; /* set port2 dest ip */
1018 }
1019 cmd[1] = ip[0]; /* set ip[0] */
1020 cmd[2] = ip[1]; /* set ip[1] */
1021 cmd[3] = ip[2]; /* set ip[0] */
1022 cmd[4] = ip[3]; /* set ip[1] */
1023 if (a_ch9121x_write_check(handle, cmd, 5,
1024 CH9121X_UART_PRE_DELAY, 1000) != 0) /* write dest ip */
1025 {
1026 return 1; /* return error */
1027 }
1028
1029 return 0; /* success return 0 */
1030}
1031
1044uint8_t ch9121x_get_dest_ip(ch9121x_handle_t *handle, ch9121x_port_t port, uint8_t ip[4])
1045{
1046 uint8_t cmd;
1047
1048 if (handle == NULL) /* check handle */
1049 {
1050 return 2; /* return error */
1051 }
1052 if (handle->inited != 1) /* check handle initialization */
1053 {
1054 return 3; /* return error */
1055 }
1056
1057 if (port == CH9121X_PORT1) /* port1 */
1058 {
1059 cmd = CH9121X_CMD_PORT1_GET_DST_IP; /* get port1 dest ip */
1060 }
1061 else /* port2 */
1062 {
1063 cmd = CH9121X_CMD_PORT2_GET_DST_IP; /* get port2 dest ip */
1064 }
1065 if (a_ch9121x_write_read(handle, &cmd, 1, ip, 4,
1066 CH9121X_UART_PRE_DELAY, 1000) != 0) /* get dest ip */
1067 {
1068 return 1; /* return error */
1069 }
1070
1071 return 0; /* success return 0 */
1072}
1073
1086uint8_t ch9121x_set_dest_port(ch9121x_handle_t *handle, ch9121x_port_t port, uint16_t num)
1087{
1088 uint8_t cmd[3];
1089
1090 if (handle == NULL) /* check handle */
1091 {
1092 return 2; /* return error */
1093 }
1094 if (handle->inited != 1) /* check handle initialization */
1095 {
1096 return 3; /* return error */
1097 }
1098
1099 if (port == CH9121X_PORT1) /* port1 */
1100 {
1101 cmd[0] = CH9121X_CMD_PORT1_SET_DST_PORT; /* set port1 dest port */
1102 }
1103 else /* port2 */
1104 {
1105 cmd[0] = CH9121X_CMD_PORT2_SET_DST_PORT; /* set port2 dest port */
1106 }
1107 cmd[1] = (num >> 0) & 0xFF; /* set port msb */
1108 cmd[2] = (num >> 8) & 0xFF; /* set port lsb */
1109 if (a_ch9121x_write_check(handle, cmd, 3,
1110 CH9121X_UART_PRE_DELAY, 1000) != 0) /* write dest port */
1111 {
1112 return 1; /* return error */
1113 }
1114
1115 return 0; /* success return 0 */
1116}
1117
1130uint8_t ch9121x_get_dest_port(ch9121x_handle_t *handle, ch9121x_port_t port, uint16_t *num)
1131{
1132 uint8_t cmd;
1133 uint8_t buf[2];
1134
1135 if (handle == NULL) /* check handle */
1136 {
1137 return 2; /* return error */
1138 }
1139 if (handle->inited != 1) /* check handle initialization */
1140 {
1141 return 3; /* return error */
1142 }
1143
1144 if (port == CH9121X_PORT1) /* port1 */
1145 {
1146 cmd = CH9121X_CMD_PORT1_GET_DST_PORT; /* get port1 dest port */
1147 }
1148 else /* port2 */
1149 {
1150 cmd = CH9121X_CMD_PORT2_GET_DST_PORT; /* get port2 dest port */
1151 }
1152 if (a_ch9121x_write_read(handle, &cmd, 1, buf, 2,
1153 CH9121X_UART_PRE_DELAY, 1000) != 0) /* get dest port */
1154 {
1155 return 1; /* return error */
1156 }
1157 *num= (uint16_t)((uint16_t)buf[1] << 8 | buf[0]); /* get port */
1158
1159 return 0; /* success return 0 */
1160}
1161
1174uint8_t ch9121x_set_uart_baud(ch9121x_handle_t *handle, ch9121x_port_t port, uint32_t baud)
1175{
1176 uint8_t cmd[5];
1177
1178 if (handle == NULL) /* check handle */
1179 {
1180 return 2; /* return error */
1181 }
1182 if (handle->inited != 1) /* check handle initialization */
1183 {
1184 return 3; /* return error */
1185 }
1186
1187 if (port == CH9121X_PORT1) /* port1 */
1188 {
1189 cmd[0] = CH9121X_CMD_PORT1_SET_BAUD; /* set port1 baud */
1190 }
1191 else /* port2 */
1192 {
1193 cmd[0] = CH9121X_CMD_PORT2_SET_BAUD; /* set port2 baud */
1194 }
1195 cmd[1] = (baud >> 0) & 0xFF; /* set baud[0] */
1196 cmd[2] = (baud >> 8) & 0xFF; /* set baud[8] */
1197 cmd[3] = (baud >> 16) & 0xFF; /* set baud[16] */
1198 cmd[4] = (baud >> 24) & 0xFF; /* set baud[24] */
1199 if (a_ch9121x_write_check(handle, cmd, 5,
1200 CH9121X_UART_PRE_DELAY, 1000) != 0) /* write dest port */
1201 {
1202 return 1; /* return error */
1203 }
1204
1205 return 0; /* success return 0 */
1206}
1207
1220uint8_t ch9121x_get_uart_baud(ch9121x_handle_t *handle, ch9121x_port_t port, uint32_t *baud)
1221{
1222 uint8_t cmd;
1223 uint8_t buf[4];
1224
1225 if (handle == NULL) /* check handle */
1226 {
1227 return 2; /* return error */
1228 }
1229 if (handle->inited != 1) /* check handle initialization */
1230 {
1231 return 3; /* return error */
1232 }
1233
1234 if (port == CH9121X_PORT1) /* port1 */
1235 {
1236 cmd = CH9121X_CMD_PORT1_GET_BAUD; /* get port1 baud */
1237 }
1238 else /* port2 */
1239 {
1240 cmd = CH9121X_CMD_PORT2_GET_BAUD; /* get port2 baud */
1241 }
1242 if (a_ch9121x_write_read(handle, &cmd, 1, buf, 4,
1243 CH9121X_UART_PRE_DELAY, 1000) != 0) /* get dest port */
1244 {
1245 return 1; /* return error */
1246 }
1247 *baud = (uint32_t)(((uint32_t)buf[0] << 0) | ((uint32_t)buf[1] << 8) |
1248 ((uint32_t)buf[2] << 16) | ((uint32_t)buf[3] << 24)); /* get baud */
1249
1250 return 0; /* success return 0 */
1251}
1252
1267uint8_t ch9121x_set_uart_config(ch9121x_handle_t *handle, ch9121x_port_t port, uint8_t data_bit, ch9121x_parity_t parity, uint8_t stop_bit)
1268{
1269 uint8_t cmd[4];
1270
1271 if (handle == NULL) /* check handle */
1272 {
1273 return 2; /* return error */
1274 }
1275 if (handle->inited != 1) /* check handle initialization */
1276 {
1277 return 3; /* return error */
1278 }
1279
1280 if (port == CH9121X_PORT1) /* port1 */
1281 {
1282 cmd[0] = CH9121X_CMD_PORT1_SET_CONFIG; /* set port1 config */
1283 }
1284 else /* port2 */
1285 {
1286 cmd[0] = CH9121X_CMD_PORT2_SET_CONFIG; /* set port2 config */
1287 }
1288 cmd[1] = stop_bit; /* set stop bit */
1289 cmd[2] = parity; /* set parity */
1290 cmd[3] = data_bit; /* set data bit */
1291 if (a_ch9121x_write_check(handle, cmd, 4,
1292 CH9121X_UART_PRE_DELAY, 1000) != 0) /* write dest port */
1293 {
1294 return 1; /* return error */
1295 }
1296
1297 return 0; /* success return 0 */
1298}
1299
1314uint8_t ch9121x_get_uart_config(ch9121x_handle_t *handle, ch9121x_port_t port, uint8_t *data_bit, ch9121x_parity_t *parity, uint8_t *stop_bit)
1315{
1316 uint8_t cmd;
1317 uint8_t buf[3];
1318
1319 if (handle == NULL) /* check handle */
1320 {
1321 return 2; /* return error */
1322 }
1323 if (handle->inited != 1) /* check handle initialization */
1324 {
1325 return 3; /* return error */
1326 }
1327
1328 if (port == CH9121X_PORT1) /* port1 */
1329 {
1330 cmd = CH9121X_CMD_PORT1_GET_CONFIG; /* get port1 config */
1331 }
1332 else /* port2 */
1333 {
1334 cmd = CH9121X_CMD_PORT2_GET_CONFIG; /* get port2 config */
1335 }
1336 if (a_ch9121x_write_read(handle, &cmd, 1, buf, 3,
1337 CH9121X_UART_PRE_DELAY, 1000) != 0) /* get dest port */
1338 {
1339 return 1; /* return error */
1340 }
1341 *stop_bit = buf[0]; /* get stop bit */
1342 *parity = (ch9121x_parity_t)buf[1]; /* get parity */
1343 *data_bit = buf[2]; /* get data bit */
1344
1345 return 0; /* success return 0 */
1346}
1347
1360uint8_t ch9121x_set_uart_timeout(ch9121x_handle_t *handle, ch9121x_port_t port, uint8_t timeout)
1361{
1362 uint8_t cmd[5];
1363
1364 if (handle == NULL) /* check handle */
1365 {
1366 return 2; /* return error */
1367 }
1368 if (handle->inited != 1) /* check handle initialization */
1369 {
1370 return 3; /* return error */
1371 }
1372
1373 if (port == CH9121X_PORT1) /* port1 */
1374 {
1375 cmd[0] = CH9121X_CMD_PORT1_SET_TIMEOUT; /* set port1 timeout */
1376 }
1377 else /* port2 */
1378 {
1379 cmd[0] = CH9121X_CMD_PORT2_SET_TIMEOUT; /* set port2 timeout */
1380 }
1381 cmd[1] = timeout; /* set timeout */
1382 cmd[2] = 0x00; /* set 0x00 */
1383 cmd[3] = 0x00; /* set 0x00 */
1384 cmd[4] = 0x00; /* set 0x00 */
1385 if (a_ch9121x_write_check(handle, cmd, 5,
1386 CH9121X_UART_PRE_DELAY, 1000) != 0) /* write uart timeout */
1387 {
1388 return 1; /* return error */
1389 }
1390
1391 return 0; /* success return 0 */
1392}
1393
1406uint8_t ch9121x_get_uart_timeout(ch9121x_handle_t *handle, ch9121x_port_t port, uint8_t *timeout)
1407{
1408 uint8_t cmd;
1409
1410 if (handle == NULL) /* check handle */
1411 {
1412 return 2; /* return error */
1413 }
1414 if (handle->inited != 1) /* check handle initialization */
1415 {
1416 return 3; /* return error */
1417 }
1418
1419 if (port == CH9121X_PORT1) /* port1 */
1420 {
1421 cmd = CH9121X_CMD_PORT1_GET_TIMEOUT; /* get port1 timeout */
1422 }
1423 else /* port2 */
1424 {
1425 cmd = CH9121X_CMD_PORT2_GET_TIMEOUT; /* get port2 timeout */
1426 }
1427 if (a_ch9121x_write_read(handle, &cmd, 1, timeout, 1,
1428 CH9121X_UART_PRE_DELAY, 1000) != 0) /* get uart timeout */
1429 {
1430 return 1; /* return error */
1431 }
1432
1433 return 0; /* success return 0 */
1434}
1435
1447uint8_t ch9121x_uart_timeout_convert_to_register(ch9121x_handle_t *handle, uint16_t ms, uint8_t *reg)
1448{
1449 if (handle == NULL) /* check handle */
1450 {
1451 return 2; /* return error */
1452 }
1453 if (handle->inited != 1) /* check handle initialization */
1454 {
1455 return 3; /* return error */
1456 }
1457
1458 *reg = (uint8_t)(ms / 5); /* convert real data to register data */
1459
1460 return 0; /* success return 0 */
1461}
1462
1474uint8_t ch9121x_uart_timeout_convert_to_data(ch9121x_handle_t *handle, uint8_t reg, uint16_t *ms)
1475{
1476 if (handle == NULL) /* check handle */
1477 {
1478 return 2; /* return error */
1479 }
1480 if (handle->inited != 1) /* check handle initialization */
1481 {
1482 return 3; /* return error */
1483 }
1484
1485 *ms = reg * 5; /* convert raw data to real data */
1486
1487 return 0; /* success return 0 */
1488}
1489
1503{
1504 uint8_t cmd[2];
1505
1506 if (handle == NULL) /* check handle */
1507 {
1508 return 2; /* return error */
1509 }
1510 if (handle->inited != 1) /* check handle initialization */
1511 {
1512 return 3; /* return error */
1513 }
1514
1515 if (port == CH9121X_PORT1) /* port1 */
1516 {
1517 cmd[0] = CH9121X_CMD_PORT1_RANDOM_PORT; /* set port1 random */
1518 }
1519 else /* port2 */
1520 {
1521 cmd[0] = CH9121X_CMD_PORT2_RANDOM_PORT ; /* set port2 random */
1522 }
1523 cmd[1] = enable; /* set bool */
1524 if (a_ch9121x_write_check(handle, cmd, 2,
1525 CH9121X_UART_PRE_DELAY, 1000) != 0) /* write source port random */
1526 {
1527 return 1; /* return error */
1528 }
1529
1530 return 0; /* success return 0 */
1531}
1532
1546{
1547 uint8_t cmd[5];
1548
1549 if (handle == NULL) /* check handle */
1550 {
1551 return 2; /* return error */
1552 }
1553 if (handle->inited != 1) /* check handle initialization */
1554 {
1555 return 3; /* return error */
1556 }
1557
1558 if (port == CH9121X_PORT1) /* port1 */
1559 {
1560 cmd[0] = CH9121X_CMD_PORT1_LEN; /* set port1 uart buffer */
1561 }
1562 else /* port2 */
1563 {
1564 cmd[0] = CH9121X_CMD_PORT2_LEN ; /* set port2 uart buffer */
1565 }
1566 cmd[1] = (len >> 0) & 0xFF; /* set len[0] */
1567 cmd[2] = (len >> 8) & 0xFF; /* set len[8] */
1568 cmd[3] = (len >> 16) & 0xFF; /* set len[16] */
1569 cmd[4] = (len >> 24) & 0xFF; /* set len[24] */
1570 if (a_ch9121x_write_check(handle, cmd, 5,
1571 CH9121X_UART_PRE_DELAY, 1000) != 0) /* write uart buffer */
1572 {
1573 return 1; /* return error */
1574 }
1575
1576 return 0; /* success return 0 */
1577}
1578
1592{
1593 uint8_t cmd[2];
1594
1595 if (handle == NULL) /* check handle */
1596 {
1597 return 2; /* return error */
1598 }
1599 if (handle->inited != 1) /* check handle initialization */
1600 {
1601 return 3; /* return error */
1602 }
1603
1604 if (port == CH9121X_PORT1) /* port1 */
1605 {
1606 cmd[0] = CH9121X_CMD_PORT1_FLUSH; /* set port1 flush */
1607 }
1608 else /* port2 */
1609 {
1610 cmd[0] = CH9121X_CMD_PORT2_FLUSH ; /* set port2 flush */
1611 }
1612 cmd[1] = enable; /* set bool */
1613 if (a_ch9121x_write_check(handle, cmd, 2,
1614 CH9121X_UART_PRE_DELAY, 1000) != 0) /* write flush */
1615 {
1616 return 1; /* return error */
1617 }
1618
1619 return 0; /* success return 0 */
1620}
1621
1634{
1635 uint8_t cmd[2];
1636
1637 if (handle == NULL) /* check handle */
1638 {
1639 return 2; /* return error */
1640 }
1641 if (handle->inited != 1) /* check handle initialization */
1642 {
1643 return 3; /* return error */
1644 }
1645
1646 cmd[0] = CH9121X_CMD_PORT2_ENABLE; /* enable port2 */
1647 cmd[1] = enable; /* set bool */
1648 if (a_ch9121x_write_check(handle, cmd, 2,
1649 CH9121X_UART_PRE_DELAY, 1000) != 0) /* write enable */
1650 {
1651 return 1; /* return error */
1652 }
1653
1654 return 0; /* success return 0 */
1655}
1656
1669{
1670 uint8_t cmd[2];
1671
1672 if (handle == NULL) /* check handle */
1673 {
1674 return 2; /* return error */
1675 }
1676 if (handle->inited != 1) /* check handle initialization */
1677 {
1678 return 3; /* return error */
1679 }
1680
1681 cmd[0] = CH9121X_CMD_DISCONNECT; /* set disconnect */
1682 cmd[1] = enable; /* set bool */
1683 if (a_ch9121x_write_check(handle, cmd, 2,
1684 CH9121X_UART_PRE_DELAY, 1000) != 0) /* write disconnect */
1685 {
1686 return 1; /* return error */
1687 }
1688
1689 return 0; /* success return 0 */
1690}
1691
1703uint8_t ch9121x_set_domain(ch9121x_handle_t *handle, char *domain)
1704{
1705 uint8_t cmd[29];
1706
1707 if (handle == NULL) /* check handle */
1708 {
1709 return 2; /* return error */
1710 }
1711 if (handle->inited != 1) /* check handle initialization */
1712 {
1713 return 3; /* return error */
1714 }
1715 if (strlen(domain) > 28) /* check domain */
1716 {
1717 handle->debug_print("ch9121x: domain > 28.\n"); /* domain > 28 */
1718
1719 return 4; /* return error */
1720 }
1721
1722 cmd[0] = CH9121X_CMD_PORT1_DOMAIN ; /* set domain */
1723 memcpy(&cmd[1], (uint8_t *)domain, strlen(domain));
1724 if (a_ch9121x_write_check(handle, cmd,
1725 (uint16_t)(strlen(domain) + 1),
1726 CH9121X_UART_PRE_DELAY, 1000) != 0) /* write domain */
1727 {
1728 return 1; /* return error */
1729 }
1730
1731 return 0; /* success return 0 */
1732}
1733
1745uint8_t ch9121x_set_mac(ch9121x_handle_t *handle, uint8_t mac[6])
1746{
1747 uint8_t cmd[7];
1748
1749 if (handle == NULL) /* check handle */
1750 {
1751 return 2; /* return error */
1752 }
1753 if (handle->inited != 1) /* check handle initialization */
1754 {
1755 return 3; /* return error */
1756 }
1757
1758 cmd[0] = CH9121X_CMD_SET_MAC_ADDR; /* set mac address */
1759 cmd[1] = mac[0]; /* set mac 0 */
1760 cmd[2] = mac[1]; /* set mac 1 */
1761 cmd[3] = mac[2]; /* set mac 2 */
1762 cmd[4] = mac[3]; /* set mac 3 */
1763 cmd[5] = mac[4]; /* set mac 4 */
1764 cmd[6] = mac[5]; /* set mac 5 */
1765 if (a_ch9121x_write_check(handle, cmd, 7,
1766 CH9121X_UART_PRE_DELAY, 1000) != 0) /* write command */
1767 {
1768 return 1; /* return error */
1769 }
1770
1771 return 0; /* success return 0 */
1772}
1773
1785{
1786 uint8_t cmd[1];
1787
1788 if (handle == NULL) /* check handle */
1789 {
1790 return 2; /* return error */
1791 }
1792 if (handle->inited != 1) /* check handle initialization */
1793 {
1794 return 3; /* return error */
1795 }
1796
1797 cmd[0] = CH9121X_CMD_CLEAR_MAC_ADDR; /* clear mac address */
1798 if (a_ch9121x_write_check(handle, cmd, 1,
1799 CH9121X_UART_PRE_DELAY, 1000) != 0) /* write command */
1800 {
1801 return 1; /* return error */
1802 }
1803
1804 return 0; /* success return 0 */
1805}
1806
1819{
1820 uint8_t cmd[2];
1821
1822 if (handle == NULL) /* check handle */
1823 {
1824 return 2; /* return error */
1825 }
1826 if (handle->inited != 1) /* check handle initialization */
1827 {
1828 return 3; /* return error */
1829 }
1830
1831 cmd[0] = CH9121X_CMD_SET_ETH_CFG_ENABLE; /* set eth cfg enable */
1832 cmd[1] = (uint8_t)enable; /* bool value */
1833 if (a_ch9121x_write_check(handle, cmd, 2,
1834 CH9121X_UART_PRE_DELAY, 1000) != 0) /* write command */
1835 {
1836 return 1; /* return error */
1837 }
1838
1839 return 0; /* success return 0 */
1840}
1841
1854{
1855 uint8_t cmd;
1856 uint8_t buf[1];
1857
1858 if (handle == NULL) /* check handle */
1859 {
1860 return 2; /* return error */
1861 }
1862 if (handle->inited != 1) /* check handle initialization */
1863 {
1864 return 3; /* return error */
1865 }
1866
1867 cmd = CH9121X_CMD_GET_ETH_CFG_STATUS; /* get eth cfg enable */
1868 if (a_ch9121x_write_read(handle, &cmd, 1, buf, 1,
1869 CH9121X_UART_PRE_DELAY, 1000) != 0) /* get data */
1870 {
1871 return 1; /* return error */
1872 }
1873 *enable = (ch9121x_bool_t)buf[0]; /* set bool value */
1874
1875 return 0; /* success return 0 */
1876}
1877
1890{
1891 uint8_t cmd[2];
1892
1893 if (handle == NULL) /* check handle */
1894 {
1895 return 2; /* return error */
1896 }
1897 if (handle->inited != 1) /* check handle initialization */
1898 {
1899 return 3; /* return error */
1900 }
1901
1902 cmd[0] = CH9121X_CMD_SET_UART_CLOCK_MODE; /* set uart clock mode */
1903 cmd[1] = (uint8_t)mode; /* set mode */
1904 if (a_ch9121x_write_check(handle, cmd, 2,
1905 CH9121X_UART_PRE_DELAY, 1000) != 0) /* write command */
1906 {
1907 return 1; /* return error */
1908 }
1909
1910 return 0; /* success return 0 */
1911}
1912
1925{
1926 uint8_t cmd;
1927 uint8_t buf[1];
1928
1929 if (handle == NULL) /* check handle */
1930 {
1931 return 2; /* return error */
1932 }
1933 if (handle->inited != 1) /* check handle initialization */
1934 {
1935 return 3; /* return error */
1936 }
1937
1938 cmd = CH9121X_CMD_GET_UART_CLOCK_MODE; /* get uart clock mode */
1939 if (a_ch9121x_write_read(handle, &cmd, 1, buf, 1,
1940 CH9121X_UART_PRE_DELAY, 1000) != 0) /* get data */
1941 {
1942 return 1; /* return error */
1943 }
1944 *mode = (ch9121x_uart_clock_mode_t)buf[0]; /* set mode */
1945
1946 return 0; /* success return 0 */
1947}
1948
1962{
1963 uint8_t cmd;
1964 uint8_t buf[1];
1965
1966 if (handle == NULL) /* check handle */
1967 {
1968 return 2; /* return error */
1969 }
1970 if (handle->inited != 1) /* check handle initialization */
1971 {
1972 return 3; /* return error */
1973 }
1974
1975 if (port == CH9121X_PORT1) /* port1 */
1976 {
1977 cmd = CH9121X_CMD_PORT1_GET_RANDOM; /* get port1 random */
1978 }
1979 else /* port2 */
1980 {
1981 cmd = CH9121X_CMD_PORT2_GET_RANDOM; /* get port2 random */
1982 }
1983 if (a_ch9121x_write_read(handle, &cmd, 1, buf, 1,
1984 CH9121X_UART_PRE_DELAY, 1000) != 0) /* get data */
1985 {
1986 return 1; /* return error */
1987 }
1988 *enable = (ch9121x_bool_t)buf[0]; /* set bool value */
1989
1990 return 0; /* success return 0 */
1991}
1992
2005{
2006 uint8_t cmd;
2007 uint8_t buf[1];
2008
2009 if (handle == NULL) /* check handle */
2010 {
2011 return 2; /* return error */
2012 }
2013 if (handle->inited != 1) /* check handle initialization */
2014 {
2015 return 3; /* return error */
2016 }
2017
2018 cmd = CH9121X_CMD_GET_PHY_STATUS; /* get phy status */
2019 if (a_ch9121x_write_read(handle, &cmd, 1, buf, 1,
2020 CH9121X_UART_PRE_DELAY, 1000) != 0) /* get data */
2021 {
2022 return 1; /* return error */
2023 }
2024 if (buf[0] == (uint8_t)CH9121X_PHY_STATUS_DISCONNECTED) /* disconnected */
2025 {
2026 *status = CH9121X_PHY_STATUS_DISCONNECTED; /* set status */
2027 }
2028 else if (buf[0] == (uint8_t)CH9121X_PHY_STATUS_10M_FULL_DUPLEX) /* 10 mbps full duplex */
2029 {
2030 *status = CH9121X_PHY_STATUS_10M_FULL_DUPLEX; /* set status */
2031 }
2032 else if (buf[0] == (uint8_t)CH9121X_PHY_STATUS_10M_HALF_DUPLEX) /* 10 mbps half duplex */
2033 {
2034 *status = CH9121X_PHY_STATUS_10M_HALF_DUPLEX; /* set status */
2035 }
2036 else if (buf[0] == (uint8_t)CH9121X_PHY_STATUS_100M_FULL_DUPLEX) /* 100 mbps full duplex */
2037 {
2038 *status = CH9121X_PHY_STATUS_100M_FULL_DUPLEX; /* set status */
2039 }
2040 else if (buf[0] == (uint8_t)CH9121X_PHY_STATUS_100M_HALF_DUPLEX) /* 100 mbps half duplex */
2041 {
2042 *status = CH9121X_PHY_STATUS_100M_HALF_DUPLEX; /* set status */
2043 }
2044 else /* unknown */
2045 {
2046 *status = CH9121X_PHY_STATUS_UNKNOWN; /* set status */
2047 }
2048
2049 return 0; /* success return 0 */
2050}
2051
2064{
2065 uint8_t cmd;
2066 uint8_t buf[1];
2067
2068 if (handle == NULL) /* check handle */
2069 {
2070 return 2; /* return error */
2071 }
2072 if (handle->inited != 1) /* check handle initialization */
2073 {
2074 return 3; /* return error */
2075 }
2076
2077 cmd = CH9121X_CMD_GET_PORT1_2_LINKDOWN; /* get port 1 and 2 linkdown */
2078 if (a_ch9121x_write_read(handle, &cmd, 1, buf, 1,
2079 CH9121X_UART_PRE_DELAY, 1000) != 0) /* get data */
2080 {
2081 return 1; /* return error */
2082 }
2083 *enable = (ch9121x_bool_t)buf[0]; /* set bool value */
2084
2085 return 0; /* success return 0 */
2086}
2087
2101{
2102 uint8_t cmd;
2103 uint8_t buf[4];
2104
2105 if (handle == NULL) /* check handle */
2106 {
2107 return 2; /* return error */
2108 }
2109 if (handle->inited != 1) /* check handle initialization */
2110 {
2111 return 3; /* return error */
2112 }
2113
2114 if (port == CH9121X_PORT1) /* port1 */
2115 {
2116 cmd = CH9121X_CMD_PORT1_GET_UART_PACK_LEN; /* get port1 uart pack len */
2117 }
2118 else /* port2 */
2119 {
2120 cmd = CH9121X_CMD_PORT2_GET_UART_PACK_LEN; /* get port2 uart pack len */
2121 }
2122 if (a_ch9121x_write_read(handle, &cmd, 1, buf, 4,
2123 CH9121X_UART_PRE_DELAY, 1000) != 0) /* get data */
2124 {
2125 return 1; /* return error */
2126 }
2127 *len = (uint32_t)buf[3] << 24 | (uint32_t)buf[2] << 16 |
2128 (uint32_t)buf[1] << 8 | (uint32_t)buf[0] << 0; /* set length */
2129
2130 return 0; /* success return 0 */
2131}
2132
2146{
2147 uint8_t cmd;
2148 uint8_t buf[1];
2149
2150 if (handle == NULL) /* check handle */
2151 {
2152 return 2; /* return error */
2153 }
2154 if (handle->inited != 1) /* check handle initialization */
2155 {
2156 return 3; /* return error */
2157 }
2158
2159 if (port == CH9121X_PORT1) /* port1 */
2160 {
2161 cmd = CH9121X_CMD_PORT1_GET_EMPTY; /* get port1 empty */
2162 }
2163 else /* port2 */
2164 {
2165 cmd = CH9121X_CMD_PORT2_GET_EMPTY; /* get port2 empty */
2166 }
2167 if (a_ch9121x_write_read(handle, &cmd, 1, buf, 1,
2168 CH9121X_UART_PRE_DELAY, 1000) != 0) /* get data */
2169 {
2170 return 1; /* return error */
2171 }
2172 *enable = (ch9121x_bool_t)buf[0]; /* set bool value */
2173
2174 return 0; /* success return 0 */
2175}
2176
2189{
2190 uint8_t cmd;
2191 uint8_t buf[1];
2192
2193 if (handle == NULL) /* check handle */
2194 {
2195 return 2; /* return error */
2196 }
2197 if (handle->inited != 1) /* check handle initialization */
2198 {
2199 return 3; /* return error */
2200 }
2201
2202 cmd = CH9121X_CMD_GET_DHCP_ENABLE; /* get dhcp enable */
2203 if (a_ch9121x_write_read(handle, &cmd, 1, buf, 1,
2204 CH9121X_UART_PRE_DELAY, 1000) != 0) /* get data */
2205 {
2206 return 1; /* return error */
2207 }
2208 *enable = (ch9121x_bool_t)buf[0]; /* set bool value */
2209
2210 return 0; /* success return 0 */
2211}
2212
2226{
2227 uint8_t cmd[3];
2228
2229 if (handle == NULL) /* check handle */
2230 {
2231 return 2; /* return error */
2232 }
2233 if (handle->inited != 1) /* check handle initialization */
2234 {
2235 return 3; /* return error */
2236 }
2237 if (t > 7) /* check t */
2238 {
2239 handle->debug_print("ch9121x: t > 7.\n"); /* t > 7 */
2240
2241 return 4; /* return error */
2242 }
2243
2244 cmd[0] = (CH9121X_CMD2_SET_TCP_RETRY_MODE >> 8) & 0xFF; /* set msb */
2245 cmd[1] = (CH9121X_CMD2_SET_TCP_RETRY_MODE >> 0) & 0xFF; /* set lsb */
2246 cmd[2] = (uint8_t)t; /* set time */
2247 if (a_ch9121x_write_check(handle, cmd, 3,
2248 CH9121X_UART_PRE_DELAY, 1000) != 0) /* write command */
2249 {
2250 return 1; /* return error */
2251 }
2252
2253 return 0; /* success return 0 */
2254}
2255
2268{
2269 uint8_t cmd[2];
2270 uint8_t buf[1];
2271
2272 if (handle == NULL) /* check handle */
2273 {
2274 return 2; /* return error */
2275 }
2276 if (handle->inited != 1) /* check handle initialization */
2277 {
2278 return 3; /* return error */
2279 }
2280
2281 cmd[0] = (CH9121X_CMD2_GET_TCP_RETRY_MODE >> 8) & 0xFF; /* set msb */
2282 cmd[1] = (CH9121X_CMD2_GET_TCP_RETRY_MODE >> 0) & 0xFF; /* set lsb */
2283 if (a_ch9121x_write_read(handle, cmd, 2, buf, 1,
2284 CH9121X_UART_PRE_DELAY, 1000) != 0) /* get data */
2285 {
2286 return 1; /* return error */
2287 }
2288 *t = buf[0]; /* set time */
2289
2290 return 0; /* success return 0 */
2291}
2292
2305{
2306 uint8_t cmd[3];
2307
2308 if (handle == NULL) /* check handle */
2309 {
2310 return 2; /* return error */
2311 }
2312 if (handle->inited != 1) /* check handle initialization */
2313 {
2314 return 3; /* return error */
2315 }
2316
2317 cmd[0] = (CH9121X_CMD2_FLOW_CONTROL_ENABLE >> 8) & 0xFF; /* set msb */
2318 cmd[1] = (CH9121X_CMD2_FLOW_CONTROL_ENABLE >> 0) & 0xFF; /* set lsb */
2319 cmd[2] = (uint8_t)enable; /* set bool value */
2320 if (a_ch9121x_write_check(handle, cmd, 3,
2321 CH9121X_UART_PRE_DELAY, 1000) != 0) /* write command */
2322 {
2323 return 1; /* return error */
2324 }
2325
2326 return 0; /* success return 0 */
2327}
2328
2341{
2342 uint8_t cmd[2];
2343 uint8_t buf[1];
2344
2345 if (handle == NULL) /* check handle */
2346 {
2347 return 2; /* return error */
2348 }
2349 if (handle->inited != 1) /* check handle initialization */
2350 {
2351 return 3; /* return error */
2352 }
2353
2354 cmd[0] = (CH9121X_CMD2_GET_FLOW_CONTROL_ENABLE >> 8) & 0xFF; /* set msb */
2355 cmd[1] = (CH9121X_CMD2_GET_FLOW_CONTROL_ENABLE >> 0) & 0xFF; /* set lsb */
2356 if (a_ch9121x_write_read(handle, cmd, 2, buf, 1,
2357 CH9121X_UART_PRE_DELAY, 1000) != 0) /* get data */
2358 {
2359 return 1; /* return error */
2360 }
2361 *enable = (ch9121x_bool_t)buf[0]; /* set bool value */
2362
2363 return 0; /* success return 0 */
2364}
2365
2378uint8_t ch9121x_set_arp_retry(ch9121x_handle_t *handle, uint8_t period, uint8_t times)
2379{
2380 uint8_t cmd[4];
2381
2382 if (handle == NULL) /* check handle */
2383 {
2384 return 2; /* return error */
2385 }
2386 if (handle->inited != 1) /* check handle initialization */
2387 {
2388 return 3; /* return error */
2389 }
2390
2391 cmd[0] = (CH9121X_CMD2_SET_ARP_RETRY >> 8) & 0xFF; /* set msb */
2392 cmd[1] = (CH9121X_CMD2_SET_ARP_RETRY >> 0) & 0xFF; /* set lsb */
2393 cmd[2] = period; /* set period */
2394 cmd[3] = times; /* set times */
2395 if (a_ch9121x_write_check(handle, cmd, 4,
2396 CH9121X_UART_PRE_DELAY, 1000) != 0) /* write command */
2397 {
2398 return 1; /* return error */
2399 }
2400
2401 return 0; /* success return 0 */
2402}
2403
2415uint8_t ch9121x_tcp_retry_time_convert_to_register(ch9121x_handle_t *handle, uint16_t ms, uint8_t *reg)
2416{
2417 if (handle == NULL) /* check handle */
2418 {
2419 return 2; /* return error */
2420 }
2421 if (handle->inited != 1) /* check handle initialization */
2422 {
2423 return 3; /* return error */
2424 }
2425
2426 *reg = (uint8_t)(ms / 500); /* convert real data to register data */
2427
2428 return 0; /* success return 0 */
2429}
2430
2442uint8_t ch9121x_tcp_retry_time_convert_to_data(ch9121x_handle_t *handle, uint8_t reg, uint16_t *ms)
2443{
2444 if (handle == NULL) /* check handle */
2445 {
2446 return 2; /* return error */
2447 }
2448 if (handle->inited != 1) /* check handle initialization */
2449 {
2450 return 3; /* return error */
2451 }
2452
2453 *ms = reg * 500; /* convert raw data to real data */
2454
2455 return 0; /* success return 0 */
2456}
2457
2469uint8_t ch9121x_arp_retry_period_convert_to_register(ch9121x_handle_t *handle, uint16_t ms, uint8_t *reg)
2470{
2471 if (handle == NULL) /* check handle */
2472 {
2473 return 2; /* return error */
2474 }
2475 if (handle->inited != 1) /* check handle initialization */
2476 {
2477 return 3; /* return error */
2478 }
2479
2480 *reg = (uint8_t)(ms / 100); /* convert real data to register data */
2481
2482 return 0; /* success return 0 */
2483}
2484
2496uint8_t ch9121x_arp_retry_period_convert_to_data(ch9121x_handle_t *handle, uint8_t reg, uint16_t *ms)
2497{
2498 if (handle == NULL) /* check handle */
2499 {
2500 return 2; /* return error */
2501 }
2502 if (handle->inited != 1) /* check handle initialization */
2503 {
2504 return 3; /* return error */
2505 }
2506
2507 *ms = reg * 100; /* convert raw data to real data */
2508
2509 return 0; /* success return 0 */
2510}
2511
2526{
2527 if (handle == NULL) /* check handle */
2528 {
2529 return 2; /* return error */
2530 }
2531 if (handle->debug_print == NULL) /* check debug_print */
2532 {
2533 return 3; /* return error */
2534 }
2535 if (handle->uart_init == NULL) /* check uart_init */
2536 {
2537 handle->debug_print("ch9121x: uart_init is null.\n"); /* uart_init is null */
2538
2539 return 3; /* return error */
2540 }
2541 if (handle->uart_deinit == NULL) /* check uart_deinit */
2542 {
2543 handle->debug_print("ch9121x: uart_deinit is null.\n"); /* uart_deinit is null */
2544
2545 return 3; /* return error */
2546 }
2547 if (handle->uart_read == NULL) /* check uart_read */
2548 {
2549 handle->debug_print("ch9121x: uart_read is null.\n"); /* uart_read is null */
2550
2551 return 3; /* return error */
2552 }
2553 if (handle->uart_write == NULL) /* check uart_write */
2554 {
2555 handle->debug_print("ch9121x: uart_write is null.\n"); /* uart_write is null */
2556
2557 return 3; /* return error */
2558 }
2559 if (handle->uart_flush == NULL) /* check uart_flush */
2560 {
2561 handle->debug_print("ch9121x: uart_flush is null.\n"); /* uart_flush is null */
2562
2563 return 3; /* return error */
2564 }
2565 if (handle->delay_ms == NULL) /* check delay_ms */
2566 {
2567 handle->debug_print("ch9121x: delay_ms is null.\n"); /* delay_ms is null */
2568
2569 return 3; /* return error */
2570 }
2571 if (handle->reset_gpio_init == NULL) /* check reset_gpio_init */
2572 {
2573 handle->debug_print("ch9121x: reset_gpio_init is null.\n"); /* reset_gpio_init is null */
2574
2575 return 3; /* return error */
2576 }
2577 if (handle->reset_gpio_deinit == NULL) /* check reset_gpio_deinit */
2578 {
2579 handle->debug_print("ch9121x: reset_gpio_deinit is null.\n"); /* reset_gpio_deinit is null */
2580
2581 return 3; /* return error */
2582 }
2583 if (handle->reset_gpio_write == NULL) /* check reset_gpio_write */
2584 {
2585 handle->debug_print("ch9121x: reset_gpio_write is null.\n"); /* reset_gpio_write is null */
2586
2587 return 3; /* return error */
2588 }
2589 if (handle->cfg_gpio_init == NULL) /* check cfg_gpio_init */
2590 {
2591 handle->debug_print("ch9121x: cfg_gpio_init is null.\n"); /* cfg_gpio_init is null */
2592
2593 return 3; /* return error */
2594 }
2595 if (handle->cfg_gpio_deinit == NULL) /* check cfg_gpio_deinit */
2596 {
2597 handle->debug_print("ch9121x: cfg_gpio_deinit is null.\n"); /* cfg_gpio_deinit is null */
2598
2599 return 3; /* return error */
2600 }
2601 if (handle->cfg_gpio_write == NULL) /* check cfg_gpio_write */
2602 {
2603 handle->debug_print("ch9121x: cfg_gpio_write is null.\n"); /* cfg_gpio_write is null */
2604
2605 return 3; /* return error */
2606 }
2607
2608 if (handle->uart_init() != 0) /* uart init */
2609 {
2610 handle->debug_print("ch9121x: uart init failed.\n"); /* uart init failed */
2611
2612 return 1; /* return error */
2613 }
2614 if (handle->reset_gpio_init() != 0) /* reset gpio init */
2615 {
2616 handle->debug_print("ch9121x: reset gpio init failed.\n"); /* reset gpio init failed */
2617 (void)handle->uart_deinit(); /* uart deinit */
2618
2619 return 4; /* return error */
2620 }
2621 if (handle->cfg_gpio_init() != 0) /* cfg gpio init */
2622 {
2623 handle->debug_print("ch9121x: cfg gpio init failed.\n"); /* cfg gpio init failed */
2624 (void)handle->uart_deinit(); /* uart deinit */
2625 (void)handle->reset_gpio_deinit(); /* reset gpio deinit */
2626
2627 return 5; /* return error */
2628 }
2629 if (handle->reset_gpio_write(0) != 0) /* set low */
2630 {
2631 handle->debug_print("ch9121x: cfg gpio write failed.\n"); /* cfg gpio write failed */
2632 (void)handle->uart_deinit(); /* uart deinit */
2633 (void)handle->reset_gpio_deinit(); /* reset gpio deinit */
2634 (void)handle->cfg_gpio_deinit(); /* cfg gpio deinit */
2635
2636 return 6; /* return error */
2637 }
2638 handle->delay_ms(10); /* delay 10ms */
2639 if (handle->reset_gpio_write(1) != 0) /* set high */
2640 {
2641 handle->debug_print("ch9121x: cfg gpio write failed.\n"); /* cfg gpio write failed */
2642 (void)handle->uart_deinit(); /* uart deinit */
2643 (void)handle->reset_gpio_deinit(); /* reset gpio deinit */
2644 (void)handle->cfg_gpio_deinit(); /* cfg gpio deinit */
2645
2646 return 6; /* return error */
2647 }
2648 handle->delay_ms(1000); /* delay 1000ms */
2649 handle->inited = 1; /* flag finish initialization */
2650
2651 return 0; /* success return 0 */
2652}
2653
2668{
2669 uint8_t cmd;
2670
2671 if (handle == NULL) /* check handle */
2672 {
2673 return 2; /* return error */
2674 }
2675 if (handle->inited != 1) /* check handle initialization */
2676 {
2677 return 3; /* return error */
2678 }
2679
2680 cmd = CH9121X_CMD_RESET; /* set reset */
2681 if (a_ch9121x_write_check(handle, &cmd, 1,
2682 CH9121X_UART_PRE_DELAY, 1000) != 0) /* reset */
2683 {
2684 return 4; /* return error */
2685 }
2686 handle->delay_ms(10); /* delay 10ms */
2687 if (handle->uart_deinit() != 0) /* uart deinit */
2688 {
2689 handle->debug_print("ch9121x: uart deinit failed.\n"); /* uart deinit failed */
2690
2691 return 1; /* return error */
2692 }
2693 if (handle->reset_gpio_deinit() != 0) /* reset gpio deinit */
2694 {
2695 handle->debug_print("ch9121x: reset gpio deinit failed.\n"); /* reset gpio deinit failed */
2696
2697 return 5; /* return error */
2698 }
2699 if (handle->cfg_gpio_deinit() != 0) /* cfg gpio deinit */
2700 {
2701 handle->debug_print("ch9121x: cfg gpio deinit failed.\n"); /* cfg gpio deinit failed */
2702
2703 return 6; /* return error */
2704 }
2705
2706 return 0; /* success return 0 */
2707}
2708
2721uint8_t ch9121x_write(ch9121x_handle_t *handle, uint8_t *buf, uint16_t len)
2722{
2723 if (handle == NULL) /* check handle */
2724 {
2725 return 2; /* return error */
2726 }
2727 if (handle->inited != 1) /* check handle initialization */
2728 {
2729 return 3; /* return error */
2730 }
2731
2732 if (handle->cfg_gpio_write(1) != 0) /* cfg gpio write */
2733 {
2734 handle->debug_print("ch9121x: cfg gpio write failed.\n"); /* cfg gpio write failed */
2735
2736 return 1; /* return error */
2737 }
2738 if (handle->uart_write(buf, len) != 0) /* uart write */
2739 {
2740 handle->debug_print("ch9121x:uart write failed.\n"); /* uart write failed */
2741
2742 return 1; /* return error */
2743 }
2744
2745 return 0; /* success return 0 */
2746}
2747
2760uint8_t ch9121x_read(ch9121x_handle_t *handle, uint8_t *buf, uint16_t *len)
2761{
2762 uint16_t l;
2763
2764 if (handle == NULL) /* check handle */
2765 {
2766 return 2; /* return error */
2767 }
2768 if (handle->inited != 1) /* check handle initialization */
2769 {
2770 return 3; /* return error */
2771 }
2772
2773 if (handle->cfg_gpio_write(1) != 0) /* cfg gpio write */
2774 {
2775 handle->debug_print("ch9121x: cfg gpio write failed.\n"); /* cfg gpio write failed */
2776
2777 return 1; /* return error */
2778 }
2779 l = handle->uart_read(buf, *len); /* uart read */
2780 *len = l; /* set data */
2781
2782 return 0; /* success return 0 */
2783}
2784
2802 uint8_t *param, uint16_t len,
2803 uint8_t *out, uint16_t out_len,
2804 uint16_t pre_delay, uint16_t timeout)
2805{
2806 if (handle == NULL) /* check handle */
2807 {
2808 return 2; /* return error */
2809 }
2810 if (handle->inited != 1) /* check handle initialization */
2811 {
2812 return 3; /* return error */
2813 }
2814
2815 if (a_ch9121x_write_read(handle, param, len,
2816 out, out_len,
2817 pre_delay, timeout) != 0) /* set command */
2818 {
2819 return 1; /* return error */
2820 }
2821
2822 return 0; /* success return 0 */
2823}
2824
2834{
2835 if (info == NULL) /* check handle */
2836 {
2837 return 2; /* return error */
2838 }
2839
2840 memset(info, 0, sizeof(ch9121x_info_t)); /* initialize ch9121x info structure */
2841 strncpy(info->chip_name, CHIP_NAME, 32); /* copy chip name */
2842 strncpy(info->manufacturer_name, MANUFACTURER_NAME, 32); /* copy manufacturer name */
2843 strncpy(info->interface, "UART", 8); /* copy interface name */
2844 info->supply_voltage_min_v = SUPPLY_VOLTAGE_MIN; /* set minimal supply voltage */
2845 info->supply_voltage_max_v = SUPPLY_VOLTAGE_MAX; /* set maximum supply voltage */
2846 info->max_current_ma = MAX_CURRENT; /* set maximum current */
2847 info->temperature_max = TEMPERATURE_MAX; /* set minimal temperature */
2848 info->temperature_min = TEMPERATURE_MIN; /* set maximum temperature */
2849 info->driver_version = DRIVER_VERSION; /* set driver version */
2850
2851 return 0; /* success return 0 */
2852}
#define CH9121X_CMD_PORT1_SET_DST_PORT
#define CH9121X_CMD_SET_MAC_ADDR
#define CH9121X_CMD_PORT1_DOMAIN
#define CH9121X_CMD_PORT1_SET_CONFIG
#define CH9121X_CMD_GET_NETMASK
#define CH9121X_CMD_MAC
#define CH9121X_CMD2_FLOW_CONTROL_ENABLE
#define CH9121X_CMD_PORT1_RANDOM_PORT
chip port extern command definition
#define CH9121X_CMD_GET_GATEWAY
#define CH9121X_CMD_SAVE_TO_EEPROM
#define CH9121X_CMD_PORT2_LEN
#define CH9121X_CMD_PORT1_SET_DST_IP
#define MAX_CURRENT
#define CH9121X_CMD2_GET_TCP_RETRY_MODE
#define CH9121X_CMD_SET_GATEWAY
#define CH9121X_CMD_PORT1_GET_RANDOM
#define CH9121X_CMD_PORT1_GET_UART_PACK_LEN
#define CH9121X_CMD_PORT2_GET_BAUD
#define CH9121X_CMD_EXIT
#define CH9121X_CMD_CHIP_VERSION
chip basic command definition
#define CH9121X_CMD_SET_ETH_CFG_ENABLE
#define CH9121X_CMD_PORT1_GET_STATUS
chip port command definition
#define CH9121X_CMD_PORT2_GET_UART_PACK_LEN
#define CH9121X_CMD_PORT1_GET_DST_PORT
#define CH9121X_CMD_PORT2_GET_RANDOM
#define CH9121X_CMD_PORT2_GET_TIMEOUT
#define CH9121X_CMD_PORT2_FLUSH
#define SUPPLY_VOLTAGE_MAX
#define CH9121X_CMD_PORT1_SET_MODE
#define CH9121X_CMD_PORT1_SET_BAUD
#define CH9121X_CMD_GET_ETH_CFG_STATUS
#define CH9121X_CMD_GET_UART_CLOCK_MODE
#define CH9121X_CMD_PORT2_GET_DST_IP
#define CH9121X_CMD_PORT2_GET_DST_PORT
#define CH9121X_CMD_PORT2_SET_PORT
#define CH9121X_CMD_PORT2_SET_TIMEOUT
#define CH9121X_CMD_PORT1_FLUSH
#define CH9121X_CMD2_SET_TCP_RETRY_MODE
chip port two bytes extern command definition
#define CH9121X_CMD2_SET_ARP_RETRY
#define CH9121X_CMD_GET_DHCP_ENABLE
#define CH9121X_CMD_PORT2_RANDOM_PORT
#define CH9121X_CMD_PORT1_GET_BAUD
#define TEMPERATURE_MAX
#define CH9121X_CMD_PORT1_SET_TIMEOUT
#define CH9121X_CMD_PORT2_SET_DST_PORT
#define CH9121X_CMD_PORT2_SET_BAUD
#define CH9121X_CMD_DHCP
#define CH9121X_CMD_PORT1_GET_DST_IP
#define MANUFACTURER_NAME
#define CH9121X_CMD_PORT2_GET_STATUS
#define TEMPERATURE_MIN
#define CH9121X_CMD_RESET
#define SUPPLY_VOLTAGE_MIN
#define CH9121X_CMD_PORT2_SET_MODE
#define CH9121X_CMD_PORT1_SET_PORT
#define CH9121X_CMD_PORT1_GET_TIMEOUT
#define CH9121X_CMD_GET_IP
#define CH9121X_CMD_PORT1_GET_EMPTY
#define CH9121X_CMD_PORT2_SET_CONFIG
#define CH9121X_CMD_GET_PHY_STATUS
#define CH9121X_CMD_PORT2_GET_EMPTY
#define CH9121X_CMD_DISCONNECT
#define CH9121X_CMD_SET_IP
#define CH9121X_CMD_PORT2_GET_PORT
#define CH9121X_CMD_PORT2_SET_DST_IP
#define CHIP_NAME
chip information definition
#define CH9121X_CMD2_GET_FLOW_CONTROL_ENABLE
#define CH9121X_CMD_PORT1_GET_PORT
#define CH9121X_CMD_PORT2_GET_CONFIG
#define CH9121X_CMD_GET_PORT1_2_LINKDOWN
#define DRIVER_VERSION
#define CH9121X_CMD_PORT1_GET_CONFIG
#define CH9121X_CMD_RUN_AND_RESET
#define CH9121X_CMD_SET_UART_CLOCK_MODE
#define CH9121X_CMD_SET_NETMASK
#define CH9121X_CMD_PORT1_LEN
#define CH9121X_CMD_PORT1_GET_MODE
#define CH9121X_CMD_PORT2_ENABLE
#define CH9121X_CMD_PORT2_GET_MODE
#define CH9121X_CMD_CLEAR_MAC_ADDR
driver ch9121x header file
ch9121x_port_t
ch9121x port enumeration definition
uint8_t ch9121x_set_dest_port(ch9121x_handle_t *handle, ch9121x_port_t port, uint16_t num)
set dest port
uint8_t ch9121x_set_uart_baud(ch9121x_handle_t *handle, ch9121x_port_t port, uint32_t baud)
set uart baud
uint8_t ch9121x_read(ch9121x_handle_t *handle, uint8_t *buf, uint16_t *len)
read data
uint8_t ch9121x_set_dest_ip(ch9121x_handle_t *handle, ch9121x_port_t port, uint8_t ip[4])
set dest ip
uint8_t ch9121x_get_mode(ch9121x_handle_t *handle, ch9121x_port_t port, ch9121x_mode_t *mode)
get mode
uint8_t ch9121x_get_dhcp(ch9121x_handle_t *handle, ch9121x_bool_t *enable)
get dhcp status
uint8_t ch9121x_get_eth_cfg(ch9121x_handle_t *handle, ch9121x_bool_t *enable)
get eth cfg
uint8_t ch9121x_get_dest_port(ch9121x_handle_t *handle, ch9121x_port_t port, uint16_t *num)
get dest port
struct ch9121x_info_s ch9121x_info_t
ch9121x information structure definition
uint8_t ch9121x_get_flow_control(ch9121x_handle_t *handle, ch9121x_bool_t *enable)
get flow control status
uint8_t ch9121x_get_uart_baud(ch9121x_handle_t *handle, ch9121x_port_t port, uint32_t *baud)
get uart baud
uint8_t ch9121x_set_uart_flush(ch9121x_handle_t *handle, ch9121x_port_t port, ch9121x_bool_t enable)
enable or disable uart auto flush
uint8_t ch9121x_get_version(ch9121x_handle_t *handle, uint8_t *version)
get version
uint8_t ch9121x_config_and_reset(ch9121x_handle_t *handle)
config and reset the chip
uint8_t ch9121x_get_source_port_random(ch9121x_handle_t *handle, ch9121x_port_t port, ch9121x_bool_t *enable)
get random source port number status
uint8_t ch9121x_clear_mac(ch9121x_handle_t *handle)
clear mac address
uint8_t ch9121x_set_uart_clock_mode(ch9121x_handle_t *handle, ch9121x_uart_clock_mode_t mode)
set uart clock mode
uint8_t ch9121x_get_uart_config(ch9121x_handle_t *handle, ch9121x_port_t port, uint8_t *data_bit, ch9121x_parity_t *parity, uint8_t *stop_bit)
get uart config
uint8_t ch9121x_set_uart_timeout(ch9121x_handle_t *handle, ch9121x_port_t port, uint8_t timeout)
set uart timeout
uint8_t ch9121x_get_dest_ip(ch9121x_handle_t *handle, ch9121x_port_t port, uint8_t ip[4])
get dest ip
uint8_t ch9121x_get_ip(ch9121x_handle_t *handle, uint8_t ip[4])
get ip address
uint8_t ch9121x_get_uart_buffer_length(ch9121x_handle_t *handle, ch9121x_port_t port, uint32_t *len)
get uart buffer length
ch9121x_phy_status_t
ch9121x phy status enumeration definition
uint8_t ch9121x_get_source_port(ch9121x_handle_t *handle, ch9121x_port_t port, uint16_t *num)
get source port
uint8_t ch9121x_set_mode(ch9121x_handle_t *handle, ch9121x_port_t port, ch9121x_mode_t mode)
set mode
ch9121x_mode_t
ch9121x mode enumeration definition
uint8_t ch9121x_set_subnet_mask(ch9121x_handle_t *handle, uint8_t mask[4])
set subnet mask
uint8_t ch9121x_uart_timeout_convert_to_register(ch9121x_handle_t *handle, uint16_t ms, uint8_t *reg)
convert the uart timeout to the register raw data
uint8_t ch9121x_write(ch9121x_handle_t *handle, uint8_t *buf, uint16_t len)
write data
uint8_t ch9121x_set_port2(ch9121x_handle_t *handle, ch9121x_bool_t enable)
enable or disable uart port2
uint8_t ch9121x_get_uart_flush(ch9121x_handle_t *handle, ch9121x_port_t port, ch9121x_bool_t *enable)
get uart auto flush status
uint8_t ch9121x_info(ch9121x_info_t *info)
get chip's information
uint8_t ch9121x_reset(ch9121x_handle_t *handle)
reset the chip
uint8_t ch9121x_arp_retry_period_convert_to_register(ch9121x_handle_t *handle, uint16_t ms, uint8_t *reg)
convert the arp retry period to the register raw data
uint8_t ch9121x_get_mac(ch9121x_handle_t *handle, uint8_t mac[6])
get chip mac
uint8_t ch9121x_set_source_port(ch9121x_handle_t *handle, ch9121x_port_t port, uint16_t num)
set source port
#define CH9121X_UART_PRE_DELAY
ch9121x uart pre delay definition
uint8_t ch9121x_set_tcp_retry_mode(ch9121x_handle_t *handle, uint8_t t)
set tcp retry mode
uint8_t ch9121x_exit(ch9121x_handle_t *handle)
exit
ch9121x_uart_clock_mode_t
ch9121x uart clock mode enumeration definition
uint8_t ch9121x_deinit(ch9121x_handle_t *handle)
close the chip
uint8_t ch9121x_set_dhcp(ch9121x_handle_t *handle, ch9121x_bool_t enable)
enable or disable dhcp
uint8_t ch9121x_arp_retry_period_convert_to_data(ch9121x_handle_t *handle, uint8_t reg, uint16_t *ms)
convert the register raw data to the arp retry period
uint8_t ch9121x_set_eth_cfg(ch9121x_handle_t *handle, ch9121x_bool_t enable)
set eth cfg
uint8_t ch9121x_get_phy_status(ch9121x_handle_t *handle, ch9121x_phy_status_t *status)
get phy status
uint8_t ch9121x_uart_timeout_convert_to_data(ch9121x_handle_t *handle, uint8_t reg, uint16_t *ms)
convert the register raw data to the offset
uint8_t ch9121x_set_disconnect_with_no_rj45(ch9121x_handle_t *handle, ch9121x_bool_t enable)
enable or disable disconnect with no rj45
uint8_t ch9121x_set_ip(ch9121x_handle_t *handle, uint8_t ip[4])
set ip address
ch9121x_bool_t
ch9121x bool enumeration definition
uint8_t ch9121x_tcp_retry_time_convert_to_register(ch9121x_handle_t *handle, uint16_t ms, uint8_t *reg)
convert the tcp retry time to the register raw data
uint8_t ch9121x_tcp_retry_time_convert_to_data(ch9121x_handle_t *handle, uint8_t reg, uint16_t *ms)
convert the register raw data to the tcp retry time
uint8_t ch9121x_set_gateway(ch9121x_handle_t *handle, uint8_t ip[4])
set gateway
ch9121x_status_t
ch9121x status enumeration definition
ch9121x_parity_t
ch9121x parity enumeration definition
uint8_t ch9121x_get_status(ch9121x_handle_t *handle, ch9121x_port_t port, ch9121x_status_t *status)
get status
uint8_t ch9121x_set_mac(ch9121x_handle_t *handle, uint8_t mac[6])
set mac address
uint8_t ch9121x_set_domain(ch9121x_handle_t *handle, char *domain)
set chip domain
uint8_t ch9121x_set_flow_control(ch9121x_handle_t *handle, ch9121x_bool_t enable)
enable or disable flow control
uint8_t ch9121x_get_uart_timeout(ch9121x_handle_t *handle, ch9121x_port_t port, uint8_t *timeout)
get uart timeout
uint8_t ch9121x_get_gateway(ch9121x_handle_t *handle, uint8_t ip[4])
get gateway
uint8_t ch9121x_get_subnet_mask(ch9121x_handle_t *handle, uint8_t mask[4])
get subnet mask
uint8_t ch9121x_get_disconnect_with_no_rj45(ch9121x_handle_t *handle, ch9121x_bool_t *enable)
get disconnect with no rj45 status
uint8_t ch9121x_save_to_eeprom(ch9121x_handle_t *handle)
save to eeprom
uint8_t ch9121x_init(ch9121x_handle_t *handle)
initialize the chip
uint8_t ch9121x_get_tcp_retry_mode(ch9121x_handle_t *handle, uint8_t *t)
get tcp retry mode
uint8_t ch9121x_set_arp_retry(ch9121x_handle_t *handle, uint8_t period, uint8_t times)
set arp retry
struct ch9121x_handle_s ch9121x_handle_t
ch9121x handle structure definition
uint8_t ch9121x_set_source_port_random(ch9121x_handle_t *handle, ch9121x_port_t port, ch9121x_bool_t enable)
enable or disable random source port number
uint8_t ch9121x_get_uart_clock_mode(ch9121x_handle_t *handle, ch9121x_uart_clock_mode_t *mode)
get uart clock mode
uint8_t ch9121x_set_uart_buffer_length(ch9121x_handle_t *handle, ch9121x_port_t port, uint32_t len)
set uart buffer length
uint8_t ch9121x_set_uart_config(ch9121x_handle_t *handle, ch9121x_port_t port, uint8_t data_bit, ch9121x_parity_t parity, uint8_t stop_bit)
set uart config
@ CH9121X_PORT1
@ CH9121X_PHY_STATUS_UNKNOWN
@ CH9121X_PHY_STATUS_100M_FULL_DUPLEX
@ CH9121X_PHY_STATUS_10M_HALF_DUPLEX
@ CH9121X_PHY_STATUS_DISCONNECTED
@ CH9121X_PHY_STATUS_10M_FULL_DUPLEX
@ CH9121X_PHY_STATUS_100M_HALF_DUPLEX
uint8_t ch9121x_set_command(ch9121x_handle_t *handle, uint8_t *param, uint16_t len, uint8_t *out, uint16_t out_len, uint16_t pre_delay, uint16_t timeout)
set command
uint8_t(* uart_flush)(void)
uint8_t(* cfg_gpio_write)(uint8_t data)
uint8_t(* uart_write)(uint8_t *buf, uint16_t len)
void(* delay_ms)(uint32_t ms)
uint8_t(* cfg_gpio_init)(void)
uint8_t(* uart_deinit)(void)
uint8_t(* reset_gpio_deinit)(void)
void(* debug_print)(const char *const fmt,...)
uint16_t(* uart_read)(uint8_t *buf, uint16_t len)
uint8_t(* reset_gpio_init)(void)
uint8_t(* uart_init)(void)
uint8_t(* reset_gpio_write)(uint8_t data)
uint8_t(* cfg_gpio_deinit)(void)
uint32_t driver_version
char manufacturer_name[32]