LibDriver CH9120
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driver_ch9120_net_test.c
Go to the documentation of this file.
1
36
38
39static ch9120_handle_t gs_handle;
40
50uint8_t ch9120_net_test(ch9120_mode_t mode, uint32_t timeout)
51{
52 uint8_t res;
53 uint8_t reg;
54 uint8_t ip[4] = CH9120_NET_TEST_IP;
55 uint8_t dst_ip[4] = CH9120_NET_TEST_DST_IP;
56 uint8_t mask[4] = CH9120_NET_TEST_MASK;
57 uint8_t gateway[4] = CH9120_NET_TEST_GATEWAY;
58 char str[] = "LibDriver";
59 ch9120_info_t info;
60
61 /* link interface function */
76
77 /* get ch9120 information */
78 res = ch9120_info(&info);
79 if (res != 0)
80 {
81 ch9120_interface_debug_print("ch9120: get info failed.\n");
82
83 return 1;
84 }
85 else
86 {
87 /* print chip information */
88 ch9120_interface_debug_print("ch9120: chip is %s.\n", info.chip_name);
89 ch9120_interface_debug_print("ch9120: manufacturer is %s.\n", info.manufacturer_name);
90 ch9120_interface_debug_print("ch9120: interface is %s.\n", info.interface);
91 ch9120_interface_debug_print("ch9120: driver version is %d.%d.\n", info.driver_version / 1000, (info.driver_version % 1000) / 100);
92 ch9120_interface_debug_print("ch9120: min supply voltage is %0.1fV.\n", info.supply_voltage_min_v);
93 ch9120_interface_debug_print("ch9120: max supply voltage is %0.1fV.\n", info.supply_voltage_max_v);
94 ch9120_interface_debug_print("ch9120: max current is %0.2fmA.\n", info.max_current_ma);
95 ch9120_interface_debug_print("ch9120: max temperature is %0.1fC.\n", info.temperature_max);
96 ch9120_interface_debug_print("ch9120: min temperature is %0.1fC.\n", info.temperature_min);
97 }
98
99 /* start net test */
100 ch9120_interface_debug_print("ch9120: start net test.\n");
101
102 /* ch9120 init */
103 res = ch9120_init(&gs_handle);
104 if (res != 0)
105 {
106 ch9120_interface_debug_print("ch9120: init failed.\n");
107
108 return 1;
109 }
110
111 /* disable dhcp */
112 res = ch9120_set_dhcp(&gs_handle, CH9120_BOOL_FALSE);
113 if (res != 0)
114 {
115 ch9120_interface_debug_print("ch9120: set dhcp failed.\n");
116 (void)ch9120_deinit(&gs_handle);
117
118 return 1;
119 }
120
121 /* set ip */
122 res = ch9120_set_ip(&gs_handle, ip);
123 if (res != 0)
124 {
125 ch9120_interface_debug_print("ch9120: set ip failed.\n");
126 (void)ch9120_deinit(&gs_handle);
127
128 return 1;
129 }
130
131 /* set subnet mask */
132 res = ch9120_set_subnet_mask(&gs_handle, mask);
133 if (res != 0)
134 {
135 ch9120_interface_debug_print("ch9120: set subnet mask failed.\n");
136 (void)ch9120_deinit(&gs_handle);
137
138 return 1;
139 }
140
141 /* set gateway */
142 res = ch9120_set_gateway(&gs_handle, gateway);
143 if (res != 0)
144 {
145 ch9120_interface_debug_print("ch9120: set gateway failed.\n");
146 (void)ch9120_deinit(&gs_handle);
147
148 return 1;
149 }
150
151 /* set source port */
153 if (res != 0)
154 {
155 ch9120_interface_debug_print("ch9120: set source port failed.\n");
156 (void)ch9120_deinit(&gs_handle);
157
158 return 1;
159 }
160
161 /* set dest ip */
162 res = ch9120_set_dest_ip(&gs_handle, dst_ip);
163 if (res != 0)
164 {
165 ch9120_interface_debug_print("ch9120: set dest ip failed.\n");
166 (void)ch9120_deinit(&gs_handle);
167
168 return 1;
169 }
170
171 /* set dest port */
173 if (res != 0)
174 {
175 ch9120_interface_debug_print("ch9120: set dest port failed.\n");
176 (void)ch9120_deinit(&gs_handle);
177
178 return 1;
179 }
180
181 /* set 9600 */
182 res = ch9120_set_uart_baud(&gs_handle, 9600);
183 if (res != 0)
184 {
185 ch9120_interface_debug_print("ch9120: set uart baud failed.\n");
186 (void)ch9120_deinit(&gs_handle);
187
188 return 1;
189 }
190
191 /* set uart 8 data bit, parity none, 1 stop bit */
192 res = ch9120_set_uart_config(&gs_handle, 8, CH9120_PARITY_NONE, 1);
193 if (res != 0)
194 {
195 ch9120_interface_debug_print("ch9120: set uart config failed.\n");
196 (void)ch9120_deinit(&gs_handle);
197
198 return 1;
199 }
200
201 /* 10ms */
202 res = ch9120_uart_timeout_convert_to_register(&gs_handle, 10, &reg);
203 if (res != 0)
204 {
205 ch9120_interface_debug_print("ch9120: uart timeout convert to register failed.\n");
206 (void)ch9120_deinit(&gs_handle);
207
208 return 1;
209 }
210
211 /* set uart timeout */
212 res = ch9120_set_uart_timeout(&gs_handle, reg);
213 if (res != 0)
214 {
215 ch9120_interface_debug_print("ch9120: set uart timeout failed.\n");
216 (void)ch9120_deinit(&gs_handle);
217
218 return 1;
219 }
220
221 /* disable source port random */
223 if (res != 0)
224 {
225 ch9120_interface_debug_print("ch9120: set source port random failed.\n");
226 (void)ch9120_deinit(&gs_handle);
227
228 return 1;
229 }
230
231 /* set uart buffer length */
232 res = ch9120_set_uart_buffer_length(&gs_handle, 1024);
233 if (res != 0)
234 {
235 ch9120_interface_debug_print("ch9120: set uart buffer length failed.\n");
236 (void)ch9120_deinit(&gs_handle);
237
238 return 1;
239 }
240
241 /* false uart flush */
242 res = ch9120_set_uart_flush(&gs_handle, CH9120_BOOL_FALSE);
243 if (res != 0)
244 {
245 ch9120_interface_debug_print("ch9120: set uart flush failed.\n");
246 (void)ch9120_deinit(&gs_handle);
247
248 return 1;
249 }
250
251 /* enable disconnect with no rj45 */
253 if (res != 0)
254 {
255 ch9120_interface_debug_print("ch9120: set disconnect with no rj45 failed.\n");
256 (void)ch9120_deinit(&gs_handle);
257
258 return 1;
259 }
260
261 /* set mode */
262 res = ch9120_set_mode(&gs_handle, mode);
263 if (res != 0)
264 {
265 ch9120_interface_debug_print("ch9120: set mode failed.\n");
266 (void)ch9120_deinit(&gs_handle);
267
268 return 1;
269 }
270
271 /* save to eeprom */
272 res = ch9120_save_to_eeprom(&gs_handle);
273 if (res != 0)
274 {
275 ch9120_interface_debug_print("ch9120: save to eeprom failed.\n");
276 (void)ch9120_deinit(&gs_handle);
277
278 return 1;
279 }
280
281 /* config and reset */
282 res = ch9120_config_and_reset(&gs_handle);
283 if (res != 0)
284 {
285 ch9120_interface_debug_print("ch9120: config and reset failed.\n");
286 (void)ch9120_deinit(&gs_handle);
287
288 return 1;
289 }
290
291 /* tcp server */
292 if (mode == CH9120_MODE_TCP_SERVER)
293 {
294 uint8_t ip_tmp[4];
295 uint16_t num;
296 uint32_t t = timeout;
297
298 /* get ip */
299 res = ch9120_get_ip(&gs_handle, ip_tmp);
300 if (res != 0)
301 {
302 ch9120_interface_debug_print("ch9120: get ip failed.\n");
303 (void)ch9120_deinit(&gs_handle);
304
305 return 1;
306 }
307
308 /* get source port */
309 res = ch9120_get_source_port(&gs_handle, &num);
310 if (res != 0)
311 {
312 ch9120_interface_debug_print("ch9120: get source port failed.\n");
313 (void)ch9120_deinit(&gs_handle);
314
315 return 1;
316 }
317
318 /* output */
319 ch9120_interface_debug_print("ch9120: tcp server src port %d, src ip %d.%d.%d.%d.\n", num, ip_tmp[0], ip_tmp[1], ip_tmp[2], ip_tmp[3]);
320
321 /* loop */
322 while (t != 0)
323 {
324 uint8_t buf[16];
325 uint16_t l;
326
327 /* init */
328 memset(buf, 0, sizeof(uint8_t) * 16);
329 l = 16;
330
331 /* read data */
332 res = ch9120_read(&gs_handle, buf, &l);
333 if (res != 0)
334 {
335 ch9120_interface_debug_print("ch9120: read failed.\n");
336 (void)ch9120_deinit(&gs_handle);
337
338 return 1;
339 }
340
341 if (l != 0)
342 {
343 /* output */
344 ch9120_interface_debug_print("ch9120: read %s.\n", buf);
345
346 break;
347 }
348
349 /* delay 1ms */
351 t--;
352 }
353
354 /* check timeout */
355 if (t == 0)
356 {
357 ch9120_interface_debug_print("ch9120: timeout.\n");
358 (void)ch9120_deinit(&gs_handle);
359
360 return 1;
361 }
362 }
363 /* tcp client */
364 else if (mode == CH9120_MODE_TCP_CLIENT)
365 {
366 uint8_t ip_tmp[4];
367 uint16_t num;
368
369 /* get ip */
370 res = ch9120_get_dest_ip(&gs_handle, ip_tmp);
371 if (res != 0)
372 {
373 ch9120_interface_debug_print("ch9120: get ip failed.\n");
374 (void)ch9120_deinit(&gs_handle);
375
376 return 1;
377 }
378
379 /* get dest port */
380 res = ch9120_get_dest_port(&gs_handle, &num);
381 if (res != 0)
382 {
383 ch9120_interface_debug_print("ch9120: get dest port failed.\n");
384 (void)ch9120_deinit(&gs_handle);
385
386 return 1;
387 }
388
389 /* output */
390 ch9120_interface_debug_print("ch9120: tcp client dest port %d, dest ip %d.%d.%d.%d.\n", num, ip_tmp[0], ip_tmp[1], ip_tmp[2], ip_tmp[3]);
391
392 /* write data */
393 res = ch9120_write(&gs_handle, (uint8_t *)str, (uint16_t)strlen(str));
394 if (res != 0)
395 {
396 ch9120_interface_debug_print("ch9120: write failed.\n");
397 (void)ch9120_deinit(&gs_handle);
398
399 return 1;
400 }
401
402 /* output */
403 ch9120_interface_debug_print("ch9120: write %s.\n", str);
404 }
405 /* udp server */
406 else if (mode == CH9120_MODE_UDP_SERVER)
407 {
408 uint8_t ip_tmp[4];
409 uint16_t num;
410 uint32_t t = timeout;
411
412 /* get ip */
413 res = ch9120_get_ip(&gs_handle, ip_tmp);
414 if (res != 0)
415 {
416 ch9120_interface_debug_print("ch9120: get ip failed.\n");
417 (void)ch9120_deinit(&gs_handle);
418
419 return 1;
420 }
421
422 /* get source port */
423 res = ch9120_get_source_port(&gs_handle, &num);
424 if (res != 0)
425 {
426 ch9120_interface_debug_print("ch9120: get source port failed.\n");
427 (void)ch9120_deinit(&gs_handle);
428
429 return 1;
430 }
431
432 /* output */
433 ch9120_interface_debug_print("ch9120: udp server src port %d, src ip %d.%d.%d.%d.\n", num, ip_tmp[0], ip_tmp[1], ip_tmp[2], ip_tmp[3]);
434
435 /* loop */
436 while (t != 0)
437 {
438 uint8_t buf[16];
439 uint16_t l;
440
441 /* init */
442 memset(buf, 0, sizeof(uint8_t) * 16);
443 l = 16;
444
445 /* read data */
446 res = ch9120_read(&gs_handle, buf, &l);
447 if (res != 0)
448 {
449 ch9120_interface_debug_print("ch9120: read failed.\n");
450 (void)ch9120_deinit(&gs_handle);
451
452 return 1;
453 }
454
455 if (l != 0)
456 {
457 /* output */
458 ch9120_interface_debug_print("ch9120: read %s.\n", buf);
459
460 break;
461 }
462
463 /* delay 1ms */
465 t--;
466 }
467
468 /* check timeout */
469 if (t == 0)
470 {
471 ch9120_interface_debug_print("ch9120: timeout.\n");
472 (void)ch9120_deinit(&gs_handle);
473
474 return 1;
475 }
476 }
477 /* udp client */
478 else
479 {
480 uint8_t ip_tmp[4];
481 uint16_t i;
482 uint16_t num;
483
484 /* get ip */
485 res = ch9120_get_dest_ip(&gs_handle, ip_tmp);
486 if (res != 0)
487 {
488 ch9120_interface_debug_print("ch9120: get ip failed.\n");
489 (void)ch9120_deinit(&gs_handle);
490
491 return 1;
492 }
493
494 /* get dest port */
495 res = ch9120_get_dest_port(&gs_handle, &num);
496 if (res != 0)
497 {
498 ch9120_interface_debug_print("ch9120: get dest port failed.\n");
499 (void)ch9120_deinit(&gs_handle);
500
501 return 1;
502 }
503
504 /* output */
505 ch9120_interface_debug_print("ch9120: udp client dest port %d, dest ip %d.%d.%d.%d.\n", num, ip_tmp[0], ip_tmp[1], ip_tmp[2], ip_tmp[3]);
506
507 /* run 10 times */
508 for (i = 0; i < 10; i++)
509 {
510 /* write data */
511 res = ch9120_write(&gs_handle, (uint8_t *)str, (uint16_t)strlen(str));
512 if (res != 0)
513 {
514 ch9120_interface_debug_print("ch9120: write failed.\n");
515 (void)ch9120_deinit(&gs_handle);
516
517 return 1;
518 }
519
520 /* output */
521 ch9120_interface_debug_print("ch9120: write %s.\n", str);
522
523 /* delay 1000ms */
525 }
526 }
527
528 /* finish net test */
529 ch9120_interface_debug_print("ch9120: finish net test.\n");
530
531 return 0;
532}
driver ch9120 net test header file
uint8_t ch9120_set_uart_baud(ch9120_handle_t *handle, uint32_t baud)
set uart baud
uint8_t ch9120_set_dest_ip(ch9120_handle_t *handle, uint8_t ip[4])
set dest ip
uint8_t ch9120_get_dest_port(ch9120_handle_t *handle, uint16_t *num)
get dest port
struct ch9120_info_s ch9120_info_t
ch9120 information structure definition
uint8_t ch9120_init(ch9120_handle_t *handle)
initialize the chip
uint8_t ch9120_get_ip(ch9120_handle_t *handle, uint8_t ip[4])
get ip address
ch9120_mode_t
ch9120 mode enumeration definition
struct ch9120_handle_s ch9120_handle_t
ch9120 handle structure definition
uint8_t ch9120_get_source_port(ch9120_handle_t *handle, uint16_t *num)
get source port
uint8_t ch9120_read(ch9120_handle_t *handle, uint8_t *buf, uint16_t *len)
read data
uint8_t ch9120_set_dest_port(ch9120_handle_t *handle, uint16_t num)
set dest port
uint8_t ch9120_set_source_port_random(ch9120_handle_t *handle, ch9120_bool_t enable)
enable or disable random source port number
uint8_t ch9120_set_uart_config(ch9120_handle_t *handle, uint8_t data_bit, ch9120_parity_t parity, uint8_t stop_bit)
set uart config
uint8_t ch9120_set_uart_buffer_length(ch9120_handle_t *handle, uint32_t len)
set uart buffer length
uint8_t ch9120_set_uart_flush(ch9120_handle_t *handle, ch9120_bool_t enable)
enable or disable uart auto flush
uint8_t ch9120_get_dest_ip(ch9120_handle_t *handle, uint8_t ip[4])
get dest ip
uint8_t ch9120_deinit(ch9120_handle_t *handle)
close the chip
uint8_t ch9120_set_gateway(ch9120_handle_t *handle, uint8_t ip[4])
set gateway
uint8_t ch9120_config_and_reset(ch9120_handle_t *handle)
config and reset the chip
uint8_t ch9120_set_uart_timeout(ch9120_handle_t *handle, uint8_t timeout)
set uart timeout
uint8_t ch9120_set_disconnect_with_no_rj45(ch9120_handle_t *handle, ch9120_bool_t enable)
enable or disable disconnect with no rj45
uint8_t ch9120_info(ch9120_info_t *info)
get chip's information
uint8_t ch9120_set_mode(ch9120_handle_t *handle, ch9120_mode_t mode)
set mode
uint8_t ch9120_uart_timeout_convert_to_register(ch9120_handle_t *handle, uint16_t ms, uint8_t *reg)
convert the uart timeout to the register raw data
uint8_t ch9120_set_dhcp(ch9120_handle_t *handle, ch9120_bool_t enable)
enable or disable dhcp
uint8_t ch9120_save_to_eeprom(ch9120_handle_t *handle)
save to eeprom
uint8_t ch9120_set_subnet_mask(ch9120_handle_t *handle, uint8_t mask[4])
set subnet mask
uint8_t ch9120_set_ip(ch9120_handle_t *handle, uint8_t ip[4])
set ip address
uint8_t ch9120_write(ch9120_handle_t *handle, uint8_t *buf, uint16_t len)
write data
uint8_t ch9120_set_source_port(ch9120_handle_t *handle, uint16_t num)
set source port
@ CH9120_MODE_TCP_SERVER
@ CH9120_MODE_UDP_SERVER
@ CH9120_MODE_TCP_CLIENT
@ CH9120_PARITY_NONE
@ CH9120_BOOL_FALSE
@ CH9120_BOOL_TRUE
uint8_t ch9120_interface_uart_write(uint8_t *buf, uint16_t len)
interface uart write
uint8_t ch9120_interface_cfg_gpio_init(void)
interface cfg gpio init
uint16_t ch9120_interface_uart_read(uint8_t *buf, uint16_t len)
interface uart read
uint8_t ch9120_interface_reset_gpio_init(void)
interface reset gpio init
uint8_t ch9120_interface_cfg_gpio_write(uint8_t data)
interface cfg gpio write
uint8_t ch9120_interface_reset_gpio_deinit(void)
interface reset gpio deinit
uint8_t ch9120_interface_uart_init(void)
interface uart init
uint8_t ch9120_interface_uart_flush(void)
interface uart flush
uint8_t ch9120_interface_uart_deinit(void)
interface uart deinit
uint8_t ch9120_interface_cfg_gpio_deinit(void)
interface cfg gpio deinit
void ch9120_interface_debug_print(const char *const fmt,...)
interface print format data
uint8_t ch9120_interface_reset_gpio_write(uint8_t data)
interface reset gpio write
void ch9120_interface_delay_ms(uint32_t ms)
interface delay ms
#define CH9120_NET_TEST_IP
ch9120 net test ip definition
uint8_t ch9120_net_test(ch9120_mode_t mode, uint32_t timeout)
net test
#define CH9120_NET_TEST_DST_PORT
ch9120 net test dest port definition
#define CH9120_NET_TEST_MASK
ch9120 net test subnet mask definition
#define CH9120_NET_TEST_DST_IP
ch9120 net test dest ip definition
#define CH9120_NET_TEST_PORT
ch9120 net test port definition
#define CH9120_NET_TEST_GATEWAY
ch9120 net test gateway definition
float supply_voltage_max_v
uint32_t driver_version
char manufacturer_name[32]
float supply_voltage_min_v
char chip_name[32]