54 uint8_t timeout_check;
58 uint8_t mask_check[4];
256 ip[0] = rand() % 0xFF;
257 ip[1] = rand() % 0xFF;
258 ip[2] = rand() % 0xFF;
259 ip[3] = rand() % 0xFF;
273 ip[0], ip[1], ip[2], ip[3]);
292 mask[0] = rand() % 0xFF;
293 mask[1] = rand() % 0xFF;
294 mask[2] = rand() % 0xFF;
295 mask[3] = rand() % 0xFF;
309 mask[0], mask[1], mask[2], mask[3]);
328 ip[0] = rand() % 0xFF;
329 ip[1] = rand() % 0xFF;
330 ip[2] = rand() % 0xFF;
331 ip[3] = rand() % 0xFF;
345 ip[0], ip[1], ip[2], ip[3]);
483 num = rand() % 0xFFFFU;
515 ip[0] = rand() % 0xFF;
516 ip[1] = rand() % 0xFF;
517 ip[2] = rand() % 0xFF;
518 ip[3] = rand() % 0xFF;
550 num = rand() % 0xFFFFU;
645 timeout = rand() % 0xFF;
712 len = 128 + rand() % 50;
781 ms = (rand() % 10) * 5;
driver ch9120 register test header file
uint8_t ch9120_set_uart_baud(ch9120_handle_t *handle, uint32_t baud)
set uart baud
uint8_t ch9120_set_dest_ip(ch9120_handle_t *handle, uint8_t ip[4])
set dest ip
uint8_t ch9120_get_status(ch9120_handle_t *handle, ch9120_status_t *status)
get status
uint8_t ch9120_get_disconnect_with_no_rj45(ch9120_handle_t *handle, ch9120_bool_t *enable)
get disconnect with no rj45 status
uint8_t ch9120_get_gateway(ch9120_handle_t *handle, uint8_t ip[4])
get gateway
uint8_t ch9120_get_uart_baud(ch9120_handle_t *handle, uint32_t *baud)
get uart baud
uint8_t ch9120_get_dest_port(ch9120_handle_t *handle, uint16_t *num)
get dest port
struct ch9120_info_s ch9120_info_t
ch9120 information structure definition
uint8_t ch9120_get_uart_buffer_length(ch9120_handle_t *handle, uint32_t *len)
get uart buffer length
uint8_t ch9120_uart_timeout_convert_to_data(ch9120_handle_t *handle, uint8_t reg, uint16_t *ms)
convert the register raw data to the offset
uint8_t ch9120_init(ch9120_handle_t *handle)
initialize the chip
uint8_t ch9120_get_ip(ch9120_handle_t *handle, uint8_t ip[4])
get ip address
ch9120_mode_t
ch9120 mode enumeration definition
struct ch9120_handle_s ch9120_handle_t
ch9120 handle structure definition
uint8_t ch9120_get_source_port(ch9120_handle_t *handle, uint16_t *num)
get source port
ch9120_parity_t
ch9120 parity enumeration definition
uint8_t ch9120_get_uart_timeout(ch9120_handle_t *handle, uint8_t *timeout)
get uart timeout
uint8_t ch9120_set_dest_port(ch9120_handle_t *handle, uint16_t num)
set dest port
uint8_t ch9120_set_source_port_random(ch9120_handle_t *handle, ch9120_bool_t enable)
enable or disable random source port number
uint8_t ch9120_set_uart_config(ch9120_handle_t *handle, uint8_t data_bit, ch9120_parity_t parity, uint8_t stop_bit)
set uart config
uint8_t ch9120_set_uart_buffer_length(ch9120_handle_t *handle, uint32_t len)
set uart buffer length
uint8_t ch9120_set_uart_flush(ch9120_handle_t *handle, ch9120_bool_t enable)
enable or disable uart auto flush
uint8_t ch9120_get_dest_ip(ch9120_handle_t *handle, uint8_t ip[4])
get dest ip
uint8_t ch9120_deinit(ch9120_handle_t *handle)
close the chip
uint8_t ch9120_get_uart_flush(ch9120_handle_t *handle, ch9120_bool_t *enable)
get uart auto flush status
uint8_t ch9120_set_gateway(ch9120_handle_t *handle, uint8_t ip[4])
set gateway
uint8_t ch9120_set_uart_timeout(ch9120_handle_t *handle, uint8_t timeout)
set uart timeout
uint8_t ch9120_get_uart_config(ch9120_handle_t *handle, uint8_t *data_bit, ch9120_parity_t *parity, uint8_t *stop_bit)
get uart config
uint8_t ch9120_exit(ch9120_handle_t *handle)
exit
uint8_t ch9120_get_mode(ch9120_handle_t *handle, ch9120_mode_t *mode)
get mode
uint8_t ch9120_set_disconnect_with_no_rj45(ch9120_handle_t *handle, ch9120_bool_t enable)
enable or disable disconnect with no rj45
uint8_t ch9120_info(ch9120_info_t *info)
get chip's information
uint8_t ch9120_set_mode(ch9120_handle_t *handle, ch9120_mode_t mode)
set mode
uint8_t ch9120_get_subnet_mask(ch9120_handle_t *handle, uint8_t mask[4])
get subnet mask
uint8_t ch9120_uart_timeout_convert_to_register(ch9120_handle_t *handle, uint16_t ms, uint8_t *reg)
convert the uart timeout to the register raw data
uint8_t ch9120_set_dhcp(ch9120_handle_t *handle, ch9120_bool_t enable)
enable or disable dhcp
ch9120_bool_t
ch9120 bool enumeration definition
uint8_t ch9120_save_to_eeprom(ch9120_handle_t *handle)
save to eeprom
uint8_t ch9120_set_subnet_mask(ch9120_handle_t *handle, uint8_t mask[4])
set subnet mask
ch9120_status_t
ch9120 status enumeration definition
uint8_t ch9120_set_ip(ch9120_handle_t *handle, uint8_t ip[4])
set ip address
uint8_t ch9120_get_version(ch9120_handle_t *handle, uint8_t *version)
get version
uint8_t ch9120_set_source_port(ch9120_handle_t *handle, uint16_t num)
set source port
uint8_t ch9120_interface_uart_write(uint8_t *buf, uint16_t len)
interface uart write
uint8_t ch9120_interface_cfg_gpio_init(void)
interface cfg gpio init
uint16_t ch9120_interface_uart_read(uint8_t *buf, uint16_t len)
interface uart read
uint8_t ch9120_interface_reset_gpio_init(void)
interface reset gpio init
uint8_t ch9120_interface_cfg_gpio_write(uint8_t data)
interface cfg gpio write
uint8_t ch9120_interface_reset_gpio_deinit(void)
interface reset gpio deinit
uint8_t ch9120_interface_uart_init(void)
interface uart init
uint8_t ch9120_interface_uart_flush(void)
interface uart flush
uint8_t ch9120_interface_uart_deinit(void)
interface uart deinit
uint8_t ch9120_interface_cfg_gpio_deinit(void)
interface cfg gpio deinit
void ch9120_interface_debug_print(const char *const fmt,...)
interface print format data
uint8_t ch9120_interface_reset_gpio_write(uint8_t data)
interface reset gpio write
void ch9120_interface_delay_ms(uint32_t ms)
interface delay ms
#define DRIVER_CH9120_LINK_RESET_GPIO_INIT(HANDLE, FUC)
link reset_gpio_init function
#define DRIVER_CH9120_LINK_UART_WRITE(HANDLE, FUC)
link uart_write function
#define DRIVER_CH9120_LINK_CFG_GPIO_DEINIT(HANDLE, FUC)
link cfg_gpio_deinit function
#define DRIVER_CH9120_LINK_CFG_GPIO_WRITE(HANDLE, FUC)
link cfg_gpio_write function
#define DRIVER_CH9120_LINK_RESET_GPIO_DEINIT(HANDLE, FUC)
link reset_gpio_deinit function
#define DRIVER_CH9120_LINK_UART_INIT(HANDLE, FUC)
link uart_init function
#define DRIVER_CH9120_LINK_INIT(HANDLE, STRUCTURE)
initialize ch9120 structure
#define DRIVER_CH9120_LINK_DELAY_MS(HANDLE, FUC)
link delay_ms function
#define DRIVER_CH9120_LINK_UART_READ(HANDLE, FUC)
link uart_read function
#define DRIVER_CH9120_LINK_UART_DEINIT(HANDLE, FUC)
link uart_deinit function
#define DRIVER_CH9120_LINK_RESET_GPIO_WRITE(HANDLE, FUC)
link reset_gpio_write function
#define DRIVER_CH9120_LINK_DEBUG_PRINT(HANDLE, FUC)
link debug_print function
#define DRIVER_CH9120_LINK_UART_FLUSH(HANDLE, FUC)
link uart_flush function
#define DRIVER_CH9120_LINK_CFG_GPIO_INIT(HANDLE, FUC)
link cfg_gpio_init function
uint8_t ch9120_register_test(void)
register test
float supply_voltage_max_v
char manufacturer_name[32]
float supply_voltage_min_v