LibDriver CH9120
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driver_ch9120_register_test.c
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1
36
38#include <stdlib.h>
39
40static ch9120_handle_t gs_handle;
41
50{
51 uint8_t res;
52 uint8_t version;
53 uint8_t timeout;
54 uint8_t timeout_check;
55 uint8_t ip[4];
56 uint8_t ip_check[4];
57 uint8_t mask[4];
58 uint8_t mask_check[4];
59 uint16_t num;
60 uint16_t num_check;
61 uint32_t baud;
62 uint32_t baud_check;
63 uint32_t len;
64 uint32_t len_check;
65 uint8_t data_bit;
66 uint8_t stop_bit;
67 uint16_t ms;
68 uint16_t ms_check;
69 uint8_t reg;
70 ch9120_bool_t enable;
71 ch9120_parity_t parity;
72 ch9120_info_t info;
73 ch9120_status_t status;
74 ch9120_mode_t mode;
75
76 /* link interface function */
91
92 /* get ch9120 information */
93 res = ch9120_info(&info);
94 if (res != 0)
95 {
96 ch9120_interface_debug_print("ch9120: get info failed.\n");
97
98 return 1;
99 }
100 else
101 {
102 /* print chip information */
103 ch9120_interface_debug_print("ch9120: chip is %s.\n", info.chip_name);
104 ch9120_interface_debug_print("ch9120: manufacturer is %s.\n", info.manufacturer_name);
105 ch9120_interface_debug_print("ch9120: interface is %s.\n", info.interface);
106 ch9120_interface_debug_print("ch9120: driver version is %d.%d.\n", info.driver_version / 1000, (info.driver_version % 1000) / 100);
107 ch9120_interface_debug_print("ch9120: min supply voltage is %0.1fV.\n", info.supply_voltage_min_v);
108 ch9120_interface_debug_print("ch9120: max supply voltage is %0.1fV.\n", info.supply_voltage_max_v);
109 ch9120_interface_debug_print("ch9120: max current is %0.2fmA.\n", info.max_current_ma);
110 ch9120_interface_debug_print("ch9120: max temperature is %0.1fC.\n", info.temperature_max);
111 ch9120_interface_debug_print("ch9120: min temperature is %0.1fC.\n", info.temperature_min);
112 }
113
114 /* start register test */
115 ch9120_interface_debug_print("ch9120: start register test.\n");
116
117 /* ch9120 init */
118 res = ch9120_init(&gs_handle);
119 if (res != 0)
120 {
121 ch9120_interface_debug_print("ch9120: init failed.\n");
122
123 return 1;
124 }
125
126 /* ch9120_get_version test */
127 ch9120_interface_debug_print("ch9120: ch9120_get_version test.\n");
128
129 /* get version */
130 res = ch9120_get_version(&gs_handle, &version);
131 if (res != 0)
132 {
133 ch9120_interface_debug_print("ch9120: get version failed.\n");
134 (void)ch9120_deinit(&gs_handle);
135
136 return 1;
137 }
138
139 /* output */
140 ch9120_interface_debug_print("ch9120: version is 0x%02X.\n", version);
141
142 /* ch9120_save_to_eeprom test */
143 ch9120_interface_debug_print("ch9120: ch9120_save_to_eeprom test.\n");
144
145 /* save to eeprom */
146 res = ch9120_save_to_eeprom(&gs_handle);
147 if (res != 0)
148 {
149 ch9120_interface_debug_print("ch9120: save to eeprom failed.\n");
150 (void)ch9120_deinit(&gs_handle);
151
152 return 1;
153 }
154
155 /* output */
156 ch9120_interface_debug_print("ch9120: check save to eeprom %s.\n", res == 0 ? "ok" : "error");
157
158 /* ch9120_exit test */
159 ch9120_interface_debug_print("ch9120: ch9120_exit test.\n");
160
161 /* exit */
162 res = ch9120_exit(&gs_handle);
163 if (res != 0)
164 {
165 ch9120_interface_debug_print("ch9120: exit failed.\n");
166 (void)ch9120_deinit(&gs_handle);
167
168 return 1;
169 }
170
171 /* output */
172 ch9120_interface_debug_print("ch9120: check exit %s.\n", res == 0 ? "ok" : "error");
173
174 /* ch9120_set_disconnect_with_no_rj45/ch9120_get_disconnect_with_no_rj45 test */
175 ch9120_interface_debug_print("ch9120: ch9120_set_disconnect_with_no_rj45/ch9120_get_disconnect_with_no_rj45 test.\n");
176
177 /* disable */
179 if (res != 0)
180 {
181 ch9120_interface_debug_print("ch9120: set disconnect with no rj45 failed.\n");
182 (void)ch9120_deinit(&gs_handle);
183
184 return 1;
185 }
186 ch9120_interface_debug_print("ch9120: disable disconnect with no rj45.\n");
187 res = ch9120_get_disconnect_with_no_rj45(&gs_handle, &enable);
188 if (res != 0)
189 {
190 ch9120_interface_debug_print("ch9120: get disconnect with no rj45 failed.\n");
191 (void)ch9120_deinit(&gs_handle);
192
193 return 1;
194 }
195 ch9120_interface_debug_print("ch9120: check disconnect with no rj45 %s.\n", enable == CH9120_BOOL_FALSE ? "ok" : "error");
196
197 /* enable */
199 if (res != 0)
200 {
201 ch9120_interface_debug_print("ch9120: set disconnect with no rj45 failed.\n");
202 (void)ch9120_deinit(&gs_handle);
203
204 return 1;
205 }
206 ch9120_interface_debug_print("ch9120: enable disconnect with no rj45.\n");
207 res = ch9120_get_disconnect_with_no_rj45(&gs_handle, &enable);
208 if (res != 0)
209 {
210 ch9120_interface_debug_print("ch9120: get disconnect with no rj45 failed.\n");
211 (void)ch9120_deinit(&gs_handle);
212
213 return 1;
214 }
215 ch9120_interface_debug_print("ch9120: check disconnect with no rj45 %s.\n", enable == CH9120_BOOL_TRUE ? "ok" : "error");
216
217 /* ch9120_set_dhcp test */
218 ch9120_interface_debug_print("ch9120: ch9120_set_dhcp test.\n");
219
220 /* disable dhcp */
221 res = ch9120_set_dhcp(&gs_handle, CH9120_BOOL_FALSE);
222 if (res != 0)
223 {
224 ch9120_interface_debug_print("ch9120: set dhcp failed.\n");
225 (void)ch9120_deinit(&gs_handle);
226
227 return 1;
228 }
229
230 /* disable dhcp */
231 ch9120_interface_debug_print("ch9120: disable dhcp.\n");
232
233 /* output */
234 ch9120_interface_debug_print("ch9120: check dhcp %s.\n", res == 0 ? "ok" : "error");
235
236 /* enable dhcp */
237 res = ch9120_set_dhcp(&gs_handle, CH9120_BOOL_TRUE);
238 if (res != 0)
239 {
240 ch9120_interface_debug_print("ch9120: set dhcp failed.\n");
241 (void)ch9120_deinit(&gs_handle);
242
243 return 1;
244 }
245
246 /* enable dhcp */
247 ch9120_interface_debug_print("ch9120: enable dhcp.\n");
248
249 /* output */
250 ch9120_interface_debug_print("ch9120: check dhcp %s.\n", res == 0 ? "ok" : "error");
251
252 /* ch9120_set_ip/ch9120_get_ip test */
253 ch9120_interface_debug_print("ch9120: ch9120_set_ip/ch9120_get_ip test.\n");
254
255 /* random ip */
256 ip[0] = rand() % 0xFF;
257 ip[1] = rand() % 0xFF;
258 ip[2] = rand() % 0xFF;
259 ip[3] = rand() % 0xFF;
260
261 /* set ip */
262 res = ch9120_set_ip(&gs_handle, ip);
263 if (res != 0)
264 {
265 ch9120_interface_debug_print("ch9120: set ip failed.\n");
266 (void)ch9120_deinit(&gs_handle);
267
268 return 1;
269 }
270
271 /* output */
272 ch9120_interface_debug_print("ch9120: set ip %d.%d.%d.%d.\n",
273 ip[0], ip[1], ip[2], ip[3]);
274
275 /* get ip */
276 res = ch9120_get_ip(&gs_handle, ip_check);
277 if (res != 0)
278 {
279 ch9120_interface_debug_print("ch9120: get ip failed.\n");
280 (void)ch9120_deinit(&gs_handle);
281
282 return 1;
283 }
284
285 /* output */
286 ch9120_interface_debug_print("ch9120: check ip %s.\n", memcmp(ip, ip_check, 4) == 0 ? "ok" : "error");
287
288 /* ch9120_set_subnet_mask/ch9120_get_subnet_mask test */
289 ch9120_interface_debug_print("ch9120: ch9120_set_subnet_mask/ch9120_get_subnet_mask test.\n");
290
291 /* random mask */
292 mask[0] = rand() % 0xFF;
293 mask[1] = rand() % 0xFF;
294 mask[2] = rand() % 0xFF;
295 mask[3] = rand() % 0xFF;
296
297 /* set subnet mask */
298 res = ch9120_set_subnet_mask(&gs_handle, mask);
299 if (res != 0)
300 {
301 ch9120_interface_debug_print("ch9120: set subnet mask failed.\n");
302 (void)ch9120_deinit(&gs_handle);
303
304 return 1;
305 }
306
307 /* output */
308 ch9120_interface_debug_print("ch9120: set subnet mask %d.%d.%d.%d.\n",
309 mask[0], mask[1], mask[2], mask[3]);
310
311 /* get subnet mask */
312 res = ch9120_get_subnet_mask(&gs_handle, mask_check);
313 if (res != 0)
314 {
315 ch9120_interface_debug_print("ch9120: get subnet mask failed.\n");
316 (void)ch9120_deinit(&gs_handle);
317
318 return 1;
319 }
320
321 /* output */
322 ch9120_interface_debug_print("ch9120: check subnet mask %s.\n", memcmp(mask, mask_check, 4) == 0 ? "ok" : "error");
323
324 /* ch9120_set_gateway/ch9120_get_gateway test */
325 ch9120_interface_debug_print("ch9120: ch9120_set_gateway/ch9120_get_gateway test.\n");
326
327 /* random ip */
328 ip[0] = rand() % 0xFF;
329 ip[1] = rand() % 0xFF;
330 ip[2] = rand() % 0xFF;
331 ip[3] = rand() % 0xFF;
332
333 /* set gateway */
334 res = ch9120_set_gateway(&gs_handle, ip);
335 if (res != 0)
336 {
337 ch9120_interface_debug_print("ch9120: set gateway failed.\n");
338 (void)ch9120_deinit(&gs_handle);
339
340 return 1;
341 }
342
343 /* output */
344 ch9120_interface_debug_print("ch9120: set gateway %d.%d.%d.%d.\n",
345 ip[0], ip[1], ip[2], ip[3]);
346
347 /* get gateway */
348 res = ch9120_get_gateway(&gs_handle, ip_check);
349 if (res != 0)
350 {
351 ch9120_interface_debug_print("ch9120: get gateway failed.\n");
352 (void)ch9120_deinit(&gs_handle);
353
354 return 1;
355 }
356
357 /* output */
358 ch9120_interface_debug_print("ch9120: check gateway %s.\n", memcmp(ip, ip_check, 4) == 0 ? "ok" : "error");
359
360 /* ch9120_get_status test */
361 ch9120_interface_debug_print("ch9120: ch9120_get_status test.\n");
362
363 /* status */
364 res = ch9120_get_status(&gs_handle, &status);
365 if (res != 0)
366 {
367 ch9120_interface_debug_print("ch9120: get status failed.\n");
368 (void)ch9120_deinit(&gs_handle);
369
370 return 1;
371 }
372
373 /* output */
374 ch9120_interface_debug_print("ch9120: get status %s.\n", status == CH9120_STATUS_CONNECT ? "connect" : "disconnect");
375
376 /* ch9120_set_mode/ch9120_get_mode test */
377 ch9120_interface_debug_print("ch9120: ch9120_set_mode/ch9120_get_mode test.\n");
378
379 /* tcp server */
380 res = ch9120_set_mode(&gs_handle, CH9120_MODE_TCP_SERVER);
381 if (res != 0)
382 {
383 ch9120_interface_debug_print("ch9120: set mode failed.\n");
384 (void)ch9120_deinit(&gs_handle);
385
386 return 1;
387 }
388
389 /* output */
390 ch9120_interface_debug_print("ch9120: set tcp server mode.\n");
391
392 res = ch9120_get_mode(&gs_handle, &mode);
393 if (res != 0)
394 {
395 ch9120_interface_debug_print("ch9120: get mode failed.\n");
396 (void)ch9120_deinit(&gs_handle);
397
398 return 1;
399 }
400
401 /* output */
402 ch9120_interface_debug_print("ch9120: check mode %s.\n", mode == CH9120_MODE_TCP_SERVER ? "ok" : "error");
403
404 /* tcp client */
405 res = ch9120_set_mode(&gs_handle, CH9120_MODE_TCP_CLIENT);
406 if (res != 0)
407 {
408 ch9120_interface_debug_print("ch9120: set mode failed.\n");
409 (void)ch9120_deinit(&gs_handle);
410
411 return 1;
412 }
413
414 /* output */
415 ch9120_interface_debug_print("ch9120: set tcp client mode.\n");
416
417 res = ch9120_get_mode(&gs_handle, &mode);
418 if (res != 0)
419 {
420 ch9120_interface_debug_print("ch9120: get mode failed.\n");
421 (void)ch9120_deinit(&gs_handle);
422
423 return 1;
424 }
425
426 /* output */
427 ch9120_interface_debug_print("ch9120: check mode %s.\n", mode == CH9120_MODE_TCP_CLIENT ? "ok" : "error");
428
429 /* udp server */
430 res = ch9120_set_mode(&gs_handle, CH9120_MODE_UDP_SERVER);
431 if (res != 0)
432 {
433 ch9120_interface_debug_print("ch9120: set mode failed.\n");
434 (void)ch9120_deinit(&gs_handle);
435
436 return 1;
437 }
438
439 /* output */
440 ch9120_interface_debug_print("ch9120: set udp server mode.\n");
441
442 res = ch9120_get_mode(&gs_handle, &mode);
443 if (res != 0)
444 {
445 ch9120_interface_debug_print("ch9120: get mode failed.\n");
446 (void)ch9120_deinit(&gs_handle);
447
448 return 1;
449 }
450
451 /* output */
452 ch9120_interface_debug_print("ch9120: check mode %s.\n", mode == CH9120_MODE_UDP_SERVER ? "ok" : "error");
453
454 /* udp client */
455 res = ch9120_set_mode(&gs_handle, CH9120_MODE_UDP_CLIENT);
456 if (res != 0)
457 {
458 ch9120_interface_debug_print("ch9120: set mode failed.\n");
459 (void)ch9120_deinit(&gs_handle);
460
461 return 1;
462 }
463
464 /* output */
465 ch9120_interface_debug_print("ch9120: set udp client mode.\n");
466
467 res = ch9120_get_mode(&gs_handle, &mode);
468 if (res != 0)
469 {
470 ch9120_interface_debug_print("ch9120: get mode failed.\n");
471 (void)ch9120_deinit(&gs_handle);
472
473 return 1;
474 }
475
476 /* output */
477 ch9120_interface_debug_print("ch9120: check mode %s.\n", mode == CH9120_MODE_UDP_CLIENT ? "ok" : "error");
478
479 /* ch9120_set_source_port/ch9120_get_source_port test */
480 ch9120_interface_debug_print("ch9120: ch9120_set_source_port/ch9120_get_source_port test.\n");
481
482 /* random */
483 num = rand() % 0xFFFFU;
484
485 /* port */
486 res = ch9120_set_source_port(&gs_handle, num);
487 if (res != 0)
488 {
489 ch9120_interface_debug_print("ch9120: set source port failed.\n");
490 (void)ch9120_deinit(&gs_handle);
491
492 return 1;
493 }
494
495 /* output */
496 ch9120_interface_debug_print("ch9120: set source %d.\n", num);
497
498 /* get source port */
499 res = ch9120_get_source_port(&gs_handle, &num_check);
500 if (res != 0)
501 {
502 ch9120_interface_debug_print("ch9120: get source port failed.\n");
503 (void)ch9120_deinit(&gs_handle);
504
505 return 1;
506 }
507
508 /* output */
509 ch9120_interface_debug_print("ch9120: check source port %s.\n", num_check == num ? "ok" : "error");
510
511 /* ch9120_set_dest_ip/ch9120_get_dest_ip test */
512 ch9120_interface_debug_print("ch9120: ch9120_set_dest_ip/ch9120_get_dest_ip test.\n");
513
514 /* random ip */
515 ip[0] = rand() % 0xFF;
516 ip[1] = rand() % 0xFF;
517 ip[2] = rand() % 0xFF;
518 ip[3] = rand() % 0xFF;
519
520 /* port */
521 res = ch9120_set_dest_ip(&gs_handle, ip);
522 if (res != 0)
523 {
524 ch9120_interface_debug_print("ch9120: set dest ip failed.\n");
525 (void)ch9120_deinit(&gs_handle);
526
527 return 1;
528 }
529
530 /* output */
531 ch9120_interface_debug_print("ch9120: set dest ip %d.%d.%d.%d.\n", ip[0], ip[1], ip[2], ip[3]);
532
533 /* get dest ip */
534 res = ch9120_get_dest_ip(&gs_handle, ip_check);
535 if (res != 0)
536 {
537 ch9120_interface_debug_print("ch9120: get dest ip failed.\n");
538 (void)ch9120_deinit(&gs_handle);
539
540 return 1;
541 }
542
543 /* output */
544 ch9120_interface_debug_print("ch9120: check dest ip %s.\n", memcmp(ip, ip_check, 4) == 0 ? "ok" : "error");
545
546 /* ch9120_set_dest_port/ch9120_get_dest_port test */
547 ch9120_interface_debug_print("ch9120: ch9120_set_dest_port/ch9120_get_dest_port test.\n");
548
549 /* random */
550 num = rand() % 0xFFFFU;
551
552 /* port */
553 res = ch9120_set_dest_port(&gs_handle, num);
554 if (res != 0)
555 {
556 ch9120_interface_debug_print("ch9120: set dest port failed.\n");
557 (void)ch9120_deinit(&gs_handle);
558
559 return 1;
560 }
561
562 /* output */
563 ch9120_interface_debug_print("ch9120: set dest %d.\n", num);
564
565 /* get dest port */
566 res = ch9120_get_dest_port(&gs_handle, &num_check);
567 if (res != 0)
568 {
569 ch9120_interface_debug_print("ch9120: get dest port failed.\n");
570 (void)ch9120_deinit(&gs_handle);
571
572 return 1;
573 }
574
575 /* output */
576 ch9120_interface_debug_print("ch9120: check dest port %s.\n", num_check == num ? "ok" : "error");
577
578 /* ch9120_set_uart_baud/ch9120_get_uart_baud test */
579 ch9120_interface_debug_print("ch9120: ch9120_set_uart_baud/ch9120_get_uart_baud test.\n");
580
581 /* 9600 */
582 baud = 9600;
583
584 /* port */
585 res = ch9120_set_uart_baud(&gs_handle, baud);
586 if (res != 0)
587 {
588 ch9120_interface_debug_print("ch9120: set uart baud failed.\n");
589 (void)ch9120_deinit(&gs_handle);
590
591 return 1;
592 }
593
594 /* output */
595 ch9120_interface_debug_print("ch9120: set uart baud %d.\n", baud);
596
597 /* get uart baud */
598 res = ch9120_get_uart_baud(&gs_handle, &baud_check);
599 if (res != 0)
600 {
601 ch9120_interface_debug_print("ch9120: get uart baud failed.\n");
602 (void)ch9120_deinit(&gs_handle);
603
604 return 1;
605 }
606
607 /* output */
608 ch9120_interface_debug_print("ch9120: check uart baud %s.\n", baud_check == baud ? "ok" : "error");
609
610 /* ch9120_set_uart_config/ch9120_get_uart_config test */
611 ch9120_interface_debug_print("ch9120: ch9120_set_uart_config/ch9120_get_uart_config test.\n");
612
613 /* set uart config */
614 res = ch9120_set_uart_config(&gs_handle, 8, CH9120_PARITY_NONE, 1);
615 if (res != 0)
616 {
617 ch9120_interface_debug_print("ch9120: set uart config failed.\n");
618 (void)ch9120_deinit(&gs_handle);
619
620 return 1;
621 }
622
623 /* output */
624 ch9120_interface_debug_print("ch9120: set data_bit 8, parity none, stop_bit 1.\n");
625
626 /* get uart config */
627 res = ch9120_get_uart_config(&gs_handle, &data_bit, &parity, &stop_bit);
628 if (res != 0)
629 {
630 ch9120_interface_debug_print("ch9120: get uart config failed.\n");
631 (void)ch9120_deinit(&gs_handle);
632
633 return 1;
634 }
635
636 /* output */
637 ch9120_interface_debug_print("ch9120: check uart data bit %s.\n", data_bit == 8 ? "ok" : "error");
638 ch9120_interface_debug_print("ch9120: check uart parity %s.\n", parity == CH9120_PARITY_NONE ? "ok" : "error");
639 ch9120_interface_debug_print("ch9120: check uart stop bit %s.\n", stop_bit == 1 ? "ok" : "error");
640
641 /* ch9120_set_uart_timeout/ch9120_get_uart_timeout test */
642 ch9120_interface_debug_print("ch9120: ch9120_set_uart_timeout/ch9120_get_uart_timeout test.\n");
643
644 /* random timeout */
645 timeout = rand() % 0xFF;
646
647 /* set uart timeout */
648 res = ch9120_set_uart_timeout(&gs_handle, timeout);
649 if (res != 0)
650 {
651 ch9120_interface_debug_print("ch9120: set uart timeout failed.\n");
652 (void)ch9120_deinit(&gs_handle);
653
654 return 1;
655 }
656
657 /* output */
658 ch9120_interface_debug_print("ch9120: set uart timeout %d.\n", timeout);
659
660 /* get uart timeout */
661 res = ch9120_get_uart_timeout(&gs_handle, &timeout_check);
662 if (res != 0)
663 {
664 ch9120_interface_debug_print("ch9120: get uart timeout failed.\n");
665 (void)ch9120_deinit(&gs_handle);
666
667 return 1;
668 }
669
670 /* output */
671 ch9120_interface_debug_print("ch9120: check uart timeout %s.\n", timeout_check == timeout ? "ok" : "error");
672
673 /* ch9120_set_source_port_random test */
674 ch9120_interface_debug_print("ch9120: ch9120_set_source_port_random test.\n");
675
676 /* enable */
678 if (res != 0)
679 {
680 ch9120_interface_debug_print("ch9120: set source port random failed.\n");
681 (void)ch9120_deinit(&gs_handle);
682
683 return 1;
684 }
685
686 /* output */
687 ch9120_interface_debug_print("ch9120: enable source port random.\n");
688
689 /* output */
690 ch9120_interface_debug_print("ch9120: check source port random %s.\n", res == 0 ? "ok" : "error");
691
692 /* disable */
694 if (res != 0)
695 {
696 ch9120_interface_debug_print("ch9120: set source port random failed.\n");
697 (void)ch9120_deinit(&gs_handle);
698
699 return 1;
700 }
701
702 /* output */
703 ch9120_interface_debug_print("ch9120: disable source port random.\n");
704
705 /* output */
706 ch9120_interface_debug_print("ch9120: check source port random %s.\n", res == 0 ? "ok" : "error");
707
708 /* ch9120_set_uart_buffer_length/ch9120_get_uart_buffer_length test */
709 ch9120_interface_debug_print("ch9120: ch9120_set_uart_buffer_length/ch9120_get_uart_buffer_length test.\n");
710
711 /* random len */
712 len = 128 + rand() % 50;
713 res = ch9120_set_uart_buffer_length(&gs_handle, len);
714 if (res != 0)
715 {
716 ch9120_interface_debug_print("ch9120: set uart buffer length failed.\n");
717 (void)ch9120_deinit(&gs_handle);
718
719 return 1;
720 }
721 ch9120_interface_debug_print("ch9120: set uart buffer length %d.\n", len);
722 res = ch9120_get_uart_buffer_length(&gs_handle, &len_check);
723 if (res != 0)
724 {
725 ch9120_interface_debug_print("ch9120: get uart buffer length failed.\n");
726 (void)ch9120_deinit(&gs_handle);
727
728 return 1;
729 }
730
731 /* output */
732 ch9120_interface_debug_print("ch9120: check uart buffer length %s.\n", len == len_check ? "ok" : "error");
733
734 /* ch9120_set_uart_flush test/ch9120_get_uart_flush */
735 ch9120_interface_debug_print("ch9120: ch9120_set_uart_flush test/ch9120_get_uart_flush.\n");
736
737 /* enable uart flush */
738 res = ch9120_set_uart_flush(&gs_handle, CH9120_BOOL_TRUE);
739 if (res != 0)
740 {
741 ch9120_interface_debug_print("ch9120: set uart flush failed.\n");
742 (void)ch9120_deinit(&gs_handle);
743
744 return 1;
745 }
746 ch9120_interface_debug_print("ch9120: enable uart flush.\n");
747 res = ch9120_get_uart_flush(&gs_handle, &enable);
748 if (res != 0)
749 {
750 ch9120_interface_debug_print("ch9120: get uart flush failed.\n");
751 (void)ch9120_deinit(&gs_handle);
752
753 return 1;
754 }
755 ch9120_interface_debug_print("ch9120: check uart flush %s.\n", enable == CH9120_BOOL_TRUE ? "ok" : "error");
756
757 /* disable uart flush */
758 res = ch9120_set_uart_flush(&gs_handle, CH9120_BOOL_FALSE);
759 if (res != 0)
760 {
761 ch9120_interface_debug_print("ch9120: set uart flush failed.\n");
762 (void)ch9120_deinit(&gs_handle);
763
764 return 1;
765 }
766 ch9120_interface_debug_print("ch9120: disable uart flush.\n");
767 res = ch9120_get_uart_flush(&gs_handle, &enable);
768 if (res != 0)
769 {
770 ch9120_interface_debug_print("ch9120: get uart flush failed.\n");
771 (void)ch9120_deinit(&gs_handle);
772
773 return 1;
774 }
775 ch9120_interface_debug_print("ch9120: check uart flush %s.\n", enable == CH9120_BOOL_FALSE ? "ok" : "error");
776
777 /* ch9120_uart_timeout_convert_to_register/ch9120_uart_timeout_convert_to_data test */
778 ch9120_interface_debug_print("ch9120: ch9120_uart_timeout_convert_to_register/ch9120_uart_timeout_convert_to_data test.\n");
779
780 /* random ms */
781 ms = (rand() % 10) * 5;
782
783 /* uart timeout convert to register */
784 res = ch9120_uart_timeout_convert_to_register(&gs_handle, ms, &reg);
785 if (res != 0)
786 {
787 ch9120_interface_debug_print("ch9120: uart timeout convert to register failed.\n");
788 (void)ch9120_deinit(&gs_handle);
789
790 return 1;
791 }
792
793 /* output */
794 ch9120_interface_debug_print("ch9120: uart timeout convert to register %d.\n", ms);
795
796 /* uart timeout convert to data */
797 res = ch9120_uart_timeout_convert_to_data(&gs_handle, reg, &ms_check);
798 if (res != 0)
799 {
800 ch9120_interface_debug_print("ch9120: uart timeout convert to data failed.\n");
801 (void)ch9120_deinit(&gs_handle);
802
803 return 1;
804 }
805
806 /* output */
807 ch9120_interface_debug_print("ch9120: check uart timeout convert %s.\n", ms == ms_check ? "ok" : "error");
808
809 /* finish register test */
810 ch9120_interface_debug_print("ch9120: finish register test.\n");
811 (void)ch9120_deinit(&gs_handle);
812
813 return 0;
814}
driver ch9120 register test header file
uint8_t ch9120_set_uart_baud(ch9120_handle_t *handle, uint32_t baud)
set uart baud
uint8_t ch9120_set_dest_ip(ch9120_handle_t *handle, uint8_t ip[4])
set dest ip
uint8_t ch9120_get_status(ch9120_handle_t *handle, ch9120_status_t *status)
get status
uint8_t ch9120_get_disconnect_with_no_rj45(ch9120_handle_t *handle, ch9120_bool_t *enable)
get disconnect with no rj45 status
uint8_t ch9120_get_gateway(ch9120_handle_t *handle, uint8_t ip[4])
get gateway
uint8_t ch9120_get_uart_baud(ch9120_handle_t *handle, uint32_t *baud)
get uart baud
uint8_t ch9120_get_dest_port(ch9120_handle_t *handle, uint16_t *num)
get dest port
struct ch9120_info_s ch9120_info_t
ch9120 information structure definition
uint8_t ch9120_get_uart_buffer_length(ch9120_handle_t *handle, uint32_t *len)
get uart buffer length
uint8_t ch9120_uart_timeout_convert_to_data(ch9120_handle_t *handle, uint8_t reg, uint16_t *ms)
convert the register raw data to the offset
uint8_t ch9120_init(ch9120_handle_t *handle)
initialize the chip
uint8_t ch9120_get_ip(ch9120_handle_t *handle, uint8_t ip[4])
get ip address
ch9120_mode_t
ch9120 mode enumeration definition
struct ch9120_handle_s ch9120_handle_t
ch9120 handle structure definition
uint8_t ch9120_get_source_port(ch9120_handle_t *handle, uint16_t *num)
get source port
ch9120_parity_t
ch9120 parity enumeration definition
uint8_t ch9120_get_uart_timeout(ch9120_handle_t *handle, uint8_t *timeout)
get uart timeout
uint8_t ch9120_set_dest_port(ch9120_handle_t *handle, uint16_t num)
set dest port
uint8_t ch9120_set_source_port_random(ch9120_handle_t *handle, ch9120_bool_t enable)
enable or disable random source port number
uint8_t ch9120_set_uart_config(ch9120_handle_t *handle, uint8_t data_bit, ch9120_parity_t parity, uint8_t stop_bit)
set uart config
uint8_t ch9120_set_uart_buffer_length(ch9120_handle_t *handle, uint32_t len)
set uart buffer length
uint8_t ch9120_set_uart_flush(ch9120_handle_t *handle, ch9120_bool_t enable)
enable or disable uart auto flush
uint8_t ch9120_get_dest_ip(ch9120_handle_t *handle, uint8_t ip[4])
get dest ip
uint8_t ch9120_deinit(ch9120_handle_t *handle)
close the chip
uint8_t ch9120_get_uart_flush(ch9120_handle_t *handle, ch9120_bool_t *enable)
get uart auto flush status
uint8_t ch9120_set_gateway(ch9120_handle_t *handle, uint8_t ip[4])
set gateway
uint8_t ch9120_set_uart_timeout(ch9120_handle_t *handle, uint8_t timeout)
set uart timeout
uint8_t ch9120_get_uart_config(ch9120_handle_t *handle, uint8_t *data_bit, ch9120_parity_t *parity, uint8_t *stop_bit)
get uart config
uint8_t ch9120_exit(ch9120_handle_t *handle)
exit
uint8_t ch9120_get_mode(ch9120_handle_t *handle, ch9120_mode_t *mode)
get mode
uint8_t ch9120_set_disconnect_with_no_rj45(ch9120_handle_t *handle, ch9120_bool_t enable)
enable or disable disconnect with no rj45
uint8_t ch9120_info(ch9120_info_t *info)
get chip's information
uint8_t ch9120_set_mode(ch9120_handle_t *handle, ch9120_mode_t mode)
set mode
uint8_t ch9120_get_subnet_mask(ch9120_handle_t *handle, uint8_t mask[4])
get subnet mask
uint8_t ch9120_uart_timeout_convert_to_register(ch9120_handle_t *handle, uint16_t ms, uint8_t *reg)
convert the uart timeout to the register raw data
uint8_t ch9120_set_dhcp(ch9120_handle_t *handle, ch9120_bool_t enable)
enable or disable dhcp
ch9120_bool_t
ch9120 bool enumeration definition
uint8_t ch9120_save_to_eeprom(ch9120_handle_t *handle)
save to eeprom
uint8_t ch9120_set_subnet_mask(ch9120_handle_t *handle, uint8_t mask[4])
set subnet mask
ch9120_status_t
ch9120 status enumeration definition
uint8_t ch9120_set_ip(ch9120_handle_t *handle, uint8_t ip[4])
set ip address
uint8_t ch9120_get_version(ch9120_handle_t *handle, uint8_t *version)
get version
uint8_t ch9120_set_source_port(ch9120_handle_t *handle, uint16_t num)
set source port
@ CH9120_MODE_UDP_CLIENT
@ CH9120_MODE_TCP_SERVER
@ CH9120_MODE_UDP_SERVER
@ CH9120_MODE_TCP_CLIENT
@ CH9120_PARITY_NONE
@ CH9120_BOOL_FALSE
@ CH9120_BOOL_TRUE
@ CH9120_STATUS_CONNECT
uint8_t ch9120_interface_uart_write(uint8_t *buf, uint16_t len)
interface uart write
uint8_t ch9120_interface_cfg_gpio_init(void)
interface cfg gpio init
uint16_t ch9120_interface_uart_read(uint8_t *buf, uint16_t len)
interface uart read
uint8_t ch9120_interface_reset_gpio_init(void)
interface reset gpio init
uint8_t ch9120_interface_cfg_gpio_write(uint8_t data)
interface cfg gpio write
uint8_t ch9120_interface_reset_gpio_deinit(void)
interface reset gpio deinit
uint8_t ch9120_interface_uart_init(void)
interface uart init
uint8_t ch9120_interface_uart_flush(void)
interface uart flush
uint8_t ch9120_interface_uart_deinit(void)
interface uart deinit
uint8_t ch9120_interface_cfg_gpio_deinit(void)
interface cfg gpio deinit
void ch9120_interface_debug_print(const char *const fmt,...)
interface print format data
uint8_t ch9120_interface_reset_gpio_write(uint8_t data)
interface reset gpio write
void ch9120_interface_delay_ms(uint32_t ms)
interface delay ms
uint8_t ch9120_register_test(void)
register test
float supply_voltage_max_v
uint32_t driver_version
char manufacturer_name[32]
float supply_voltage_min_v
char chip_name[32]