LibDriver CH9121X
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driver_ch9121x_register_test.c
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1
36
37#include "driver_ch9121x_register_test.h"
38#include <stdlib.h>
39
40static ch9121x_handle_t gs_handle;
41
49uint8_t ch9121x_register_test(void)
50{
51 uint8_t res;
52 uint8_t reg;
53 uint8_t reg_check;
54 uint8_t version;
55 uint8_t timeout;
56 uint8_t timeout_check;
57 uint8_t mac[6];
58 uint8_t mac_check[6];
59 uint8_t ip[4];
60 uint8_t ip_check[4];
61 uint8_t mask[4];
62 uint8_t mask_check[4];
63 uint16_t num;
64 uint16_t num_check;
65 uint32_t baud;
66 uint32_t baud_check;
67 uint32_t len;
68 uint32_t len_check;
69 uint8_t data_bit;
70 uint8_t stop_bit;
71 uint16_t ms;
72 uint16_t ms_check;
73 ch9121x_parity_t parity;
74 ch9121x_info_t info;
75 ch9121x_status_t status;
76 ch9121x_mode_t mode;
77 ch9121x_bool_t enable;
78 ch9121x_uart_clock_mode_t uart_clock_mode;
79 ch9121x_phy_status_t phy_status;
80 char domain[] = "www.ch9121x.com";
81
82 /* link interface function */
83 DRIVER_CH9121X_LINK_INIT(&gs_handle, ch9121x_handle_t);
84 DRIVER_CH9121X_LINK_UART_INIT(&gs_handle, ch9121x_interface_uart_init);
85 DRIVER_CH9121X_LINK_UART_DEINIT(&gs_handle, ch9121x_interface_uart_deinit);
86 DRIVER_CH9121X_LINK_UART_READ(&gs_handle, ch9121x_interface_uart_read);
87 DRIVER_CH9121X_LINK_UART_WRITE(&gs_handle, ch9121x_interface_uart_write);
88 DRIVER_CH9121X_LINK_UART_FLUSH(&gs_handle, ch9121x_interface_uart_flush);
89 DRIVER_CH9121X_LINK_RESET_GPIO_INIT(&gs_handle, ch9121x_interface_reset_gpio_init);
90 DRIVER_CH9121X_LINK_RESET_GPIO_DEINIT(&gs_handle, ch9121x_interface_reset_gpio_deinit);
91 DRIVER_CH9121X_LINK_RESET_GPIO_WRITE(&gs_handle, ch9121x_interface_reset_gpio_write);
92 DRIVER_CH9121X_LINK_CFG_GPIO_INIT(&gs_handle, ch9121x_interface_cfg_gpio_init);
93 DRIVER_CH9121X_LINK_CFG_GPIO_DEINIT(&gs_handle, ch9121x_interface_cfg_gpio_deinit);
94 DRIVER_CH9121X_LINK_CFG_GPIO_WRITE(&gs_handle, ch9121x_interface_cfg_gpio_write);
95 DRIVER_CH9121X_LINK_DELAY_MS(&gs_handle, ch9121x_interface_delay_ms);
96 DRIVER_CH9121X_LINK_DEBUG_PRINT(&gs_handle, ch9121x_interface_debug_print);
97
98 /* get ch9121x information */
99 res = ch9121x_info(&info);
100 if (res != 0)
101 {
102 ch9121x_interface_debug_print("ch9121x: get info failed.\n");
103
104 return 1;
105 }
106 else
107 {
108 /* print chip information */
109 ch9121x_interface_debug_print("ch9121x: chip is %s.\n", info.chip_name);
110 ch9121x_interface_debug_print("ch9121x: manufacturer is %s.\n", info.manufacturer_name);
111 ch9121x_interface_debug_print("ch9121x: interface is %s.\n", info.interface);
112 ch9121x_interface_debug_print("ch9121x: driver version is %d.%d.\n", info.driver_version / 1000, (info.driver_version % 1000) / 100);
113 ch9121x_interface_debug_print("ch9121x: min supply voltage is %0.1fV.\n", info.supply_voltage_min_v);
114 ch9121x_interface_debug_print("ch9121x: max supply voltage is %0.1fV.\n", info.supply_voltage_max_v);
115 ch9121x_interface_debug_print("ch9121x: max current is %0.2fmA.\n", info.max_current_ma);
116 ch9121x_interface_debug_print("ch9121x: max temperature is %0.1fC.\n", info.temperature_max);
117 ch9121x_interface_debug_print("ch9121x: min temperature is %0.1fC.\n", info.temperature_min);
118 }
119
120 /* start register test */
121 ch9121x_interface_debug_print("ch9121x: start register test.\n");
122
123 /* ch9121x init */
124 res = ch9121x_init(&gs_handle);
125 if (res != 0)
126 {
127 ch9121x_interface_debug_print("ch9121x: init failed.\n");
128
129 return 1;
130 }
131
132 /* ch9121x_get_version test */
133 ch9121x_interface_debug_print("ch9121x: ch9121x_get_version test.\n");
134
135 /* get version */
136 res = ch9121x_get_version(&gs_handle, &version);
137 if (res != 0)
138 {
139 ch9121x_interface_debug_print("ch9121x: get version failed.\n");
140 (void)ch9121x_deinit(&gs_handle);
141
142 return 1;
143 }
144
145 /* output */
146 ch9121x_interface_debug_print("ch9121x: version is 0x%02X.\n", version);
147
148 /* ch9121x_save_to_eeprom test */
149 ch9121x_interface_debug_print("ch9121x: ch9121x_save_to_eeprom test.\n");
150
151 /* save to eeprom */
152 res = ch9121x_save_to_eeprom(&gs_handle);
153 if (res != 0)
154 {
155 ch9121x_interface_debug_print("ch9121x: save to eeprom failed.\n");
156 (void)ch9121x_deinit(&gs_handle);
157
158 return 1;
159 }
160
161 /* output */
162 ch9121x_interface_debug_print("ch9121x: check save to eeprom %s.\n", res == 0 ? "ok" : "error");
163
164 /* ch9121x_exit test */
165 ch9121x_interface_debug_print("ch9121x: ch9121x_exit test.\n");
166
167 /* exit */
168 res = ch9121x_exit(&gs_handle);
169 if (res != 0)
170 {
171 ch9121x_interface_debug_print("ch9121x: exit failed.\n");
172 (void)ch9121x_deinit(&gs_handle);
173
174 return 1;
175 }
176
177 /* output */
178 ch9121x_interface_debug_print("ch9121x: check exit %s.\n", res == 0 ? "ok" : "error");
179
180 /* ch9121x_set_port2 test */
181 ch9121x_interface_debug_print("ch9121x: ch9121x_set_port2 test.\n");
182
183 /* disable port2 */
184 res = ch9121x_set_port2(&gs_handle, CH9121X_BOOL_FALSE);
185 if (res != 0)
186 {
187 ch9121x_interface_debug_print("ch9121x: set port2 failed.\n");
188 (void)ch9121x_deinit(&gs_handle);
189
190 return 1;
191 }
192
193 /* disable port2 */
194 ch9121x_interface_debug_print("ch9121x: disable port2.\n");
195
196 /* output */
197 ch9121x_interface_debug_print("ch9121x: check port2 %s.\n", res == 0 ? "ok" : "error");
198
199 /* enable port2 */
200 res = ch9121x_set_port2(&gs_handle, CH9121X_BOOL_TRUE);
201 if (res != 0)
202 {
203 ch9121x_interface_debug_print("ch9121x: set port2 failed.\n");
204 (void)ch9121x_deinit(&gs_handle);
205
206 return 1;
207 }
208
209 /* enable port2 */
210 ch9121x_interface_debug_print("ch9121x: enable port2.\n");
211
212 /* output */
213 ch9121x_interface_debug_print("ch9121x: check port2 %s.\n", res == 0 ? "ok" : "error");
214
215 /* ch9121x_set_disconnect_with_no_rj45/ch9121x_get_disconnect_with_no_rj45 test */
216 ch9121x_interface_debug_print("ch9121x: ch9121x_set_disconnect_with_no_rj45/ch9121x_get_disconnect_with_no_rj45 test.\n");
217
218 /* disable */
219 res = ch9121x_set_disconnect_with_no_rj45(&gs_handle, CH9121X_BOOL_FALSE);
220 if (res != 0)
221 {
222 ch9121x_interface_debug_print("ch9121x: set disconnect with no rj45 failed.\n");
223 (void)ch9121x_deinit(&gs_handle);
224
225 return 1;
226 }
227 ch9121x_interface_debug_print("ch9121x: disable disconnect with no rj45.\n");
228 res = ch9121x_get_disconnect_with_no_rj45(&gs_handle, &enable);
229 if (res != 0)
230 {
231 ch9121x_interface_debug_print("ch9121x: get disconnect with no rj45 failed.\n");
232 (void)ch9121x_deinit(&gs_handle);
233
234 return 1;
235 }
236
237 /* output */
238 ch9121x_interface_debug_print("ch9121x: check disconnect with no rj45 %s.\n", enable == CH9121X_BOOL_FALSE ? "ok" : "error");
239
240 /* enable */
241 res = ch9121x_set_disconnect_with_no_rj45(&gs_handle, CH9121X_BOOL_TRUE);
242 if (res != 0)
243 {
244 ch9121x_interface_debug_print("ch9121x: set disconnect with no rj45 failed.\n");
245 (void)ch9121x_deinit(&gs_handle);
246
247 return 1;
248 }
249 ch9121x_interface_debug_print("ch9121x: enable disconnect with no rj45.\n");
250 res = ch9121x_get_disconnect_with_no_rj45(&gs_handle, &enable);
251 if (res != 0)
252 {
253 ch9121x_interface_debug_print("ch9121x: get disconnect with no rj45 failed.\n");
254 (void)ch9121x_deinit(&gs_handle);
255
256 return 1;
257 }
258
259 /* output */
260 ch9121x_interface_debug_print("ch9121x: check disconnect with no rj45 %s.\n", enable == CH9121X_BOOL_TRUE ? "ok" : "error");
261
262 /* ch9121x_set_domain test */
263 ch9121x_interface_debug_print("ch9121x: ch9121x_set_domain test.\n");
264
265 /* set domain */
266 res = ch9121x_set_domain(&gs_handle, domain);
267 if (res != 0)
268 {
269 ch9121x_interface_debug_print("ch9121x: set domain failed.\n");
270 (void)ch9121x_deinit(&gs_handle);
271
272 return 1;
273 }
274
275 /* set domain */
276 ch9121x_interface_debug_print("ch9121x: set domain %s.\n", domain);
277
278 /* output */
279 ch9121x_interface_debug_print("ch9121x: check domain %s.\n", res == 0 ? "ok" : "error");
280
281 /* ch9121x_set_dhcp/ch9121x_get_dhcp test */
282 ch9121x_interface_debug_print("ch9121x: ch9121x_set_dhcp/ch9121x_get_dhcp test.\n");
283
284 /* disable dhcp */
285 res = ch9121x_set_dhcp(&gs_handle, CH9121X_BOOL_FALSE);
286 if (res != 0)
287 {
288 ch9121x_interface_debug_print("ch9121x: set dhcp failed.\n");
289 (void)ch9121x_deinit(&gs_handle);
290
291 return 1;
292 }
293 ch9121x_interface_debug_print("ch9121x: disable dhcp.\n");
294 res = ch9121x_get_dhcp(&gs_handle, &enable);
295 if (res != 0)
296 {
297 ch9121x_interface_debug_print("ch9121x: get dhcp failed.\n");
298 (void)ch9121x_deinit(&gs_handle);
299
300 return 1;
301 }
302
303 /* output */
304 ch9121x_interface_debug_print("ch9121x: check dhcp %s.\n", enable == CH9121X_BOOL_FALSE ? "ok" : "error");
305
306 /* enable dhcp */
307 res = ch9121x_set_dhcp(&gs_handle, CH9121X_BOOL_TRUE);
308 if (res != 0)
309 {
310 ch9121x_interface_debug_print("ch9121x: set dhcp failed.\n");
311 (void)ch9121x_deinit(&gs_handle);
312
313 return 1;
314 }
315 ch9121x_interface_debug_print("ch9121x: enable dhcp.\n");
316 res = ch9121x_get_dhcp(&gs_handle, &enable);
317 if (res != 0)
318 {
319 ch9121x_interface_debug_print("ch9121x: get dhcp failed.\n");
320 (void)ch9121x_deinit(&gs_handle);
321
322 return 1;
323 }
324
325 /* output */
326 ch9121x_interface_debug_print("ch9121x: check dhcp %s.\n", enable == CH9121X_BOOL_TRUE ? "ok" : "error");
327
328 /* ch9121x_set_mac/ch9121x_get_mac test */
329 ch9121x_interface_debug_print("ch9121x: ch9121x_set_mac/ch9121x_get_mac test.\n");
330
331 mac[0] = rand() % 0xFF;
332 mac[1] = rand() % 0xFF;
333 mac[2] = rand() % 0xFF;
334 mac[3] = rand() % 0xFF;
335 mac[4] = rand() % 0xFF;
336 mac[5] = rand() % 0xFF;
337 res = ch9121x_set_mac(&gs_handle, mac);
338 if (res != 0)
339 {
340 ch9121x_interface_debug_print("ch9121x: set mac failed.\n");
341 (void)ch9121x_deinit(&gs_handle);
342
343 return 1;
344 }
345 ch9121x_interface_debug_print("ch9121x: set mac 0x%02X 0x%02X 0x%02X 0x%02X 0x%02X 0x%02X.\n",
346 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
347 res = ch9121x_get_mac(&gs_handle, mac_check);
348 if (res != 0)
349 {
350 ch9121x_interface_debug_print("ch9121x: get mac failed.\n");
351 (void)ch9121x_deinit(&gs_handle);
352
353 return 1;
354 }
355
356 /* output */
357 ch9121x_interface_debug_print("ch9121x: check mac[0] %s.\n", mac[0] == mac_check[0] ? "ok" : "error");
358 ch9121x_interface_debug_print("ch9121x: check mac[1] %s.\n", mac[1] == mac_check[1] ? "ok" : "error");
359 ch9121x_interface_debug_print("ch9121x: check mac[2] %s.\n", mac[2] == mac_check[2] ? "ok" : "error");
360 ch9121x_interface_debug_print("ch9121x: check mac[3] %s.\n", mac[3] == mac_check[3] ? "ok" : "error");
361 ch9121x_interface_debug_print("ch9121x: check mac[4] %s.\n", mac[4] == mac_check[4] ? "ok" : "error");
362 ch9121x_interface_debug_print("ch9121x: check mac[5] %s.\n", mac[5] == mac_check[5] ? "ok" : "error");
363
364 /* ch9121x_clear_mac test */
365 ch9121x_interface_debug_print("ch9121x: ch9121x_clear_mac test.\n");
366
367 /* clear mac */
368 res = ch9121x_clear_mac(&gs_handle);
369 if (res != 0)
370 {
371 ch9121x_interface_debug_print("ch9121x: clear mac failed.\n");
372 (void)ch9121x_deinit(&gs_handle);
373
374 return 1;
375 }
376
377 /* get mac */
378 res = ch9121x_get_mac(&gs_handle, mac);
379 if (res != 0)
380 {
381 ch9121x_interface_debug_print("ch9121x: get mac failed.\n");
382 (void)ch9121x_deinit(&gs_handle);
383
384 return 1;
385 }
386
387 /* output */
388 ch9121x_interface_debug_print("ch9121x: default mac is 0x%02X 0x%02X 0x%02X 0x%02X 0x%02X 0x%02X.\n",
389 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
390
391 /* ch9121x_set_ip/ch9121x_get_ip test */
392 ch9121x_interface_debug_print("ch9121x: ch9121x_set_ip/ch9121x_get_ip test.\n");
393
394 /* random ip */
395 ip[0] = rand() % 0xFF;
396 ip[1] = rand() % 0xFF;
397 ip[2] = rand() % 0xFF;
398 ip[3] = rand() % 0xFF;
399
400 /* set ip */
401 res = ch9121x_set_ip(&gs_handle, ip);
402 if (res != 0)
403 {
404 ch9121x_interface_debug_print("ch9121x: set ip failed.\n");
405 (void)ch9121x_deinit(&gs_handle);
406
407 return 1;
408 }
409
410 /* output */
411 ch9121x_interface_debug_print("ch9121x: set ip %d.%d.%d.%d.\n",
412 ip[0], ip[1], ip[2], ip[3]);
413
414 /* get ip */
415 res = ch9121x_get_ip(&gs_handle, ip_check);
416 if (res != 0)
417 {
418 ch9121x_interface_debug_print("ch9121x: get ip failed.\n");
419 (void)ch9121x_deinit(&gs_handle);
420
421 return 1;
422 }
423
424 /* output */
425 ch9121x_interface_debug_print("ch9121x: check ip %s.\n", memcmp(ip, ip_check, 4) == 0 ? "ok" : "error");
426
427 /* ch9121x_set_subnet_mask/ch9121x_get_subnet_mask test */
428 ch9121x_interface_debug_print("ch9121x: ch9121x_set_subnet_mask/ch9121x_get_subnet_mask test.\n");
429
430 /* random mask */
431 mask[0] = rand() % 0xFF;
432 mask[1] = rand() % 0xFF;
433 mask[2] = rand() % 0xFF;
434 mask[3] = rand() % 0xFF;
435
436 /* set subnet mask */
437 res = ch9121x_set_subnet_mask(&gs_handle, mask);
438 if (res != 0)
439 {
440 ch9121x_interface_debug_print("ch9121x: set subnet mask failed.\n");
441 (void)ch9121x_deinit(&gs_handle);
442
443 return 1;
444 }
445
446 /* output */
447 ch9121x_interface_debug_print("ch9121x: set subnet mask %d.%d.%d.%d.\n",
448 mask[0], mask[1], mask[2], mask[3]);
449
450 /* get subnet mask */
451 res = ch9121x_get_subnet_mask(&gs_handle, mask_check);
452 if (res != 0)
453 {
454 ch9121x_interface_debug_print("ch9121x: get subnet mask failed.\n");
455 (void)ch9121x_deinit(&gs_handle);
456
457 return 1;
458 }
459
460 /* output */
461 ch9121x_interface_debug_print("ch9121x: check subnet mask %s.\n", memcmp(mask, mask_check, 4) == 0 ? "ok" : "error");
462
463 /* ch9121x_set_gateway/ch9121x_get_gateway test */
464 ch9121x_interface_debug_print("ch9121x: ch9121x_set_gateway/ch9121x_get_gateway test.\n");
465
466 /* random ip */
467 ip[0] = rand() % 0xFF;
468 ip[1] = rand() % 0xFF;
469 ip[2] = rand() % 0xFF;
470 ip[3] = rand() % 0xFF;
471
472 /* set gateway */
473 res = ch9121x_set_gateway(&gs_handle, ip);
474 if (res != 0)
475 {
476 ch9121x_interface_debug_print("ch9121x: set gateway failed.\n");
477 (void)ch9121x_deinit(&gs_handle);
478
479 return 1;
480 }
481
482 /* output */
483 ch9121x_interface_debug_print("ch9121x: set gateway %d.%d.%d.%d.\n",
484 ip[0], ip[1], ip[2], ip[3]);
485
486 /* get gateway */
487 res = ch9121x_get_gateway(&gs_handle, ip_check);
488 if (res != 0)
489 {
490 ch9121x_interface_debug_print("ch9121x: get gateway failed.\n");
491 (void)ch9121x_deinit(&gs_handle);
492
493 return 1;
494 }
495
496 /* output */
497 ch9121x_interface_debug_print("ch9121x: check gateway %s.\n", memcmp(ip, ip_check, 4) == 0 ? "ok" : "error");
498
499 /* ch9121x_get_status test */
500 ch9121x_interface_debug_print("ch9121x: ch9121x_get_status test.\n");
501
502 /* port1 */
503 res = ch9121x_get_status(&gs_handle, CH9121X_PORT1, &status);
504 if (res != 0)
505 {
506 ch9121x_interface_debug_print("ch9121x: get status failed.\n");
507 (void)ch9121x_deinit(&gs_handle);
508
509 return 1;
510 }
511
512 /* output */
513 ch9121x_interface_debug_print("ch9121x: get port1 status %s.\n", status == CH9121X_STATUS_CONNECT ? "connect" : "disconnect");
514
515 /* port2 */
516 res = ch9121x_get_status(&gs_handle, CH9121X_PORT2, &status);
517 if (res != 0)
518 {
519 ch9121x_interface_debug_print("ch9121x: get status failed.\n");
520 (void)ch9121x_deinit(&gs_handle);
521
522 return 1;
523 }
524
525 /* output */
526 ch9121x_interface_debug_print("ch9121x: get port2 status %s.\n", status == CH9121X_STATUS_CONNECT ? "connect" : "disconnect");
527
528 /* ch9121x_set_mode/ch9121x_get_mode test */
529 ch9121x_interface_debug_print("ch9121x: ch9121x_set_mode/ch9121x_get_mode test.\n");
530
531 /* tcp server */
532 res = ch9121x_set_mode(&gs_handle, CH9121X_PORT1, CH9121X_MODE_TCP_SERVER);
533 if (res != 0)
534 {
535 ch9121x_interface_debug_print("ch9121x: set mode failed.\n");
536 (void)ch9121x_deinit(&gs_handle);
537
538 return 1;
539 }
540
541 /* output */
542 ch9121x_interface_debug_print("ch9121x: set port1 tcp server mode.\n");
543
544 res = ch9121x_get_mode(&gs_handle, CH9121X_PORT1, &mode);
545 if (res != 0)
546 {
547 ch9121x_interface_debug_print("ch9121x: get mode failed.\n");
548 (void)ch9121x_deinit(&gs_handle);
549
550 return 1;
551 }
552
553 /* output */
554 ch9121x_interface_debug_print("ch9121x: check mode %s.\n", mode == CH9121X_MODE_TCP_SERVER ? "ok" : "error");
555
556 /* tcp client */
557 res = ch9121x_set_mode(&gs_handle, CH9121X_PORT1, CH9121X_MODE_TCP_CLIENT);
558 if (res != 0)
559 {
560 ch9121x_interface_debug_print("ch9121x: set mode failed.\n");
561 (void)ch9121x_deinit(&gs_handle);
562
563 return 1;
564 }
565
566 /* output */
567 ch9121x_interface_debug_print("ch9121x: set port1 tcp client mode.\n");
568
569 res = ch9121x_get_mode(&gs_handle, CH9121X_PORT1, &mode);
570 if (res != 0)
571 {
572 ch9121x_interface_debug_print("ch9121x: get mode failed.\n");
573 (void)ch9121x_deinit(&gs_handle);
574
575 return 1;
576 }
577
578 /* output */
579 ch9121x_interface_debug_print("ch9121x: check mode %s.\n", mode == CH9121X_MODE_TCP_CLIENT ? "ok" : "error");
580
581 /* udp server */
582 res = ch9121x_set_mode(&gs_handle, CH9121X_PORT1, CH9121X_MODE_UDP_SERVER);
583 if (res != 0)
584 {
585 ch9121x_interface_debug_print("ch9121x: set mode failed.\n");
586 (void)ch9121x_deinit(&gs_handle);
587
588 return 1;
589 }
590
591 /* output */
592 ch9121x_interface_debug_print("ch9121x: set port1 udp server mode.\n");
593
594 res = ch9121x_get_mode(&gs_handle, CH9121X_PORT1, &mode);
595 if (res != 0)
596 {
597 ch9121x_interface_debug_print("ch9121x: get mode failed.\n");
598 (void)ch9121x_deinit(&gs_handle);
599
600 return 1;
601 }
602
603 /* output */
604 ch9121x_interface_debug_print("ch9121x: check mode %s.\n", mode == CH9121X_MODE_UDP_SERVER ? "ok" : "error");
605
606 /* udp client */
607 res = ch9121x_set_mode(&gs_handle, CH9121X_PORT1, CH9121X_MODE_UDP_CLIENT);
608 if (res != 0)
609 {
610 ch9121x_interface_debug_print("ch9121x: set mode failed.\n");
611 (void)ch9121x_deinit(&gs_handle);
612
613 return 1;
614 }
615
616 /* output */
617 ch9121x_interface_debug_print("ch9121x: set port1 udp client mode.\n");
618
619 res = ch9121x_get_mode(&gs_handle, CH9121X_PORT1, &mode);
620 if (res != 0)
621 {
622 ch9121x_interface_debug_print("ch9121x: get mode failed.\n");
623 (void)ch9121x_deinit(&gs_handle);
624
625 return 1;
626 }
627
628 /* output */
629 ch9121x_interface_debug_print("ch9121x: check mode %s.\n", mode == CH9121X_MODE_UDP_CLIENT ? "ok" : "error");
630
631 /* tcp server */
632 res = ch9121x_set_mode(&gs_handle, CH9121X_PORT2, CH9121X_MODE_TCP_SERVER);
633 if (res != 0)
634 {
635 ch9121x_interface_debug_print("ch9121x: set mode failed.\n");
636 (void)ch9121x_deinit(&gs_handle);
637
638 return 1;
639 }
640
641 /* output */
642 ch9121x_interface_debug_print("ch9121x: set port2 tcp server mode.\n");
643
644 res = ch9121x_get_mode(&gs_handle, CH9121X_PORT2, &mode);
645 if (res != 0)
646 {
647 ch9121x_interface_debug_print("ch9121x: get mode failed.\n");
648 (void)ch9121x_deinit(&gs_handle);
649
650 return 1;
651 }
652
653 /* output */
654 ch9121x_interface_debug_print("ch9121x: check mode %s.\n", mode == CH9121X_MODE_TCP_SERVER ? "ok" : "error");
655
656 /* tcp client */
657 res = ch9121x_set_mode(&gs_handle, CH9121X_PORT2, CH9121X_MODE_TCP_CLIENT);
658 if (res != 0)
659 {
660 ch9121x_interface_debug_print("ch9121x: set mode failed.\n");
661 (void)ch9121x_deinit(&gs_handle);
662
663 return 1;
664 }
665
666 /* output */
667 ch9121x_interface_debug_print("ch9121x: set port2 tcp client mode.\n");
668
669 res = ch9121x_get_mode(&gs_handle, CH9121X_PORT2, &mode);
670 if (res != 0)
671 {
672 ch9121x_interface_debug_print("ch9121x: get mode failed.\n");
673 (void)ch9121x_deinit(&gs_handle);
674
675 return 1;
676 }
677
678 /* output */
679 ch9121x_interface_debug_print("ch9121x: check mode %s.\n", mode == CH9121X_MODE_TCP_CLIENT ? "ok" : "error");
680
681 /* udp server */
682 res = ch9121x_set_mode(&gs_handle, CH9121X_PORT2, CH9121X_MODE_UDP_SERVER);
683 if (res != 0)
684 {
685 ch9121x_interface_debug_print("ch9121x: set mode failed.\n");
686 (void)ch9121x_deinit(&gs_handle);
687
688 return 1;
689 }
690
691 /* output */
692 ch9121x_interface_debug_print("ch9121x: set port2 udp server mode.\n");
693
694 res = ch9121x_get_mode(&gs_handle, CH9121X_PORT2, &mode);
695 if (res != 0)
696 {
697 ch9121x_interface_debug_print("ch9121x: get mode failed.\n");
698 (void)ch9121x_deinit(&gs_handle);
699
700 return 1;
701 }
702
703 /* output */
704 ch9121x_interface_debug_print("ch9121x: check mode %s.\n", mode == CH9121X_MODE_UDP_SERVER ? "ok" : "error");
705
706 /* udp client */
707 res = ch9121x_set_mode(&gs_handle, CH9121X_PORT2, CH9121X_MODE_UDP_CLIENT);
708 if (res != 0)
709 {
710 ch9121x_interface_debug_print("ch9121x: set mode failed.\n");
711 (void)ch9121x_deinit(&gs_handle);
712
713 return 1;
714 }
715
716 /* output */
717 ch9121x_interface_debug_print("ch9121x: set port2 udp client mode.\n");
718
719 res = ch9121x_get_mode(&gs_handle, CH9121X_PORT2, &mode);
720 if (res != 0)
721 {
722 ch9121x_interface_debug_print("ch9121x: get mode failed.\n");
723 (void)ch9121x_deinit(&gs_handle);
724
725 return 1;
726 }
727
728 /* output */
729 ch9121x_interface_debug_print("ch9121x: check mode %s.\n", mode == CH9121X_MODE_UDP_CLIENT ? "ok" : "error");
730
731 /* ch9121x_set_source_port/ch9121x_get_source_port test */
732 ch9121x_interface_debug_print("ch9121x: ch9121x_set_source_port/ch9121x_get_source_port test.\n");
733
734 /* random */
735 num = rand() % 0xFFFFU;
736
737 /* port1 */
738 res = ch9121x_set_source_port(&gs_handle, CH9121X_PORT1, num);
739 if (res != 0)
740 {
741 ch9121x_interface_debug_print("ch9121x: set source port failed.\n");
742 (void)ch9121x_deinit(&gs_handle);
743
744 return 1;
745 }
746
747 /* output */
748 ch9121x_interface_debug_print("ch9121x: set source port1 %d.\n", num);
749
750 /* get source port */
751 res = ch9121x_get_source_port(&gs_handle, CH9121X_PORT1, &num_check);
752 if (res != 0)
753 {
754 ch9121x_interface_debug_print("ch9121x: get source port failed.\n");
755 (void)ch9121x_deinit(&gs_handle);
756
757 return 1;
758 }
759
760 /* output */
761 ch9121x_interface_debug_print("ch9121x: check source port %s.\n", num_check == num ? "ok" : "error");
762
763 /* random */
764 num = rand() % 0xFFFFU;
765
766 /* port2 */
767 res = ch9121x_set_source_port(&gs_handle, CH9121X_PORT2, num);
768 if (res != 0)
769 {
770 ch9121x_interface_debug_print("ch9121x: set source port failed.\n");
771 (void)ch9121x_deinit(&gs_handle);
772
773 return 1;
774 }
775
776 /* output */
777 ch9121x_interface_debug_print("ch9121x: set source port2 %d.\n", num);
778
779 /* get source port */
780 res = ch9121x_get_source_port(&gs_handle, CH9121X_PORT2, &num_check);
781 if (res != 0)
782 {
783 ch9121x_interface_debug_print("ch9121x: get source port failed.\n");
784 (void)ch9121x_deinit(&gs_handle);
785
786 return 1;
787 }
788
789 /* output */
790 ch9121x_interface_debug_print("ch9121x: check source port %s.\n", num_check == num ? "ok" : "error");
791
792 /* ch9121x_set_dest_ip/ch9121x_get_dest_ip test */
793 ch9121x_interface_debug_print("ch9121x: ch9121x_set_dest_ip/ch9121x_get_dest_ip test.\n");
794
795 /* random ip */
796 ip[0] = rand() % 0xFF;
797 ip[1] = rand() % 0xFF;
798 ip[2] = rand() % 0xFF;
799 ip[3] = rand() % 0xFF;
800
801 /* port1 */
802 res = ch9121x_set_dest_ip(&gs_handle, CH9121X_PORT1, ip);
803 if (res != 0)
804 {
805 ch9121x_interface_debug_print("ch9121x: set dest ip failed.\n");
806 (void)ch9121x_deinit(&gs_handle);
807
808 return 1;
809 }
810
811 /* output */
812 ch9121x_interface_debug_print("ch9121x: set port1 dest ip %d.%d.%d.%d.\n", ip[0], ip[1], ip[2], ip[3]);
813
814 /* get dest ip */
815 res = ch9121x_get_dest_ip(&gs_handle, CH9121X_PORT1, ip_check);
816 if (res != 0)
817 {
818 ch9121x_interface_debug_print("ch9121x: get dest ip failed.\n");
819 (void)ch9121x_deinit(&gs_handle);
820
821 return 1;
822 }
823
824 /* output */
825 ch9121x_interface_debug_print("ch9121x: check dest ip %s.\n", memcmp(ip, ip_check, 4) == 0 ? "ok" : "error");
826
827 /* random ip */
828 ip[0] = rand() % 0xFF;
829 ip[1] = rand() % 0xFF;
830 ip[2] = rand() % 0xFF;
831 ip[3] = rand() % 0xFF;
832
833 /* port2 */
834 res = ch9121x_set_dest_ip(&gs_handle, CH9121X_PORT2, ip);
835 if (res != 0)
836 {
837 ch9121x_interface_debug_print("ch9121x: set dest ip failed.\n");
838 (void)ch9121x_deinit(&gs_handle);
839
840 return 1;
841 }
842
843 /* output */
844 ch9121x_interface_debug_print("ch9121x: set port2 dest ip %d.%d.%d.%d.\n", ip[0], ip[1], ip[2], ip[3]);
845
846 /* get dest ip */
847 res = ch9121x_get_dest_ip(&gs_handle, CH9121X_PORT2, ip_check);
848 if (res != 0)
849 {
850 ch9121x_interface_debug_print("ch9121x: get dest ip failed.\n");
851 (void)ch9121x_deinit(&gs_handle);
852
853 return 1;
854 }
855
856 /* output */
857 ch9121x_interface_debug_print("ch9121x: check dest ip %s.\n", memcmp(ip, ip_check, 4) == 0 ? "ok" : "error");
858
859 /* ch9121x_set_dest_port/ch9121x_get_dest_port test */
860 ch9121x_interface_debug_print("ch9121x: ch9121x_set_dest_port/ch9121x_get_dest_port test.\n");
861
862 /* random */
863 num = rand() % 0xFFFFU;
864
865 /* port1 */
866 res = ch9121x_set_dest_port(&gs_handle, CH9121X_PORT1, num);
867 if (res != 0)
868 {
869 ch9121x_interface_debug_print("ch9121x: set dest port failed.\n");
870 (void)ch9121x_deinit(&gs_handle);
871
872 return 1;
873 }
874
875 /* output */
876 ch9121x_interface_debug_print("ch9121x: set dest port1 %d.\n", num);
877
878 /* get dest port */
879 res = ch9121x_get_dest_port(&gs_handle, CH9121X_PORT1, &num_check);
880 if (res != 0)
881 {
882 ch9121x_interface_debug_print("ch9121x: get dest port failed.\n");
883 (void)ch9121x_deinit(&gs_handle);
884
885 return 1;
886 }
887
888 /* output */
889 ch9121x_interface_debug_print("ch9121x: check dest port %s.\n", num_check == num ? "ok" : "error");
890
891 /* random */
892 num = rand() % 0xFFFFU;
893
894 /* port2 */
895 res = ch9121x_set_dest_port(&gs_handle, CH9121X_PORT2, num);
896 if (res != 0)
897 {
898 ch9121x_interface_debug_print("ch9121x: set dest port failed.\n");
899 (void)ch9121x_deinit(&gs_handle);
900
901 return 1;
902 }
903
904 /* output */
905 ch9121x_interface_debug_print("ch9121x: set dest port2 %d.\n", num);
906
907 /* get dest port */
908 res = ch9121x_get_dest_port(&gs_handle, CH9121X_PORT2, &num_check);
909 if (res != 0)
910 {
911 ch9121x_interface_debug_print("ch9121x: get dest port failed.\n");
912 (void)ch9121x_deinit(&gs_handle);
913
914 return 1;
915 }
916
917 /* output */
918 ch9121x_interface_debug_print("ch9121x: check dest port %s.\n", num_check == num ? "ok" : "error");
919
920 /* ch9121x_set_uart_baud/ch9121x_get_uart_baud test */
921 ch9121x_interface_debug_print("ch9121x: ch9121x_set_uart_baud/ch9121x_get_uart_baud test.\n");
922
923 /* 9600 */
924 baud = 9600;
925
926 /* port1 */
927 res = ch9121x_set_uart_baud(&gs_handle, CH9121X_PORT1, baud);
928 if (res != 0)
929 {
930 ch9121x_interface_debug_print("ch9121x: set uart baud failed.\n");
931 (void)ch9121x_deinit(&gs_handle);
932
933 return 1;
934 }
935
936 /* output */
937 ch9121x_interface_debug_print("ch9121x: set port1 uart baud %d.\n", baud);
938
939 /* get uart baud */
940 res = ch9121x_get_uart_baud(&gs_handle, CH9121X_PORT1, &baud_check);
941 if (res != 0)
942 {
943 ch9121x_interface_debug_print("ch9121x: get uart baud failed.\n");
944 (void)ch9121x_deinit(&gs_handle);
945
946 return 1;
947 }
948
949 /* output */
950 ch9121x_interface_debug_print("ch9121x: check uart baud %s.\n", baud_check == baud ? "ok" : "error");
951
952 /* 9600 */
953 baud = 9600;
954
955 /* port2 */
956 res = ch9121x_set_uart_baud(&gs_handle, CH9121X_PORT2, baud);
957 if (res != 0)
958 {
959 ch9121x_interface_debug_print("ch9121x: set uart baud failed.\n");
960 (void)ch9121x_deinit(&gs_handle);
961
962 return 1;
963 }
964
965 /* output */
966 ch9121x_interface_debug_print("ch9121x: set port2 uart baud %d.\n", baud);
967
968 /* get uart baud */
969 res = ch9121x_get_uart_baud(&gs_handle, CH9121X_PORT2, &baud_check);
970 if (res != 0)
971 {
972 ch9121x_interface_debug_print("ch9121x: get uart baud failed.\n");
973 (void)ch9121x_deinit(&gs_handle);
974
975 return 1;
976 }
977
978 /* output */
979 ch9121x_interface_debug_print("ch9121x: check uart baud %s.\n", baud_check == baud ? "ok" : "error");
980
981 /* ch9121x_set_uart_config/ch9121x_get_uart_config test */
982 ch9121x_interface_debug_print("ch9121x: ch9121x_set_uart_config/ch9121x_get_uart_config test.\n");
983
984 /* set uart config */
985 res = ch9121x_set_uart_config(&gs_handle, CH9121X_PORT1, 8, CH9121X_PARITY_NONE, 1);
986 if (res != 0)
987 {
988 ch9121x_interface_debug_print("ch9121x: set uart config failed.\n");
989 (void)ch9121x_deinit(&gs_handle);
990
991 return 1;
992 }
993
994 /* output */
995 ch9121x_interface_debug_print("ch9121x: set port1 data_bit 8, parity none, stop_bit 1.\n");
996
997 /* get uart config */
998 res = ch9121x_get_uart_config(&gs_handle, CH9121X_PORT1, &data_bit, &parity, &stop_bit);
999 if (res != 0)
1000 {
1001 ch9121x_interface_debug_print("ch9121x: get uart config failed.\n");
1002 (void)ch9121x_deinit(&gs_handle);
1003
1004 return 1;
1005 }
1006
1007 /* output */
1008 ch9121x_interface_debug_print("ch9121x: check uart data bit %s.\n", data_bit == 8 ? "ok" : "error");
1009 ch9121x_interface_debug_print("ch9121x: check uart parity %s.\n", parity == CH9121X_PARITY_NONE ? "ok" : "error");
1010 ch9121x_interface_debug_print("ch9121x: check uart stop bit %s.\n", stop_bit == 1 ? "ok" : "error");
1011
1012 /* set uart config */
1013 res = ch9121x_set_uart_config(&gs_handle, CH9121X_PORT2, 8, CH9121X_PARITY_NONE, 1);
1014 if (res != 0)
1015 {
1016 ch9121x_interface_debug_print("ch9121x: set uart config failed.\n");
1017 (void)ch9121x_deinit(&gs_handle);
1018
1019 return 1;
1020 }
1021
1022 /* output */
1023 ch9121x_interface_debug_print("ch9121x: set port2 data_bit 8, parity none, stop_bit 1.\n");
1024
1025 /* get uart config */
1026 res = ch9121x_get_uart_config(&gs_handle, CH9121X_PORT2, &data_bit, &parity, &stop_bit);
1027 if (res != 0)
1028 {
1029 ch9121x_interface_debug_print("ch9121x: get uart config failed.\n");
1030 (void)ch9121x_deinit(&gs_handle);
1031
1032 return 1;
1033 }
1034
1035 /* output */
1036 ch9121x_interface_debug_print("ch9121x: check uart data bit %s.\n", data_bit == 8 ? "ok" : "error");
1037 ch9121x_interface_debug_print("ch9121x: check uart parity %s.\n", parity == CH9121X_PARITY_NONE ? "ok" : "error");
1038 ch9121x_interface_debug_print("ch9121x: check uart stop bit %s.\n", stop_bit == 1 ? "ok" : "error");
1039
1040 /* ch9121x_set_uart_timeout/ch9121x_get_uart_timeout test */
1041 ch9121x_interface_debug_print("ch9121x: ch9121x_set_uart_timeout/ch9121x_get_uart_timeout test.\n");
1042
1043 /* random timeout */
1044 timeout = rand() % 0xFF;
1045
1046 /* set uart timeout */
1047 res = ch9121x_set_uart_timeout(&gs_handle, CH9121X_PORT1, timeout);
1048 if (res != 0)
1049 {
1050 ch9121x_interface_debug_print("ch9121x: set uart timeout failed.\n");
1051 (void)ch9121x_deinit(&gs_handle);
1052
1053 return 1;
1054 }
1055
1056 /* output */
1057 ch9121x_interface_debug_print("ch9121x: set port1 uart timeout %d.\n", timeout);
1058
1059 /* get uart timeout */
1060 res = ch9121x_get_uart_timeout(&gs_handle, CH9121X_PORT1, &timeout_check);
1061 if (res != 0)
1062 {
1063 ch9121x_interface_debug_print("ch9121x: get uart timeout failed.\n");
1064 (void)ch9121x_deinit(&gs_handle);
1065
1066 return 1;
1067 }
1068
1069 /* output */
1070 ch9121x_interface_debug_print("ch9121x: check uart timeout %s.\n", timeout_check == timeout ? "ok" : "error");
1071
1072 /* random timeout */
1073 timeout = rand() % 0xFF;
1074
1075 /* set uart timeout */
1076 res = ch9121x_set_uart_timeout(&gs_handle, CH9121X_PORT2, timeout);
1077 if (res != 0)
1078 {
1079 ch9121x_interface_debug_print("ch9121x: set uart timeout failed.\n");
1080 (void)ch9121x_deinit(&gs_handle);
1081
1082 return 1;
1083 }
1084
1085 /* output */
1086 ch9121x_interface_debug_print("ch9121x: set port2 uart timeout %d.\n", timeout);
1087
1088 /* get uart timeout */
1089 res = ch9121x_get_uart_timeout(&gs_handle, CH9121X_PORT2, &timeout_check);
1090 if (res != 0)
1091 {
1092 ch9121x_interface_debug_print("ch9121x: get uart timeout failed.\n");
1093 (void)ch9121x_deinit(&gs_handle);
1094
1095 return 1;
1096 }
1097
1098 /* output */
1099 ch9121x_interface_debug_print("ch9121x: check uart timeout %s.\n", timeout_check == timeout ? "ok" : "error");
1100
1101 /* ch9121x_set_source_port_random/ch9121x_get_source_port_random test */
1102 ch9121x_interface_debug_print("ch9121x: ch9121x_set_source_port_random/ch9121x_get_source_port_random test.\n");
1103
1104 /* port1 */
1105 res = ch9121x_set_source_port_random(&gs_handle, CH9121X_PORT1, CH9121X_BOOL_TRUE);
1106 if (res != 0)
1107 {
1108 ch9121x_interface_debug_print("ch9121x: set source port random failed.\n");
1109 (void)ch9121x_deinit(&gs_handle);
1110
1111 return 1;
1112 }
1113 ch9121x_interface_debug_print("ch9121x: enable port1 source port random.\n");
1114 res = ch9121x_get_source_port_random(&gs_handle, CH9121X_PORT1, &enable);
1115 if (res != 0)
1116 {
1117 ch9121x_interface_debug_print("ch9121x: get source port random failed.\n");
1118 (void)ch9121x_deinit(&gs_handle);
1119
1120 return 1;
1121 }
1122
1123 /* output */
1124 ch9121x_interface_debug_print("ch9121x: check source port random %s.\n", enable == CH9121X_BOOL_TRUE ? "ok" : "error");
1125
1126 /* port1 */
1127 res = ch9121x_set_source_port_random(&gs_handle, CH9121X_PORT1, CH9121X_BOOL_FALSE);
1128 if (res != 0)
1129 {
1130 ch9121x_interface_debug_print("ch9121x: set source port random failed.\n");
1131 (void)ch9121x_deinit(&gs_handle);
1132
1133 return 1;
1134 }
1135 ch9121x_interface_debug_print("ch9121x: disable port1 source port random.\n");
1136 res = ch9121x_get_source_port_random(&gs_handle, CH9121X_PORT1, &enable);
1137 if (res != 0)
1138 {
1139 ch9121x_interface_debug_print("ch9121x: get source port random failed.\n");
1140 (void)ch9121x_deinit(&gs_handle);
1141
1142 return 1;
1143 }
1144
1145 /* output */
1146 ch9121x_interface_debug_print("ch9121x: check source port random %s.\n", enable == CH9121X_BOOL_FALSE ? "ok" : "error");
1147
1148 /* port2 */
1149 res = ch9121x_set_source_port_random(&gs_handle, CH9121X_PORT2, CH9121X_BOOL_TRUE);
1150 if (res != 0)
1151 {
1152 ch9121x_interface_debug_print("ch9121x: set source port random failed.\n");
1153 (void)ch9121x_deinit(&gs_handle);
1154
1155 return 1;
1156 }
1157 ch9121x_interface_debug_print("ch9121x: enable port2 source port random.\n");
1158 res = ch9121x_get_source_port_random(&gs_handle, CH9121X_PORT2, &enable);
1159 if (res != 0)
1160 {
1161 ch9121x_interface_debug_print("ch9121x: get source port random failed.\n");
1162 (void)ch9121x_deinit(&gs_handle);
1163
1164 return 1;
1165 }
1166
1167 /* output */
1168 ch9121x_interface_debug_print("ch9121x: check source port random %s.\n", enable == CH9121X_BOOL_TRUE ? "ok" : "error");
1169
1170 /* port2 */
1171 res = ch9121x_set_source_port_random(&gs_handle, CH9121X_PORT2, CH9121X_BOOL_FALSE);
1172 if (res != 0)
1173 {
1174 ch9121x_interface_debug_print("ch9121x: set source port random failed.\n");
1175 (void)ch9121x_deinit(&gs_handle);
1176
1177 return 1;
1178 }
1179 ch9121x_interface_debug_print("ch9121x: disable port2 source port random.\n");
1180 res = ch9121x_get_source_port_random(&gs_handle, CH9121X_PORT2, &enable);
1181 if (res != 0)
1182 {
1183 ch9121x_interface_debug_print("ch9121x: get source port random failed.\n");
1184 (void)ch9121x_deinit(&gs_handle);
1185
1186 return 1;
1187 }
1188
1189 /* output */
1190 ch9121x_interface_debug_print("ch9121x: check source port random %s.\n", enable == CH9121X_BOOL_FALSE ? "ok" : "error");
1191
1192 /* ch9121x_set_uart_buffer_length/ch9121x_get_uart_buffer_length test */
1193 ch9121x_interface_debug_print("ch9121x: ch9121x_set_uart_buffer_length/ch9121x_get_uart_buffer_length test.\n");
1194
1195 /* random len */
1196 len = 128 + rand() % 50;
1197
1198 /* set_uart_buffer_length */
1199 res = ch9121x_set_uart_buffer_length(&gs_handle, CH9121X_PORT1, len);
1200 if (res != 0)
1201 {
1202 ch9121x_interface_debug_print("ch9121x: set uart buffer length failed.\n");
1203 (void)ch9121x_deinit(&gs_handle);
1204
1205 return 1;
1206 }
1207 ch9121x_interface_debug_print("ch9121x: set port1 uart buffer length %d.\n", len);
1208 res = ch9121x_get_uart_buffer_length(&gs_handle, CH9121X_PORT1, &len_check);
1209 if (res != 0)
1210 {
1211 ch9121x_interface_debug_print("ch9121x: get uart buffer length failed.\n");
1212 (void)ch9121x_deinit(&gs_handle);
1213
1214 return 1;
1215 }
1216
1217 /* output */
1218 ch9121x_interface_debug_print("ch9121x: check uart buffer length %s.\n", len == len_check ? "ok" : "error");
1219
1220 /* random len */
1221 len = 128 + rand() % 50;
1222
1223 /* set_uart_buffer_length */
1224 res = ch9121x_set_uart_buffer_length(&gs_handle, CH9121X_PORT2, len);
1225 if (res != 0)
1226 {
1227 ch9121x_interface_debug_print("ch9121x: set uart buffer length failed.\n");
1228 (void)ch9121x_deinit(&gs_handle);
1229
1230 return 1;
1231 }
1232 ch9121x_interface_debug_print("ch9121x: set port2 uart buffer length %d.\n", len);
1233 res = ch9121x_get_uart_buffer_length(&gs_handle, CH9121X_PORT2, &len_check);
1234 if (res != 0)
1235 {
1236 ch9121x_interface_debug_print("ch9121x: get uart buffer length failed.\n");
1237 (void)ch9121x_deinit(&gs_handle);
1238
1239 return 1;
1240 }
1241
1242 /* output */
1243 ch9121x_interface_debug_print("ch9121x: check uart buffer length %s.\n", len == len_check ? "ok" : "error");
1244
1245 /* ch9121x_set_uart_flush/ch9121x_get_uart_flush test */
1246 ch9121x_interface_debug_print("ch9121x: ch9121x_set_uart_flush/ch9121x_get_uart_flush test.\n");
1247
1248 /* enable uart flush */
1249 res = ch9121x_set_uart_flush(&gs_handle, CH9121X_PORT1, CH9121X_BOOL_TRUE);
1250 if (res != 0)
1251 {
1252 ch9121x_interface_debug_print("ch9121x: set uart flush failed.\n");
1253 (void)ch9121x_deinit(&gs_handle);
1254
1255 return 1;
1256 }
1257 ch9121x_interface_debug_print("ch9121x: enable port1 uart flush.\n");
1258 res = ch9121x_get_uart_flush(&gs_handle, CH9121X_PORT1, &enable);
1259 if (res != 0)
1260 {
1261 ch9121x_interface_debug_print("ch9121x: get uart flush failed.\n");
1262 (void)ch9121x_deinit(&gs_handle);
1263
1264 return 1;
1265 }
1266
1267 /* output */
1268 ch9121x_interface_debug_print("ch9121x: check uart flush %s.\n", enable == CH9121X_BOOL_TRUE ? "ok" : "error");
1269
1270 /* disable uart flush */
1271 res = ch9121x_set_uart_flush(&gs_handle, CH9121X_PORT1, CH9121X_BOOL_FALSE);
1272 if (res != 0)
1273 {
1274 ch9121x_interface_debug_print("ch9121x: set uart flush failed.\n");
1275 (void)ch9121x_deinit(&gs_handle);
1276
1277 return 1;
1278 }
1279 ch9121x_interface_debug_print("ch9121x: disable port1 uart flush.\n");
1280 res = ch9121x_get_uart_flush(&gs_handle, CH9121X_PORT1, &enable);
1281 if (res != 0)
1282 {
1283 ch9121x_interface_debug_print("ch9121x: get uart flush failed.\n");
1284 (void)ch9121x_deinit(&gs_handle);
1285
1286 return 1;
1287 }
1288
1289 /* output */
1290 ch9121x_interface_debug_print("ch9121x: check uart flush %s.\n", enable == CH9121X_BOOL_FALSE ? "ok" : "error");
1291
1292 /* enable uart flush */
1293 res = ch9121x_set_uart_flush(&gs_handle, CH9121X_PORT2, CH9121X_BOOL_TRUE);
1294 if (res != 0)
1295 {
1296 ch9121x_interface_debug_print("ch9121x: set uart flush failed.\n");
1297 (void)ch9121x_deinit(&gs_handle);
1298
1299 return 1;
1300 }
1301 ch9121x_interface_debug_print("ch9121x: enable port2 uart flush.\n");
1302 res = ch9121x_get_uart_flush(&gs_handle, CH9121X_PORT2, &enable);
1303 if (res != 0)
1304 {
1305 ch9121x_interface_debug_print("ch9121x: get uart flush failed.\n");
1306 (void)ch9121x_deinit(&gs_handle);
1307
1308 return 1;
1309 }
1310
1311 /* output */
1312 ch9121x_interface_debug_print("ch9121x: check uart flush %s.\n", enable == CH9121X_BOOL_TRUE ? "ok" : "error");
1313
1314 /* disable uart flush */
1315 res = ch9121x_set_uart_flush(&gs_handle, CH9121X_PORT2, CH9121X_BOOL_FALSE);
1316 if (res != 0)
1317 {
1318 ch9121x_interface_debug_print("ch9121x: set uart flush failed.\n");
1319 (void)ch9121x_deinit(&gs_handle);
1320
1321 return 1;
1322 }
1323 ch9121x_interface_debug_print("ch9121x: disable port2 uart flush.\n");
1324 res = ch9121x_get_uart_flush(&gs_handle, CH9121X_PORT2, &enable);
1325 if (res != 0)
1326 {
1327 ch9121x_interface_debug_print("ch9121x: get uart flush failed.\n");
1328 (void)ch9121x_deinit(&gs_handle);
1329
1330 return 1;
1331 }
1332
1333 /* output */
1334 ch9121x_interface_debug_print("ch9121x: check uart flush %s.\n", enable == CH9121X_BOOL_FALSE ? "ok" : "error");
1335
1336 /* ch9121x_set_eth_cfg/ch9121x_get_eth_cfg test */
1337 ch9121x_interface_debug_print("ch9121x: ch9121x_set_eth_cfg/ch9121x_get_eth_cfg test.\n");
1338
1339 /* enable eth cfg */
1340 res = ch9121x_set_eth_cfg(&gs_handle, CH9121X_BOOL_TRUE);
1341 if (res != 0)
1342 {
1343 ch9121x_interface_debug_print("ch9121x: set eth cfg failed.\n");
1344 (void)ch9121x_deinit(&gs_handle);
1345
1346 return 1;
1347 }
1348 ch9121x_interface_debug_print("ch9121x: enable eth cfg.\n");
1349 res = ch9121x_get_eth_cfg(&gs_handle, &enable);
1350 if (res != 0)
1351 {
1352 ch9121x_interface_debug_print("ch9121x: get eth cfg failed.\n");
1353 (void)ch9121x_deinit(&gs_handle);
1354
1355 return 1;
1356 }
1357
1358 /* output */
1359 ch9121x_interface_debug_print("ch9121x: check eth cfg %s.\n", enable == CH9121X_BOOL_TRUE ? "ok" : "error");
1360
1361 /* ch9121x_set_uart_clock_mode/ch9121x_get_uart_clock_mode test */
1362 ch9121x_interface_debug_print("ch9121x: ch9121x_set_uart_clock_mode/ch9121x_get_uart_clock_mode test.\n");
1363
1364 /* set uart clock mode default */
1365 res = ch9121x_set_uart_clock_mode(&gs_handle, CH9121X_UART_CLOCK_MODE_DEFAULT);
1366 if (res != 0)
1367 {
1368 ch9121x_interface_debug_print("ch9121x: set uart clock mode failed.\n");
1369 (void)ch9121x_deinit(&gs_handle);
1370
1371 return 1;
1372 }
1373 ch9121x_interface_debug_print("ch9121x: set uart clock mode default.\n");
1374 res = ch9121x_get_uart_clock_mode(&gs_handle, &uart_clock_mode);
1375 if (res != 0)
1376 {
1377 ch9121x_interface_debug_print("ch9121x: get uart clock mode failed.\n");
1378 (void)ch9121x_deinit(&gs_handle);
1379
1380 return 1;
1381 }
1382
1383 /* output */
1384 ch9121x_interface_debug_print("ch9121x: check uart clock mode %s.\n", uart_clock_mode == CH9121X_UART_CLOCK_MODE_DEFAULT ? "ok" : "error");
1385
1386 /* set uart clock mode classical */
1387 res = ch9121x_set_uart_clock_mode(&gs_handle, CH9121X_UART_CLOCK_MODE_CLASSICAL);
1388 if (res != 0)
1389 {
1390 ch9121x_interface_debug_print("ch9121x: set uart clock mode failed.\n");
1391 (void)ch9121x_deinit(&gs_handle);
1392
1393 return 1;
1394 }
1395 ch9121x_interface_debug_print("ch9121x: set uart clock mode classical.\n");
1396 res = ch9121x_get_uart_clock_mode(&gs_handle, &uart_clock_mode);
1397 if (res != 0)
1398 {
1399 ch9121x_interface_debug_print("ch9121x: get uart clock mode failed.\n");
1400 (void)ch9121x_deinit(&gs_handle);
1401
1402 return 1;
1403 }
1404
1405 /* output */
1406 ch9121x_interface_debug_print("ch9121x: check uart clock mode %s.\n", uart_clock_mode == CH9121X_UART_CLOCK_MODE_CLASSICAL ? "ok" : "error");
1407
1408 /* ch9121x_set_tcp_retry_mode/ch9121x_get_tcp_retry_mode test */
1409 ch9121x_interface_debug_print("ch9121x: ch9121x_set_tcp_retry_mode/ch9121x_get_tcp_retry_mode test.\n");
1410
1411 reg = 2;
1412 res = ch9121x_set_tcp_retry_mode(&gs_handle, reg);
1413 if (res != 0)
1414 {
1415 ch9121x_interface_debug_print("ch9121x: set tcp retry mode failed.\n");
1416 (void)ch9121x_deinit(&gs_handle);
1417
1418 return 1;
1419 }
1420 ch9121x_interface_debug_print("ch9121x: set tcp retry %d.\n", reg);
1421 res = ch9121x_get_tcp_retry_mode(&gs_handle, &reg_check);
1422 if (res != 0)
1423 {
1424 ch9121x_interface_debug_print("ch9121x: get tcp retry mode failed.\n");
1425 (void)ch9121x_deinit(&gs_handle);
1426
1427 return 1;
1428 }
1429
1430 /* output */
1431 ch9121x_interface_debug_print("ch9121x: check tcp retry %s.\n", reg == reg_check ? "ok" : "error");
1432
1433#ifndef CH9121X_DISABLE_FLOW_CONTROL_TEST
1434 /* ch9121x_set_flow_control/ch9121x_get_flow_control test */
1435 ch9121x_interface_debug_print("ch9121x: ch9121x_set_flow_control/ch9121x_get_flow_control test.\n");
1436
1437 /* enable flow control */
1438 res = ch9121x_set_flow_control(&gs_handle, CH9121X_BOOL_TRUE);
1439 if (res != 0)
1440 {
1441 ch9121x_interface_debug_print("ch9121x: set flow control failed.\n");
1442 (void)ch9121x_deinit(&gs_handle);
1443
1444 return 1;
1445 }
1446 ch9121x_interface_debug_print("ch9121x: enable flow control.\n");
1447 res = ch9121x_get_flow_control(&gs_handle, &enable);
1448 if (res != 0)
1449 {
1450 ch9121x_interface_debug_print("ch9121x: get flow control failed.\n");
1451 (void)ch9121x_deinit(&gs_handle);
1452
1453 return 1;
1454 }
1455
1456 /* output */
1457 ch9121x_interface_debug_print("ch9121x: check flow control %s.\n", enable == CH9121X_BOOL_TRUE ? "ok" : "error");
1458
1459 /* disable flow control */
1460 res = ch9121x_set_flow_control(&gs_handle, CH9121X_BOOL_FALSE);
1461 if (res != 0)
1462 {
1463 ch9121x_interface_debug_print("ch9121x: set flow control failed.\n");
1464 (void)ch9121x_deinit(&gs_handle);
1465
1466 return 1;
1467 }
1468 ch9121x_interface_debug_print("ch9121x: disable flow control.\n");
1469 res = ch9121x_get_flow_control(&gs_handle, &enable);
1470 if (res != 0)
1471 {
1472 ch9121x_interface_debug_print("ch9121x: get flow control failed.\n");
1473 (void)ch9121x_deinit(&gs_handle);
1474
1475 return 1;
1476 }
1477
1478 /* output */
1479 ch9121x_interface_debug_print("ch9121x: check flow control %s.\n", enable == CH9121X_BOOL_FALSE ? "ok" : "error");
1480#endif
1481
1482 /* ch9121x_set_arp_retry test */
1483 ch9121x_interface_debug_print("ch9121x: ch9121x_set_arp_retry test.\n");
1484
1485 /* set arp retry */
1486 res = ch9121x_set_arp_retry(&gs_handle, 0, 0);
1487 if (res != 0)
1488 {
1489 ch9121x_interface_debug_print("ch9121x: set arp retry failed.\n");
1490 (void)ch9121x_deinit(&gs_handle);
1491
1492 return 1;
1493 }
1494
1495 /* output */
1496 ch9121x_interface_debug_print("ch9121x: check arp retry %s.\n", res == 0 ? "ok" : "error");
1497
1498 /* ch9121x_get_phy_status test */
1499 ch9121x_interface_debug_print("ch9121x: ch9121x_get_phy_status test.\n");
1500
1501 /* get phy status */
1502 res = ch9121x_get_phy_status(&gs_handle, &phy_status);
1503 if (res != 0)
1504 {
1505 ch9121x_interface_debug_print("ch9121x: get phy status failed.\n");
1506 (void)ch9121x_deinit(&gs_handle);
1507
1508 return 1;
1509 }
1510
1511 /* output */
1512 if (phy_status == CH9121X_PHY_STATUS_DISCONNECTED)
1513 {
1514 ch9121x_interface_debug_print("ch9121x: phy status is disconnected.\n");
1515 }
1516 else if (phy_status == CH9121X_PHY_STATUS_10M_FULL_DUPLEX)
1517 {
1518 ch9121x_interface_debug_print("ch9121x: phy status is 10Mbps full duplex.\n");
1519 }
1520 else if (phy_status == CH9121X_PHY_STATUS_10M_HALF_DUPLEX)
1521 {
1522 ch9121x_interface_debug_print("ch9121x: phy status is 10Mbps half duplex.\n");
1523 }
1524 else if (phy_status == CH9121X_PHY_STATUS_100M_FULL_DUPLEX)
1525 {
1526 ch9121x_interface_debug_print("ch9121x: phy status is 100Mbps full duplex.\n");
1527 }
1528 else if (phy_status == CH9121X_PHY_STATUS_100M_HALF_DUPLEX)
1529 {
1530 ch9121x_interface_debug_print("ch9121x: phy status is 100Mbps half duplex.\n");
1531 }
1532 else
1533 {
1534 ch9121x_interface_debug_print("ch9121x: phy status is unknown.\n");
1535 }
1536
1537 /* ch9121x_uart_timeout_convert_to_register/ch9121x_uart_timeout_convert_to_data test */
1538 ch9121x_interface_debug_print("ch9121x: ch9121x_uart_timeout_convert_to_register/ch9121x_uart_timeout_convert_to_data test.\n");
1539
1540 /* random ms */
1541 ms = (rand() % 10) * 5;
1542
1543 /* uart timeout convert to register */
1544 res = ch9121x_uart_timeout_convert_to_register(&gs_handle, ms, &reg);
1545 if (res != 0)
1546 {
1547 ch9121x_interface_debug_print("ch9121x: uart timeout convert to register failed.\n");
1548 (void)ch9121x_deinit(&gs_handle);
1549
1550 return 1;
1551 }
1552
1553 /* output */
1554 ch9121x_interface_debug_print("ch9121x: uart timeout convert to register %d.\n", ms);
1555
1556 /* uart timeout convert to data */
1557 res = ch9121x_uart_timeout_convert_to_data(&gs_handle, reg, &ms_check);
1558 if (res != 0)
1559 {
1560 ch9121x_interface_debug_print("ch9121x: uart timeout convert to data failed.\n");
1561 (void)ch9121x_deinit(&gs_handle);
1562
1563 return 1;
1564 }
1565
1566 /* output */
1567 ch9121x_interface_debug_print("ch9121x: check uart timeout convert %s.\n", ms == ms_check ? "ok" : "error");
1568
1569 /* ch9121x_tcp_retry_time_convert_to_register/ch9121x_tcp_retry_time_convert_to_data test */
1570 ch9121x_interface_debug_print("ch9121x: ch9121x_tcp_retry_time_convert_to_register/ch9121x_tcp_retry_time_convert_to_data test.\n");
1571
1572 ms = (rand() % 7) * 500;
1573 res = ch9121x_tcp_retry_time_convert_to_register(&gs_handle, ms, &reg);
1574 if (res != 0)
1575 {
1576 ch9121x_interface_debug_print("ch9121x: tcp retry time convert to register failed.\n");
1577 (void)ch9121x_deinit(&gs_handle);
1578
1579 return 1;
1580 }
1581
1582 /* output */
1583 ch9121x_interface_debug_print("ch9121x: tcp retry time convert to register %d.\n", ms);
1584
1585 res = ch9121x_tcp_retry_time_convert_to_data(&gs_handle, reg, &ms_check);
1586 if (res != 0)
1587 {
1588 ch9121x_interface_debug_print("ch9121x: tcp retry time convert to data failed.\n");
1589 (void)ch9121x_deinit(&gs_handle);
1590
1591 return 1;
1592 }
1593
1594 /* output */
1595 ch9121x_interface_debug_print("ch9121x: check tcp retry time convert %s.\n", ms == ms_check ? "ok" : "error");
1596
1597 /* ch9121x_arp_retry_period_convert_to_register/ch9121x_arp_retry_period_convert_to_data test */
1598 ch9121x_interface_debug_print("ch9121x: ch9121x_arp_retry_period_convert_to_register/ch9121x_arp_retry_period_convert_to_data test.\n");
1599
1600 ms = (rand() % 7) * 100;
1601 res = ch9121x_arp_retry_period_convert_to_register(&gs_handle, ms, &reg);
1602 if (res != 0)
1603 {
1604 ch9121x_interface_debug_print("ch9121x: arp retry period convert to register failed.\n");
1605 (void)ch9121x_deinit(&gs_handle);
1606
1607 return 1;
1608 }
1609
1610 /* output */
1611 ch9121x_interface_debug_print("ch9121x: arp retry period convert to register %d.\n", ms);
1612
1613 res = ch9121x_arp_retry_period_convert_to_data(&gs_handle, reg, &ms_check);
1614 if (res != 0)
1615 {
1616 ch9121x_interface_debug_print("ch9121x: arp retry period convert to data failed.\n");
1617 (void)ch9121x_deinit(&gs_handle);
1618
1619 return 1;
1620 }
1621
1622 /* output */
1623 ch9121x_interface_debug_print("ch9121x: check arp retry period convert %s.\n", ms == ms_check ? "ok" : "error");
1624
1625 /* finish register test */
1626 ch9121x_interface_debug_print("ch9121x: finish register test.\n");
1627 (void)ch9121x_deinit(&gs_handle);
1628
1629 return 0;
1630}
driver_ch9121x_register_test.h
driver ch9121x register test header file
ch9121x_set_dest_port
uint8_t ch9121x_set_dest_port(ch9121x_handle_t *handle, ch9121x_port_t port, uint16_t num)
set dest port
Definition driver_ch9121x.c:1086
ch9121x_set_uart_baud
uint8_t ch9121x_set_uart_baud(ch9121x_handle_t *handle, ch9121x_port_t port, uint32_t baud)
set uart baud
Definition driver_ch9121x.c:1174
ch9121x_set_dest_ip
uint8_t ch9121x_set_dest_ip(ch9121x_handle_t *handle, ch9121x_port_t port, uint8_t ip[4])
set dest ip
Definition driver_ch9121x.c:998
ch9121x_get_mode
uint8_t ch9121x_get_mode(ch9121x_handle_t *handle, ch9121x_port_t port, ch9121x_mode_t *mode)
get mode
Definition driver_ch9121x.c:650
ch9121x_get_dhcp
uint8_t ch9121x_get_dhcp(ch9121x_handle_t *handle, ch9121x_bool_t *enable)
get dhcp status
Definition driver_ch9121x.c:2188
ch9121x_get_eth_cfg
uint8_t ch9121x_get_eth_cfg(ch9121x_handle_t *handle, ch9121x_bool_t *enable)
get eth cfg
Definition driver_ch9121x.c:1853
ch9121x_get_dest_port
uint8_t ch9121x_get_dest_port(ch9121x_handle_t *handle, ch9121x_port_t port, uint16_t *num)
get dest port
Definition driver_ch9121x.c:1130
ch9121x_info_t
struct ch9121x_info_s ch9121x_info_t
ch9121x information structure definition
ch9121x_get_flow_control
uint8_t ch9121x_get_flow_control(ch9121x_handle_t *handle, ch9121x_bool_t *enable)
get flow control status
Definition driver_ch9121x.c:2340
ch9121x_get_uart_baud
uint8_t ch9121x_get_uart_baud(ch9121x_handle_t *handle, ch9121x_port_t port, uint32_t *baud)
get uart baud
Definition driver_ch9121x.c:1220
ch9121x_set_uart_flush
uint8_t ch9121x_set_uart_flush(ch9121x_handle_t *handle, ch9121x_port_t port, ch9121x_bool_t enable)
enable or disable uart auto flush
Definition driver_ch9121x.c:1591
ch9121x_get_version
uint8_t ch9121x_get_version(ch9121x_handle_t *handle, uint8_t *version)
get version
Definition driver_ch9121x.c:325
ch9121x_get_source_port_random
uint8_t ch9121x_get_source_port_random(ch9121x_handle_t *handle, ch9121x_port_t port, ch9121x_bool_t *enable)
get random source port number status
Definition driver_ch9121x.c:1961
ch9121x_clear_mac
uint8_t ch9121x_clear_mac(ch9121x_handle_t *handle)
clear mac address
Definition driver_ch9121x.c:1784
ch9121x_set_uart_clock_mode
uint8_t ch9121x_set_uart_clock_mode(ch9121x_handle_t *handle, ch9121x_uart_clock_mode_t mode)
set uart clock mode
Definition driver_ch9121x.c:1889
ch9121x_get_uart_config
uint8_t ch9121x_get_uart_config(ch9121x_handle_t *handle, ch9121x_port_t port, uint8_t *data_bit, ch9121x_parity_t *parity, uint8_t *stop_bit)
get uart config
Definition driver_ch9121x.c:1314
ch9121x_set_uart_timeout
uint8_t ch9121x_set_uart_timeout(ch9121x_handle_t *handle, ch9121x_port_t port, uint8_t timeout)
set uart timeout
Definition driver_ch9121x.c:1360
ch9121x_get_dest_ip
uint8_t ch9121x_get_dest_ip(ch9121x_handle_t *handle, ch9121x_port_t port, uint8_t ip[4])
get dest ip
Definition driver_ch9121x.c:1044
ch9121x_get_ip
uint8_t ch9121x_get_ip(ch9121x_handle_t *handle, uint8_t ip[4])
get ip address
Definition driver_ch9121x.c:731
ch9121x_get_uart_buffer_length
uint8_t ch9121x_get_uart_buffer_length(ch9121x_handle_t *handle, ch9121x_port_t port, uint32_t *len)
get uart buffer length
Definition driver_ch9121x.c:2100
ch9121x_phy_status_t
ch9121x_phy_status_t
ch9121x phy status enumeration definition
Definition driver_ch9121x.h:106
ch9121x_get_source_port
uint8_t ch9121x_get_source_port(ch9121x_handle_t *handle, ch9121x_port_t port, uint16_t *num)
get source port
Definition driver_ch9121x.c:954
ch9121x_set_mode
uint8_t ch9121x_set_mode(ch9121x_handle_t *handle, ch9121x_port_t port, ch9121x_mode_t mode)
set mode
Definition driver_ch9121x.c:607
ch9121x_mode_t
ch9121x_mode_t
ch9121x mode enumeration definition
Definition driver_ch9121x.h:119
ch9121x_set_subnet_mask
uint8_t ch9121x_set_subnet_mask(ch9121x_handle_t *handle, uint8_t mask[4])
set subnet mask
Definition driver_ch9121x.c:765
ch9121x_uart_timeout_convert_to_register
uint8_t ch9121x_uart_timeout_convert_to_register(ch9121x_handle_t *handle, uint16_t ms, uint8_t *reg)
convert the uart timeout to the register raw data
Definition driver_ch9121x.c:1447
ch9121x_set_port2
uint8_t ch9121x_set_port2(ch9121x_handle_t *handle, ch9121x_bool_t enable)
enable or disable uart port2
Definition driver_ch9121x.c:1633
ch9121x_get_uart_flush
uint8_t ch9121x_get_uart_flush(ch9121x_handle_t *handle, ch9121x_port_t port, ch9121x_bool_t *enable)
get uart auto flush status
Definition driver_ch9121x.c:2145
ch9121x_info
uint8_t ch9121x_info(ch9121x_info_t *info)
get chip's information
Definition driver_ch9121x.c:2833
ch9121x_arp_retry_period_convert_to_register
uint8_t ch9121x_arp_retry_period_convert_to_register(ch9121x_handle_t *handle, uint16_t ms, uint8_t *reg)
convert the arp retry period to the register raw data
Definition driver_ch9121x.c:2469
ch9121x_get_mac
uint8_t ch9121x_get_mac(ch9121x_handle_t *handle, uint8_t mac[6])
get chip mac
Definition driver_ch9121x.c:528
ch9121x_set_source_port
uint8_t ch9121x_set_source_port(ch9121x_handle_t *handle, ch9121x_port_t port, uint16_t num)
set source port
Definition driver_ch9121x.c:910
ch9121x_set_tcp_retry_mode
uint8_t ch9121x_set_tcp_retry_mode(ch9121x_handle_t *handle, uint8_t t)
set tcp retry mode
Definition driver_ch9121x.c:2225
ch9121x_exit
uint8_t ch9121x_exit(ch9121x_handle_t *handle)
exit
Definition driver_ch9121x.c:459
ch9121x_uart_clock_mode_t
ch9121x_uart_clock_mode_t
ch9121x uart clock mode enumeration definition
Definition driver_ch9121x.h:97
ch9121x_deinit
uint8_t ch9121x_deinit(ch9121x_handle_t *handle)
close the chip
Definition driver_ch9121x.c:2667
ch9121x_set_dhcp
uint8_t ch9121x_set_dhcp(ch9121x_handle_t *handle, ch9121x_bool_t enable)
enable or disable dhcp
Definition driver_ch9121x.c:493
ch9121x_arp_retry_period_convert_to_data
uint8_t ch9121x_arp_retry_period_convert_to_data(ch9121x_handle_t *handle, uint8_t reg, uint16_t *ms)
convert the register raw data to the arp retry period
Definition driver_ch9121x.c:2496
ch9121x_set_eth_cfg
uint8_t ch9121x_set_eth_cfg(ch9121x_handle_t *handle, ch9121x_bool_t enable)
set eth cfg
Definition driver_ch9121x.c:1818
ch9121x_get_phy_status
uint8_t ch9121x_get_phy_status(ch9121x_handle_t *handle, ch9121x_phy_status_t *status)
get phy status
Definition driver_ch9121x.c:2004
ch9121x_uart_timeout_convert_to_data
uint8_t ch9121x_uart_timeout_convert_to_data(ch9121x_handle_t *handle, uint8_t reg, uint16_t *ms)
convert the register raw data to the offset
Definition driver_ch9121x.c:1474
ch9121x_set_disconnect_with_no_rj45
uint8_t ch9121x_set_disconnect_with_no_rj45(ch9121x_handle_t *handle, ch9121x_bool_t enable)
enable or disable disconnect with no rj45
Definition driver_ch9121x.c:1668
ch9121x_set_ip
uint8_t ch9121x_set_ip(ch9121x_handle_t *handle, uint8_t ip[4])
set ip address
Definition driver_ch9121x.c:693
ch9121x_bool_t
ch9121x_bool_t
ch9121x bool enumeration definition
Definition driver_ch9121x.h:79
ch9121x_tcp_retry_time_convert_to_register
uint8_t ch9121x_tcp_retry_time_convert_to_register(ch9121x_handle_t *handle, uint16_t ms, uint8_t *reg)
convert the tcp retry time to the register raw data
Definition driver_ch9121x.c:2415
ch9121x_tcp_retry_time_convert_to_data
uint8_t ch9121x_tcp_retry_time_convert_to_data(ch9121x_handle_t *handle, uint8_t reg, uint16_t *ms)
convert the register raw data to the tcp retry time
Definition driver_ch9121x.c:2442
ch9121x_set_gateway
uint8_t ch9121x_set_gateway(ch9121x_handle_t *handle, uint8_t ip[4])
set gateway
Definition driver_ch9121x.c:837
ch9121x_status_t
ch9121x_status_t
ch9121x status enumeration definition
Definition driver_ch9121x.h:88
ch9121x_parity_t
ch9121x_parity_t
ch9121x parity enumeration definition
Definition driver_ch9121x.h:130
ch9121x_get_status
uint8_t ch9121x_get_status(ch9121x_handle_t *handle, ch9121x_port_t port, ch9121x_status_t *status)
get status
Definition driver_ch9121x.c:563
ch9121x_set_mac
uint8_t ch9121x_set_mac(ch9121x_handle_t *handle, uint8_t mac[6])
set mac address
Definition driver_ch9121x.c:1745
ch9121x_set_domain
uint8_t ch9121x_set_domain(ch9121x_handle_t *handle, char *domain)
set chip domain
Definition driver_ch9121x.c:1703
ch9121x_set_flow_control
uint8_t ch9121x_set_flow_control(ch9121x_handle_t *handle, ch9121x_bool_t enable)
enable or disable flow control
Definition driver_ch9121x.c:2304
ch9121x_get_uart_timeout
uint8_t ch9121x_get_uart_timeout(ch9121x_handle_t *handle, ch9121x_port_t port, uint8_t *timeout)
get uart timeout
Definition driver_ch9121x.c:1406
ch9121x_get_gateway
uint8_t ch9121x_get_gateway(ch9121x_handle_t *handle, uint8_t ip[4])
get gateway
Definition driver_ch9121x.c:875
ch9121x_get_subnet_mask
uint8_t ch9121x_get_subnet_mask(ch9121x_handle_t *handle, uint8_t mask[4])
get subnet mask
Definition driver_ch9121x.c:803
ch9121x_get_disconnect_with_no_rj45
uint8_t ch9121x_get_disconnect_with_no_rj45(ch9121x_handle_t *handle, ch9121x_bool_t *enable)
get disconnect with no rj45 status
Definition driver_ch9121x.c:2063
ch9121x_save_to_eeprom
uint8_t ch9121x_save_to_eeprom(ch9121x_handle_t *handle)
save to eeprom
Definition driver_ch9121x.c:392
ch9121x_init
uint8_t ch9121x_init(ch9121x_handle_t *handle)
initialize the chip
Definition driver_ch9121x.c:2525
ch9121x_get_tcp_retry_mode
uint8_t ch9121x_get_tcp_retry_mode(ch9121x_handle_t *handle, uint8_t *t)
get tcp retry mode
Definition driver_ch9121x.c:2267
ch9121x_set_arp_retry
uint8_t ch9121x_set_arp_retry(ch9121x_handle_t *handle, uint8_t period, uint8_t times)
set arp retry
Definition driver_ch9121x.c:2378
ch9121x_handle_t
struct ch9121x_handle_s ch9121x_handle_t
ch9121x handle structure definition
ch9121x_set_source_port_random
uint8_t ch9121x_set_source_port_random(ch9121x_handle_t *handle, ch9121x_port_t port, ch9121x_bool_t enable)
enable or disable random source port number
Definition driver_ch9121x.c:1502
ch9121x_get_uart_clock_mode
uint8_t ch9121x_get_uart_clock_mode(ch9121x_handle_t *handle, ch9121x_uart_clock_mode_t *mode)
get uart clock mode
Definition driver_ch9121x.c:1924
ch9121x_set_uart_buffer_length
uint8_t ch9121x_set_uart_buffer_length(ch9121x_handle_t *handle, ch9121x_port_t port, uint32_t len)
set uart buffer length
Definition driver_ch9121x.c:1545
ch9121x_set_uart_config
uint8_t ch9121x_set_uart_config(ch9121x_handle_t *handle, ch9121x_port_t port, uint8_t data_bit, ch9121x_parity_t parity, uint8_t stop_bit)
set uart config
Definition driver_ch9121x.c:1267
CH9121X_PORT1
@ CH9121X_PORT1
Definition driver_ch9121x.h:71
CH9121X_PORT2
@ CH9121X_PORT2
Definition driver_ch9121x.h:72
CH9121X_PHY_STATUS_100M_FULL_DUPLEX
@ CH9121X_PHY_STATUS_100M_FULL_DUPLEX
Definition driver_ch9121x.h:111
CH9121X_PHY_STATUS_10M_HALF_DUPLEX
@ CH9121X_PHY_STATUS_10M_HALF_DUPLEX
Definition driver_ch9121x.h:110
CH9121X_PHY_STATUS_DISCONNECTED
@ CH9121X_PHY_STATUS_DISCONNECTED
Definition driver_ch9121x.h:108
CH9121X_PHY_STATUS_10M_FULL_DUPLEX
@ CH9121X_PHY_STATUS_10M_FULL_DUPLEX
Definition driver_ch9121x.h:109
CH9121X_PHY_STATUS_100M_HALF_DUPLEX
@ CH9121X_PHY_STATUS_100M_HALF_DUPLEX
Definition driver_ch9121x.h:112
CH9121X_MODE_TCP_CLIENT
@ CH9121X_MODE_TCP_CLIENT
Definition driver_ch9121x.h:121
CH9121X_MODE_UDP_CLIENT
@ CH9121X_MODE_UDP_CLIENT
Definition driver_ch9121x.h:123
CH9121X_MODE_TCP_SERVER
@ CH9121X_MODE_TCP_SERVER
Definition driver_ch9121x.h:120
CH9121X_MODE_UDP_SERVER
@ CH9121X_MODE_UDP_SERVER
Definition driver_ch9121x.h:122
CH9121X_UART_CLOCK_MODE_DEFAULT
@ CH9121X_UART_CLOCK_MODE_DEFAULT
Definition driver_ch9121x.h:98
CH9121X_UART_CLOCK_MODE_CLASSICAL
@ CH9121X_UART_CLOCK_MODE_CLASSICAL
Definition driver_ch9121x.h:99
CH9121X_BOOL_FALSE
@ CH9121X_BOOL_FALSE
Definition driver_ch9121x.h:80
CH9121X_BOOL_TRUE
@ CH9121X_BOOL_TRUE
Definition driver_ch9121x.h:81
CH9121X_STATUS_CONNECT
@ CH9121X_STATUS_CONNECT
Definition driver_ch9121x.h:90
CH9121X_PARITY_NONE
@ CH9121X_PARITY_NONE
Definition driver_ch9121x.h:135
ch9121x_interface_cfg_gpio_deinit
uint8_t ch9121x_interface_cfg_gpio_deinit(void)
interface cfg gpio deinit
Definition driver_ch9121x_interface_template.c:159
ch9121x_interface_cfg_gpio_init
uint8_t ch9121x_interface_cfg_gpio_init(void)
interface cfg gpio init
Definition driver_ch9121x_interface_template.c:147
ch9121x_interface_debug_print
void ch9121x_interface_debug_print(const char *const fmt,...)
interface print format data
Definition driver_ch9121x_interface_template.c:192
ch9121x_interface_uart_write
uint8_t ch9121x_interface_uart_write(uint8_t *buf, uint16_t len)
interface uart write
Definition driver_ch9121x_interface_template.c:98
ch9121x_interface_uart_flush
uint8_t ch9121x_interface_uart_flush(void)
interface uart flush
Definition driver_ch9121x_interface_template.c:84
ch9121x_interface_uart_read
uint16_t ch9121x_interface_uart_read(uint8_t *buf, uint16_t len)
interface uart read
Definition driver_ch9121x_interface_template.c:72
ch9121x_interface_reset_gpio_deinit
uint8_t ch9121x_interface_reset_gpio_deinit(void)
interface reset gpio deinit
Definition driver_ch9121x_interface_template.c:122
ch9121x_interface_reset_gpio_write
uint8_t ch9121x_interface_reset_gpio_write(uint8_t data)
interface reset gpio write
Definition driver_ch9121x_interface_template.c:135
ch9121x_interface_delay_ms
void ch9121x_interface_delay_ms(uint32_t ms)
interface delay ms
Definition driver_ch9121x_interface_template.c:182
ch9121x_interface_cfg_gpio_write
uint8_t ch9121x_interface_cfg_gpio_write(uint8_t data)
interface cfg gpio write
Definition driver_ch9121x_interface_template.c:172
ch9121x_interface_uart_deinit
uint8_t ch9121x_interface_uart_deinit(void)
interface uart deinit
Definition driver_ch9121x_interface_template.c:58
ch9121x_interface_reset_gpio_init
uint8_t ch9121x_interface_reset_gpio_init(void)
interface reset gpio init
Definition driver_ch9121x_interface_template.c:110
ch9121x_interface_uart_init
uint8_t ch9121x_interface_uart_init(void)
interface uart init
Definition driver_ch9121x_interface_template.c:46
DRIVER_CH9121X_LINK_UART_FLUSH
#define DRIVER_CH9121X_LINK_UART_FLUSH(HANDLE, FUC)
link uart_flush function
Definition driver_ch9121x.h:233
DRIVER_CH9121X_LINK_DEBUG_PRINT
#define DRIVER_CH9121X_LINK_DEBUG_PRINT(HANDLE, FUC)
link debug_print function
Definition driver_ch9121x.h:297
DRIVER_CH9121X_LINK_CFG_GPIO_INIT
#define DRIVER_CH9121X_LINK_CFG_GPIO_INIT(HANDLE, FUC)
link cfg_gpio_init function
Definition driver_ch9121x.h:265
DRIVER_CH9121X_LINK_DELAY_MS
#define DRIVER_CH9121X_LINK_DELAY_MS(HANDLE, FUC)
link delay_ms function
Definition driver_ch9121x.h:289
DRIVER_CH9121X_LINK_UART_DEINIT
#define DRIVER_CH9121X_LINK_UART_DEINIT(HANDLE, FUC)
link uart_deinit function
Definition driver_ch9121x.h:209
DRIVER_CH9121X_LINK_UART_INIT
#define DRIVER_CH9121X_LINK_UART_INIT(HANDLE, FUC)
link uart_init function
Definition driver_ch9121x.h:201
DRIVER_CH9121X_LINK_CFG_GPIO_DEINIT
#define DRIVER_CH9121X_LINK_CFG_GPIO_DEINIT(HANDLE, FUC)
link cfg_gpio_deinit function
Definition driver_ch9121x.h:273
DRIVER_CH9121X_LINK_RESET_GPIO_INIT
#define DRIVER_CH9121X_LINK_RESET_GPIO_INIT(HANDLE, FUC)
link reset_gpio_init function
Definition driver_ch9121x.h:241
DRIVER_CH9121X_LINK_UART_WRITE
#define DRIVER_CH9121X_LINK_UART_WRITE(HANDLE, FUC)
link uart_write function
Definition driver_ch9121x.h:225
DRIVER_CH9121X_LINK_RESET_GPIO_WRITE
#define DRIVER_CH9121X_LINK_RESET_GPIO_WRITE(HANDLE, FUC)
link reset_gpio_write function
Definition driver_ch9121x.h:257
DRIVER_CH9121X_LINK_INIT
#define DRIVER_CH9121X_LINK_INIT(HANDLE, STRUCTURE)
initialize ch9121x structure
Definition driver_ch9121x.h:193
DRIVER_CH9121X_LINK_RESET_GPIO_DEINIT
#define DRIVER_CH9121X_LINK_RESET_GPIO_DEINIT(HANDLE, FUC)
link reset_gpio_deinit function
Definition driver_ch9121x.h:249
DRIVER_CH9121X_LINK_CFG_GPIO_WRITE
#define DRIVER_CH9121X_LINK_CFG_GPIO_WRITE(HANDLE, FUC)
link cfg_gpio_write function
Definition driver_ch9121x.h:281
DRIVER_CH9121X_LINK_UART_READ
#define DRIVER_CH9121X_LINK_UART_READ(HANDLE, FUC)
link uart_read function
Definition driver_ch9121x.h:217
ch9121x_register_test
uint8_t ch9121x_register_test(void)
register test
Definition driver_ch9121x_register_test.c:49
ch9121x_info_s::temperature_max
float temperature_max
Definition driver_ch9121x.h:172
ch9121x_info_s::supply_voltage_max_v
float supply_voltage_max_v
Definition driver_ch9121x.h:169
ch9121x_info_s::driver_version
uint32_t driver_version
Definition driver_ch9121x.h:173
ch9121x_info_s::temperature_min
float temperature_min
Definition driver_ch9121x.h:171
ch9121x_info_s::max_current_ma
float max_current_ma
Definition driver_ch9121x.h:170
ch9121x_info_s::manufacturer_name
char manufacturer_name[32]
Definition driver_ch9121x.h:166
ch9121x_info_s::supply_voltage_min_v
float supply_voltage_min_v
Definition driver_ch9121x.h:168
ch9121x_info_s::interface
char interface[8]
Definition driver_ch9121x.h:167
ch9121x_info_s::chip_name
char chip_name[32]
Definition driver_ch9121x.h:165