LibDriver W25QXX  1.0.0
W25QXX full-featured driver
driver_w25qxx_read_test.c
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1 
37 #include "driver_w25qxx_read_test.h"
38 #include <stdlib.h>
39 
40 static w25qxx_handle_t gs_handle;
41 static uint8_t gs_buffer_input[600];
42 static uint8_t gs_buffer_output[600];
43 static const uint32_t gsc_size[] = {0x100000, 0x200000, 0x400000, 0x800000, 0x1000000, 0x2000000};
55 uint8_t w25qxx_read_test(w25qxx_type_t type, w25qxx_interface_t interface, w25qxx_bool_t dual_quad_spi_enable)
56 {
57  uint8_t res;
58  w25qxx_info_t info;
59 
60  /* link interface function */
61  DRIVER_W25QXX_LINK_INIT(&gs_handle, w25qxx_handle_t);
62  DRIVER_W25QXX_LINK_SPI_QSPI_INIT(&gs_handle, w25qxx_interface_spi_qspi_init);
63  DRIVER_W25QXX_LINK_SPI_QSPI_DEINIT(&gs_handle, w25qxx_interface_spi_qspi_deinit);
64  DRIVER_W25QXX_LINK_SPI_QSPI_WRITE_READ(&gs_handle, w25qxx_interface_spi_qspi_write_read);
65  DRIVER_W25QXX_LINK_DELAY_MS(&gs_handle, w25qxx_interface_delay_ms);
66  DRIVER_W25QXX_LINK_DELAY_US(&gs_handle, w25qxx_interface_delay_us);
67  DRIVER_W25QXX_LINK_DEBUG_PRINT(&gs_handle, w25qxx_interface_debug_print);
68 
69  /* get information */
70  res = w25qxx_info(&info);
71  if (res != 0)
72  {
73  w25qxx_interface_debug_print("w25qxx: get info failed.\n");
74 
75  return 1;
76  }
77  else
78  {
79  /* print chip information */
80  w25qxx_interface_debug_print("w25qxx: chip is %s.\n", info.chip_name);
81  w25qxx_interface_debug_print("w25qxx: manufacturer is %s.\n", info.manufacturer_name);
82  w25qxx_interface_debug_print("w25qxx: interface is %s.\n", info.interface);
83  w25qxx_interface_debug_print("w25qxx: driver version is %d.%d.\n", info.driver_version / 1000, (info.driver_version % 1000) / 100);
84  w25qxx_interface_debug_print("w25qxx: min supply voltage is %0.1fV.\n", info.supply_voltage_min_v);
85  w25qxx_interface_debug_print("w25qxx: max supply voltage is %0.1fV.\n", info.supply_voltage_max_v);
86  w25qxx_interface_debug_print("w25qxx: max current is %0.2fmA.\n", info.max_current_ma);
87  w25qxx_interface_debug_print("w25qxx: max temperature is %0.1fC.\n", info.temperature_max);
88  w25qxx_interface_debug_print("w25qxx: min temperature is %0.1fC.\n", info.temperature_min);
89  }
90 
91  /* set chip type */
92  res = w25qxx_set_type(&gs_handle, type);
93  if (res != 0)
94  {
95  w25qxx_interface_debug_print("w25qxx: set type failed.\n");
96 
97  return 1;
98  }
99 
100  /* set chip interface */
101  res = w25qxx_set_interface(&gs_handle, interface);
102  if (res != 0)
103  {
104  w25qxx_interface_debug_print("w25qxx: set interface failed.\n");
105 
106  return 1;
107  }
108 
109  /* set dual quad spi */
110  res = w25qxx_set_dual_quad_spi(&gs_handle, dual_quad_spi_enable);
111  if (res != 0)
112  {
113  w25qxx_interface_debug_print("w25qxx: set dual quad spi failed.\n");
114  (void)w25qxx_deinit(&gs_handle);
115 
116  return 1;
117  }
118 
119  /* chip init */
120  res = w25qxx_init(&gs_handle);
121  if (res != 0)
122  {
123  w25qxx_interface_debug_print("w25qxx: init failed.\n");
124 
125  return 1;
126  }
127 
128  /* start read test */
129  w25qxx_interface_debug_print("w25qxx: start read test.\n");
130 
131  if (interface == W25QXX_INTERFACE_SPI)
132  {
133  uint32_t size;
134  uint32_t addr, step, j;
135 
136  size = gsc_size[type - W25Q80];
137  step = size / 16;
138 
139  /* w25qxx_write/w25qxx_read test */
140  w25qxx_interface_debug_print("w25qxx: w25qxx_write/w25qxx_read test.\n");
141 
142  for (addr = 0; addr < size; addr += step)
143  {
144  for (j = 0; j < 600; j++)
145  {
146  gs_buffer_input[j] = rand() %256;
147  }
148  res = w25qxx_write(&gs_handle, addr, gs_buffer_input, 600);
149  if (res != 0)
150  {
151  w25qxx_interface_debug_print("w25qxx: write failed.\n");
152  (void)w25qxx_deinit(&gs_handle);
153 
154  return 1;
155  }
156  res = w25qxx_read(&gs_handle, addr, gs_buffer_output, 600);
157  if (res != 0)
158  {
159  w25qxx_interface_debug_print("w25qxx: read failed.\n");
160  (void)w25qxx_deinit(&gs_handle);
161 
162  return 1;
163  }
164  for (j = 0; j < 600; j++)
165  {
166  if (gs_buffer_input[j] != gs_buffer_output[j])
167  {
168  w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
169  (void)w25qxx_deinit(&gs_handle);
170 
171  return 1;
172  }
173  }
174  w25qxx_interface_debug_print("w25qxx: 0x%08X/0x%08X successful.\n", addr, size);
175  }
176 
177  /* w25qxx_sector_erase_4k test */
178  addr = (rand() % 10) * 4 * 1024;
179  w25qxx_interface_debug_print("w25qxx: w25qxx_sector_erase_4k test with address 0x%X.\n", addr);
180  res = w25qxx_sector_erase_4k(&gs_handle, addr);
181  if (res != 0)
182  {
183  w25qxx_interface_debug_print("w25qxx: sector erase 4k failed.\n");
184  (void)w25qxx_deinit(&gs_handle);
185 
186  return 1;
187  }
188  for (j = 0; j < 256; j++)
189  {
190  gs_buffer_input[j] = rand() %256;
191  }
192 
193  /* w25qxx_page_program */
194  res = w25qxx_page_program(&gs_handle, addr, gs_buffer_input, 256);
195  if (res != 0)
196  {
197  w25qxx_interface_debug_print("w25qxx: page program failed.\n");
198  (void)w25qxx_deinit(&gs_handle);
199 
200  return 1;
201  }
202 
203  /* w25qxx_only_spi_read */
204  res = w25qxx_only_spi_read(&gs_handle, addr, gs_buffer_output, 256);
205  if (res != 0)
206  {
207  w25qxx_interface_debug_print("w25qxx: only spi read failed.\n");
208  (void)w25qxx_deinit(&gs_handle);
209 
210  return 1;
211  }
212  for (j = 0; j < 256; j++)
213  {
214  if (gs_buffer_input[j] != gs_buffer_output[j])
215  {
216  w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
217  (void)w25qxx_deinit(&gs_handle);
218 
219  return 1;
220  }
221  }
222  w25qxx_interface_debug_print("w25qxx: only spi read test passed.\n");
223 
224  /* w25qxx_fast_read */
225  res = w25qxx_fast_read(&gs_handle, addr, gs_buffer_output, 256);
226  if (res != 0)
227  {
228  w25qxx_interface_debug_print("w25qxx: fast read failed.\n");
229  (void)w25qxx_deinit(&gs_handle);
230 
231  return 1;
232  }
233  for (j = 0; j < 256; j++)
234  {
235  if (gs_buffer_input[j] != gs_buffer_output[j])
236  {
237  w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
238  (void)w25qxx_deinit(&gs_handle);
239 
240  return 1;
241  }
242  }
243  w25qxx_interface_debug_print("w25qxx: fast read test passed.\n");
244 
245  /* w25qxx_block_erase_32k test */
246  addr = (rand() % 10) * 32 * 1024;
247  w25qxx_interface_debug_print("w25qxx: w25qxx_block_erase_32k test with address 0x%X.\n", addr);
248  res = w25qxx_block_erase_32k(&gs_handle, addr);
249  if (res != 0)
250  {
251  w25qxx_interface_debug_print("w25qxx: sector erase 32k failed.\n");
252  (void)w25qxx_deinit(&gs_handle);
253 
254  return 1;
255  }
256  for (j = 0; j < 256; j++)
257  {
258  gs_buffer_input[j] = rand() %256;
259  }
260 
261  /* w25qxx_page_program */
262  res = w25qxx_page_program(&gs_handle, addr, gs_buffer_input, 256);
263  if (res != 0)
264  {
265  w25qxx_interface_debug_print("w25qxx: page program failed.\n");
266  (void)w25qxx_deinit(&gs_handle);
267 
268  return 1;
269  }
270 
271  /* w25qxx_only_spi_read */
272  res = w25qxx_only_spi_read(&gs_handle, addr, gs_buffer_output, 256);
273  if (res != 0)
274  {
275  w25qxx_interface_debug_print("w25qxx: only spi read failed.\n");
276  (void)w25qxx_deinit(&gs_handle);
277 
278  return 1;
279  }
280  for (j = 0; j < 256; j++)
281  {
282  if (gs_buffer_input[j] != gs_buffer_output[j])
283  {
284  w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
285  (void)w25qxx_deinit(&gs_handle);
286 
287  return 1;
288  }
289  }
290  w25qxx_interface_debug_print("w25qxx: only spi read test passed.\n");
291 
292  /* w25qxx_fast_read */
293  res = w25qxx_fast_read(&gs_handle, addr, gs_buffer_output, 256);
294  if (res != 0)
295  {
296  w25qxx_interface_debug_print("w25qxx: fast read failed.\n");
297  (void)w25qxx_deinit(&gs_handle);
298 
299  return 1;
300  }
301  for (j = 0; j < 256; j++)
302  {
303  if (gs_buffer_input[j] != gs_buffer_output[j])
304  {
305  w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
306  (void)w25qxx_deinit(&gs_handle);
307 
308  return 1;
309  }
310  }
311  w25qxx_interface_debug_print("w25qxx: fast read test passed.\n");
312 
313  /* w25qxx_block_erase_64k test */
314  addr = (rand() % 10) * 64 * 1024;
315  w25qxx_interface_debug_print("w25qxx: w25qxx_block_erase_64k test with address 0x%X.\n", addr);
316  res = w25qxx_block_erase_64k(&gs_handle, addr);
317  if (res != 0)
318  {
319  w25qxx_interface_debug_print("w25qxx: sector erase 64k failed.\n");
320  (void)w25qxx_deinit(&gs_handle);
321 
322  return 1;
323  }
324  for (j = 0; j < 256; j++)
325  {
326  gs_buffer_input[j] = rand() %256;
327  }
328 
329  /* w25qxx_page_program */
330  res = w25qxx_page_program(&gs_handle, addr, gs_buffer_input, 256);
331  if (res != 0)
332  {
333  w25qxx_interface_debug_print("w25qxx: page program failed.\n");
334  (void)w25qxx_deinit(&gs_handle);
335 
336  return 1;
337  }
338 
339  /* w25qxx_only_spi_read */
340  res = w25qxx_only_spi_read(&gs_handle, addr, gs_buffer_output, 256);
341  if (res != 0)
342  {
343  w25qxx_interface_debug_print("w25qxx: only spi read failed.\n");
344  (void)w25qxx_deinit(&gs_handle);
345 
346  return 1;
347  }
348  for (j = 0; j < 256; j++)
349  {
350  if (gs_buffer_input[j] != gs_buffer_output[j])
351  {
352  w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
353  (void)w25qxx_deinit(&gs_handle);
354 
355  return 1;
356  }
357  }
358  w25qxx_interface_debug_print("w25qxx: only spi read test passed.\n");
359 
360  /* w25qxx_fast_read */
361  res = w25qxx_fast_read(&gs_handle, addr, gs_buffer_output, 256);
362  if (res != 0)
363  {
364  w25qxx_interface_debug_print("w25qxx: fast read failed.\n");
365  (void)w25qxx_deinit(&gs_handle);
366 
367  return 1;
368  }
369  for (j = 0; j < 256; j++)
370  {
371  if (gs_buffer_input[j] != gs_buffer_output[j])
372  {
373  w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
374  (void)w25qxx_deinit(&gs_handle);
375 
376  return 1;
377  }
378  }
379  w25qxx_interface_debug_print("w25qxx: fast read test passed.\n");
380 
381  /* get sfdp */
382  w25qxx_interface_debug_print("w25qxx: get sfdp.\n");
383  memset(gs_buffer_output, 0, sizeof(uint8_t) * 256);
384  res = w25qxx_get_sfdp(&gs_handle, (uint8_t *)gs_buffer_output);
385  if (res != 0)
386  {
387  w25qxx_interface_debug_print("w25qxx: get sfdp failed.\n");
388  (void)w25qxx_deinit(&gs_handle);
389 
390  return 1;
391  }
392  for (j = 0; j < 256; j += 8)
393  {
394  w25qxx_interface_debug_print("w25qxx: sdfp[%d-%d] is 0x%02X 0x%02X 0x%02X 0x%02X 0x%02X 0x%02X 0x%02X 0x%02X.\n",
395  j , j + 7,
396  gs_buffer_output[j + 0], gs_buffer_output[j + 1], gs_buffer_output[j + 2],
397  gs_buffer_output[j + 3], gs_buffer_output[j + 4], gs_buffer_output[j + 5],
398  gs_buffer_output[j + 6], gs_buffer_output[j + 7]);
399  }
400 
401  /* security register1 write and read test */
402  w25qxx_interface_debug_print("w25qxx: security register1 write and read test.\n");
403 
404  /* security register1 write and read test */
405  res = w25qxx_erase_security_register(&gs_handle, W25QXX_SECURITY_REGISTER_1);
406  if (res != 0)
407  {
408  w25qxx_interface_debug_print("w25qxx: erase security register failed.\n");
409  (void)w25qxx_deinit(&gs_handle);
410 
411  return 1;
412  }
413  for (j = 0; j < 256; j++)
414  {
415  gs_buffer_input[j] = rand() %256;
416  }
417  res = w25qxx_program_security_register(&gs_handle, W25QXX_SECURITY_REGISTER_1, gs_buffer_input);
418  if (res != 0)
419  {
420  w25qxx_interface_debug_print("w25qxx: program security register failed.\n");
421  (void)w25qxx_deinit(&gs_handle);
422 
423  return 1;
424  }
425  res = w25qxx_read_security_register(&gs_handle, W25QXX_SECURITY_REGISTER_1, gs_buffer_output);
426  if (res != 0)
427  {
428  w25qxx_interface_debug_print("w25qxx: read security register failed.\n");
429  (void)w25qxx_deinit(&gs_handle);
430 
431  return 1;
432  }
433  for (j = 0; j < 256; j++)
434  {
435  if (gs_buffer_input[j] != gs_buffer_output[j])
436  {
437  w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
438  (void)w25qxx_deinit(&gs_handle);
439 
440  return 1;
441  }
442  }
443  w25qxx_interface_debug_print("w25qxx: security register1 check passed.\n");
444 
445  /* security register2 write and read test */
446  w25qxx_interface_debug_print("w25qxx: security register2 write and read test.\n");
447 
448  /* security register2 write and read test */
449  res = w25qxx_erase_security_register(&gs_handle, W25QXX_SECURITY_REGISTER_2);
450  if (res != 0)
451  {
452  w25qxx_interface_debug_print("w25qxx: erase security register failed.\n");
453  (void)w25qxx_deinit(&gs_handle);
454 
455  return 1;
456  }
457  for (j = 0; j < 256; j++)
458  {
459  gs_buffer_input[j] = rand() %256;
460  }
461  res = w25qxx_program_security_register(&gs_handle, W25QXX_SECURITY_REGISTER_2, gs_buffer_input);
462  if (res != 0)
463  {
464  w25qxx_interface_debug_print("w25qxx: program security register failed.\n");
465  (void)w25qxx_deinit(&gs_handle);
466 
467  return 1;
468  }
469  res = w25qxx_read_security_register(&gs_handle, W25QXX_SECURITY_REGISTER_2, gs_buffer_output);
470  if (res != 0)
471  {
472  w25qxx_interface_debug_print("w25qxx: read security register failed.\n");
473  (void)w25qxx_deinit(&gs_handle);
474 
475  return 1;
476  }
477  for (j = 0; j < 256; j++)
478  {
479  if (gs_buffer_input[j] != gs_buffer_output[j])
480  {
481  w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
482  (void)w25qxx_deinit(&gs_handle);
483 
484  return 1;
485  }
486  }
487  w25qxx_interface_debug_print("w25qxx: security register2 check passed.\n");
488 
489  /* security register3 write and read test */
490  w25qxx_interface_debug_print("w25qxx: security register3 write and read test.\n");
491 
492  /* security register3 write and read test */
493  res = w25qxx_erase_security_register(&gs_handle, W25QXX_SECURITY_REGISTER_3);
494  if (res != 0)
495  {
496  w25qxx_interface_debug_print("w25qxx: erase security register failed.\n");
497  (void)w25qxx_deinit(&gs_handle);
498 
499  return 1;
500  }
501  for (j = 0; j < 256; j++)
502  {
503  gs_buffer_input[j] = rand() %256;
504  }
505  res = w25qxx_program_security_register(&gs_handle, W25QXX_SECURITY_REGISTER_3, gs_buffer_input);
506  if (res != 0)
507  {
508  w25qxx_interface_debug_print("w25qxx: program security register failed.\n");
509  (void)w25qxx_deinit(&gs_handle);
510 
511  return 1;
512  }
513  res = w25qxx_read_security_register(&gs_handle, W25QXX_SECURITY_REGISTER_3, gs_buffer_output);
514  if (res != 0)
515  {
516  w25qxx_interface_debug_print("w25qxx: read security register failed.\n");
517  (void)w25qxx_deinit(&gs_handle);
518 
519  return 1;
520  }
521  for (j = 0; j < 256; j++)
522  {
523  if (gs_buffer_input[j] != gs_buffer_output[j])
524  {
525  w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
526  (void)w25qxx_deinit(&gs_handle);
527 
528  return 1;
529  }
530  }
531  w25qxx_interface_debug_print("w25qxx: security register3 check passed.\n");
532 
533  #if (W25QXX_ENABLE_ERASE_READ_TEST == 1)
534  /* start chip erasing */
535  w25qxx_interface_debug_print("w25qxx: start chip erasing.\n");
536 
537  /* chip erase */
538  w25qxx_interface_debug_print("w25qxx: w25qxx_chip_erase test.\n");
539  res = w25qxx_chip_erase(&gs_handle);
540  if (res != 0)
541  {
542  w25qxx_interface_debug_print("w25qxx: chip erase failed.\n");
543  (void)w25qxx_deinit(&gs_handle);
544 
545  return 1;
546  }
547  w25qxx_interface_debug_print("w25qxx: chip erase successful.\n");
548  #endif
549 
550  if (type >= W25Q256)
551  {
552  /* set address mode 4 byte */
553  w25qxx_interface_debug_print("w25qxx: set address mode 4 byte.\n");
554 
555  /* set address mode 4 byte */
556  res = w25qxx_set_address_mode(&gs_handle, W25QXX_ADDRESS_MODE_4_BYTE);
557  if (res != 0)
558  {
559  w25qxx_interface_debug_print("w25qxx: set address mode failed.\n");
560  (void)w25qxx_deinit(&gs_handle);
561 
562  return 1;
563  }
564 
565  /* w25qxx_write/w25qxx_read test */
566  w25qxx_interface_debug_print("w25qxx: w25qxx_write/w25qxx_read test.\n");
567 
568  for (addr = 0; addr < size; addr += step)
569  {
570  for (j = 0; j < 600; j++)
571  {
572  gs_buffer_input[j] = rand() %256;
573  }
574  res = w25qxx_write(&gs_handle, addr, gs_buffer_input, 600);
575  if (res != 0)
576  {
577  w25qxx_interface_debug_print("w25qxx: write failed.\n");
578  (void)w25qxx_deinit(&gs_handle);
579 
580  return 1;
581  }
582  res = w25qxx_read(&gs_handle, addr, gs_buffer_output, 600);
583  if (res != 0)
584  {
585  w25qxx_interface_debug_print("w25qxx: read failed.\n");
586  (void)w25qxx_deinit(&gs_handle);
587 
588  return 1;
589  }
590  for (j = 0; j < 600; j++)
591  {
592  if (gs_buffer_input[j] != gs_buffer_output[j])
593  {
594  w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
595  (void)w25qxx_deinit(&gs_handle);
596 
597  return 1;
598  }
599  }
600  w25qxx_interface_debug_print("w25qxx: %d/%d successful.\n", addr, size);
601  }
602 
603  /* w25qxx_sector_erase_4k test */
604  addr = (rand() % 10) * 4 * 1024;
605  w25qxx_interface_debug_print("w25qxx: w25qxx_sector_erase_4k test with address 0x%X.\n", addr);
606  res = w25qxx_sector_erase_4k(&gs_handle, addr);
607  if (res != 0)
608  {
609  w25qxx_interface_debug_print("w25qxx: sector erase 4k failed.\n");
610  (void)w25qxx_deinit(&gs_handle);
611 
612  return 1;
613  }
614  for (j = 0; j < 256; j++)
615  {
616  gs_buffer_input[j] = rand() %256;
617  }
618 
619  /* w25qxx_page_program */
620  res = w25qxx_page_program(&gs_handle, addr, gs_buffer_input, 256);
621  if (res != 0)
622  {
623  w25qxx_interface_debug_print("w25qxx: page program failed.\n");
624  (void)w25qxx_deinit(&gs_handle);
625 
626  return 1;
627  }
628 
629  /* w25qxx_only_spi_read */
630  res = w25qxx_only_spi_read(&gs_handle, addr, gs_buffer_output, 256);
631  if (res != 0)
632  {
633  w25qxx_interface_debug_print("w25qxx: only spi read failed.\n");
634  (void)w25qxx_deinit(&gs_handle);
635 
636  return 1;
637  }
638  for (j = 0; j < 256; j++)
639  {
640  if (gs_buffer_input[j] != gs_buffer_output[j])
641  {
642  w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
643  (void)w25qxx_deinit(&gs_handle);
644 
645  return 1;
646  }
647  }
648  w25qxx_interface_debug_print("w25qxx: only spi read test passed.\n");
649 
650  /* w25qxx_fast_read */
651  res = w25qxx_fast_read(&gs_handle, addr, gs_buffer_output, 256);
652  if (res != 0)
653  {
654  w25qxx_interface_debug_print("w25qxx: fast read failed.\n");
655  (void)w25qxx_deinit(&gs_handle);
656 
657  return 1;
658  }
659  for (j = 0; j < 256; j++)
660  {
661  if (gs_buffer_input[j] != gs_buffer_output[j])
662  {
663  w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
664  (void)w25qxx_deinit(&gs_handle);
665 
666  return 1;
667  }
668  }
669  w25qxx_interface_debug_print("w25qxx: fast read test passed.\n");
670 
671  /* w25qxx_block_erase_32k test */
672  addr = (rand() % 10) * 32 * 1024;
673  w25qxx_interface_debug_print("w25qxx: w25qxx_block_erase_32k test with address 0x%X.\n", addr);
674  res = w25qxx_block_erase_32k(&gs_handle, addr);
675  if (res != 0)
676  {
677  w25qxx_interface_debug_print("w25qxx: sector erase 32k failed.\n");
678  (void)w25qxx_deinit(&gs_handle);
679 
680  return 1;
681  }
682  for (j = 0; j < 256; j++)
683  {
684  gs_buffer_input[j] = rand() %256;
685  }
686 
687  /* w25qxx_page_program */
688  res = w25qxx_page_program(&gs_handle, addr, gs_buffer_input, 256);
689  if (res != 0)
690  {
691  w25qxx_interface_debug_print("w25qxx: page program failed.\n");
692  (void)w25qxx_deinit(&gs_handle);
693 
694  return 1;
695  }
696 
697  /* w25qxx_only_spi_read */
698  res = w25qxx_only_spi_read(&gs_handle, addr, gs_buffer_output, 256);
699  if (res != 0)
700  {
701  w25qxx_interface_debug_print("w25qxx: only spi read failed.\n");
702  (void)w25qxx_deinit(&gs_handle);
703 
704  return 1;
705  }
706  for (j = 0; j < 256; j++)
707  {
708  if (gs_buffer_input[j] != gs_buffer_output[j])
709  {
710  w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
711  (void)w25qxx_deinit(&gs_handle);
712 
713  return 1;
714  }
715  }
716  w25qxx_interface_debug_print("w25qxx: only spi read test passed.\n");
717 
718  /* w25qxx_fast_read */
719  res = w25qxx_fast_read(&gs_handle, addr, gs_buffer_output, 256);
720  if (res != 0)
721  {
722  w25qxx_interface_debug_print("w25qxx: fast read failed.\n");
723  (void)w25qxx_deinit(&gs_handle);
724 
725  return 1;
726  }
727  for (j = 0; j < 256; j++)
728  {
729  if (gs_buffer_input[j] != gs_buffer_output[j])
730  {
731  w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
732  (void)w25qxx_deinit(&gs_handle);
733 
734  return 1;
735  }
736  }
737  w25qxx_interface_debug_print("w25qxx: fast read test passed.\n");
738 
739  /* w25qxx_block_erase_64k test */
740  addr = (rand() % 10) * 64 * 1024;
741  w25qxx_interface_debug_print("w25qxx: w25qxx_block_erase_64k test with address 0x%X.\n", addr);
742  res = w25qxx_block_erase_64k(&gs_handle, addr);
743  if (res != 0)
744  {
745  w25qxx_interface_debug_print("w25qxx: sector erase 64k failed.\n");
746  (void)w25qxx_deinit(&gs_handle);
747 
748  return 1;
749  }
750  for (j = 0; j < 256; j++)
751  {
752  gs_buffer_input[j] = rand() %256;
753  }
754 
755  /* w25qxx_page_program */
756  res = w25qxx_page_program(&gs_handle, addr, gs_buffer_input, 256);
757  if (res != 0)
758  {
759  w25qxx_interface_debug_print("w25qxx: page program failed.\n");
760  (void)w25qxx_deinit(&gs_handle);
761 
762  return 1;
763  }
764 
765  /* w25qxx_only_spi_read */
766  res = w25qxx_only_spi_read(&gs_handle, addr, gs_buffer_output, 256);
767  if (res != 0)
768  {
769  w25qxx_interface_debug_print("w25qxx: only spi read failed.\n");
770  (void)w25qxx_deinit(&gs_handle);
771 
772  return 1;
773  }
774  for (j = 0; j < 256; j++)
775  {
776  if (gs_buffer_input[j] != gs_buffer_output[j])
777  {
778  w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
779  (void)w25qxx_deinit(&gs_handle);
780 
781  return 1;
782  }
783  }
784  w25qxx_interface_debug_print("w25qxx: only spi read test passed.\n");
785 
786  /* w25qxx_fast_read */
787  res = w25qxx_fast_read(&gs_handle, addr, gs_buffer_output, 256);
788  if (res != 0)
789  {
790  w25qxx_interface_debug_print("w25qxx: fast read failed.\n");
791  (void)w25qxx_deinit(&gs_handle);
792 
793  return 1;
794  }
795  for (j = 0; j < 256; j++)
796  {
797  if (gs_buffer_input[j] != gs_buffer_output[j])
798  {
799  w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
800  (void)w25qxx_deinit(&gs_handle);
801 
802  return 1;
803  }
804  }
805  w25qxx_interface_debug_print("w25qxx: fast read test passed.\n");
806 
807  /* get sfdp */
808  w25qxx_interface_debug_print("w25qxx: get sfdp.\n");
809  memset(gs_buffer_output, 0, sizeof(uint8_t) * 256);
810  res = w25qxx_get_sfdp(&gs_handle, (uint8_t *)gs_buffer_output);
811  if (res != 0)
812  {
813  w25qxx_interface_debug_print("w25qxx: get sfdp failed.\n");
814  (void)w25qxx_deinit(&gs_handle);
815 
816  return 1;
817  }
818  for (j = 0; j < 256; j += 8)
819  {
820  w25qxx_interface_debug_print("w25qxx: sdfp[%d-%d] is 0x%02X 0x%02X 0x%02X 0x%02X 0x%02X 0x%02X 0x%02X 0x%02X.\n",
821  j , j + 7,
822  gs_buffer_output[j + 0], gs_buffer_output[j + 1], gs_buffer_output[j + 2],
823  gs_buffer_output[j + 3], gs_buffer_output[j + 4], gs_buffer_output[j + 5],
824  gs_buffer_output[j + 6], gs_buffer_output[j + 7]);
825  }
826 
827  /* security register1 write and read test */
828  w25qxx_interface_debug_print("w25qxx: security register1 write and read test.\n");
829 
830  /* security register1 write and read test */
831  res = w25qxx_erase_security_register(&gs_handle, W25QXX_SECURITY_REGISTER_1);
832  if (res != 0)
833  {
834  w25qxx_interface_debug_print("w25qxx: erase security register failed.\n");
835  (void)w25qxx_deinit(&gs_handle);
836 
837  return 1;
838  }
839  for (j = 0; j < 256; j++)
840  {
841  gs_buffer_input[j] = rand() %256;
842  }
843  res = w25qxx_program_security_register(&gs_handle, W25QXX_SECURITY_REGISTER_1, gs_buffer_input);
844  if (res != 0)
845  {
846  w25qxx_interface_debug_print("w25qxx: program security register failed.\n");
847  (void)w25qxx_deinit(&gs_handle);
848 
849  return 1;
850  }
851  res = w25qxx_read_security_register(&gs_handle, W25QXX_SECURITY_REGISTER_1, gs_buffer_output);
852  if (res != 0)
853  {
854  w25qxx_interface_debug_print("w25qxx: read security register failed.\n");
855  (void)w25qxx_deinit(&gs_handle);
856 
857  return 1;
858  }
859  for (j = 0; j < 256; j++)
860  {
861  if (gs_buffer_input[j] != gs_buffer_output[j])
862  {
863  w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
864  (void)w25qxx_deinit(&gs_handle);
865 
866  return 1;
867  }
868  }
869  w25qxx_interface_debug_print("w25qxx: security register1 check passed.\n");
870 
871  /* security register2 write and read test */
872  w25qxx_interface_debug_print("w25qxx: security register2 write and read test.\n");
873 
874  /* security register2 write and read test */
875  res = w25qxx_erase_security_register(&gs_handle, W25QXX_SECURITY_REGISTER_2);
876  if (res != 0)
877  {
878  w25qxx_interface_debug_print("w25qxx: erase security register failed.\n");
879  (void)w25qxx_deinit(&gs_handle);
880 
881  return 1;
882  }
883  for (j = 0; j < 256; j++)
884  {
885  gs_buffer_input[j] = rand() %256;
886  }
887  res = w25qxx_program_security_register(&gs_handle, W25QXX_SECURITY_REGISTER_2, gs_buffer_input);
888  if (res != 0)
889  {
890  w25qxx_interface_debug_print("w25qxx: program security register failed.\n");
891  (void)w25qxx_deinit(&gs_handle);
892 
893  return 1;
894  }
895  res = w25qxx_read_security_register(&gs_handle, W25QXX_SECURITY_REGISTER_2, gs_buffer_output);
896  if (res != 0)
897  {
898  w25qxx_interface_debug_print("w25qxx: read security register failed.\n");
899  (void)w25qxx_deinit(&gs_handle);
900 
901  return 1;
902  }
903  for (j = 0; j < 256; j++)
904  {
905  if (gs_buffer_input[j] != gs_buffer_output[j])
906  {
907  w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
908  (void)w25qxx_deinit(&gs_handle);
909 
910  return 1;
911  }
912  }
913  w25qxx_interface_debug_print("w25qxx: security register2 check passed.\n");
914 
915  /* security register3 write and read test */
916  w25qxx_interface_debug_print("w25qxx: security register3 write and read test.\n");
917 
918  /* security register3 write and read test */
919  res = w25qxx_erase_security_register(&gs_handle, W25QXX_SECURITY_REGISTER_3);
920  if (res != 0)
921  {
922  w25qxx_interface_debug_print("w25qxx: erase security register failed.\n");
923  (void)w25qxx_deinit(&gs_handle);
924 
925  return 1;
926  }
927  for (j = 0; j < 256; j++)
928  {
929  gs_buffer_input[j] = rand() %256;
930  }
931  res = w25qxx_program_security_register(&gs_handle, W25QXX_SECURITY_REGISTER_3, gs_buffer_input);
932  if (res != 0)
933  {
934  w25qxx_interface_debug_print("w25qxx: program security register failed.\n");
935  (void)w25qxx_deinit(&gs_handle);
936 
937  return 1;
938  }
939  res = w25qxx_read_security_register(&gs_handle, W25QXX_SECURITY_REGISTER_3, gs_buffer_output);
940  if (res != 0)
941  {
942  w25qxx_interface_debug_print("w25qxx: read security register failed.\n");
943  (void)w25qxx_deinit(&gs_handle);
944 
945  return 1;
946  }
947  for (j = 0; j < 256; j++)
948  {
949  if (gs_buffer_input[j] != gs_buffer_output[j])
950  {
951  w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
952  (void)w25qxx_deinit(&gs_handle);
953 
954  return 1;
955  }
956  }
957  w25qxx_interface_debug_print("w25qxx: security register3 check passed.\n");
958 
959  /* set address mode 3 byte */
960  w25qxx_interface_debug_print("w25qxx: set address mode 3 byte.\n");
961 
962  /* set address mode 3 byte */
963  res = w25qxx_set_address_mode(&gs_handle, W25QXX_ADDRESS_MODE_3_BYTE);
964  if (res != 0)
965  {
966  w25qxx_interface_debug_print("w25qxx: set address mode failed.\n");
967  (void)w25qxx_deinit(&gs_handle);
968 
969  return 1;
970  }
971  }
972  }
973  else
974  {
975  uint32_t size;
976  uint32_t addr, step, j;
977 
978  size = gsc_size[type - W25Q80];
979  step = size / 16;
980 
981  /* w25qxx_write/w25qxx_read test */
982  w25qxx_interface_debug_print("w25qxx: w25qxx_write/w25qxx_read test.\n");
983 
984  for (addr = 0; addr < size; addr += step)
985  {
986  for (j = 0; j < 600; j++)
987  {
988  gs_buffer_input[j] = rand() %256;
989  }
990  res = w25qxx_write(&gs_handle, addr, gs_buffer_input, 600);
991  if (res != 0)
992  {
993  w25qxx_interface_debug_print("w25qxx: write failed.\n");
994  (void)w25qxx_deinit(&gs_handle);
995 
996  return 1;
997  }
998  res = w25qxx_read(&gs_handle, addr, gs_buffer_output, 600);
999  if (res != 0)
1000  {
1001  w25qxx_interface_debug_print("w25qxx: read failed.\n");
1002  (void)w25qxx_deinit(&gs_handle);
1003 
1004  return 1;
1005  }
1006  for (j = 0; j < 600; j++)
1007  {
1008  if (gs_buffer_input[j] != gs_buffer_output[j])
1009  {
1010  w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
1011  (void)w25qxx_deinit(&gs_handle);
1012 
1013  return 1;
1014  }
1015  }
1016  w25qxx_interface_debug_print("w25qxx: 0x%08X/0x%08X successful.\n", addr, size);
1017  }
1018 
1019  /* w25qxx_sector_erase_4k test */
1020  addr = (rand() % 10) * 4 * 1024;
1021  w25qxx_interface_debug_print("w25qxx: w25qxx_sector_erase_4k test with address 0x%X.\n", addr);
1022  res = w25qxx_sector_erase_4k(&gs_handle, addr);
1023  if (res != 0)
1024  {
1025  w25qxx_interface_debug_print("w25qxx: sector erase 4k failed.\n");
1026  (void)w25qxx_deinit(&gs_handle);
1027 
1028  return 1;
1029  }
1030  for (j = 0; j < 256; j++)
1031  {
1032  gs_buffer_input[j] = rand() %256;
1033  }
1034 
1035  /* w25qxx_page_program */
1036  res = w25qxx_page_program(&gs_handle, addr, gs_buffer_input, 256);
1037  if (res != 0)
1038  {
1039  w25qxx_interface_debug_print("w25qxx: page program failed.\n");
1040  (void)w25qxx_deinit(&gs_handle);
1041 
1042  return 1;
1043  }
1044 
1045  /* w25qxx_fast_read */
1046  res = w25qxx_fast_read(&gs_handle, addr, gs_buffer_output, 256);
1047  if (res != 0)
1048  {
1049  w25qxx_interface_debug_print("w25qxx: fast read failed.\n");
1050  (void)w25qxx_deinit(&gs_handle);
1051 
1052  return 1;
1053  }
1054  for (j = 0; j < 256; j++)
1055  {
1056  if (gs_buffer_input[j] != gs_buffer_output[j])
1057  {
1058  w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
1059  (void)w25qxx_deinit(&gs_handle);
1060 
1061  return 1;
1062  }
1063  }
1064  w25qxx_interface_debug_print("w25qxx: fast read test passed.\n");
1065 
1066  /* w25qxx_block_erase_32k test */
1067  addr = (rand() % 10) * 32 * 1024;
1068  w25qxx_interface_debug_print("w25qxx: w25qxx_block_erase_32k test with address 0x%X.\n", addr);
1069  res = w25qxx_block_erase_32k(&gs_handle, addr);
1070  if (res != 0)
1071  {
1072  w25qxx_interface_debug_print("w25qxx: sector erase 32k failed.\n");
1073  (void)w25qxx_deinit(&gs_handle);
1074 
1075  return 1;
1076  }
1077  for (j = 0; j < 256; j++)
1078  {
1079  gs_buffer_input[j] = rand() %256;
1080  }
1081 
1082  /* w25qxx_page_program */
1083  res = w25qxx_page_program(&gs_handle, addr, gs_buffer_input, 256);
1084  if (res != 0)
1085  {
1086  w25qxx_interface_debug_print("w25qxx: page program failed.\n");
1087  (void)w25qxx_deinit(&gs_handle);
1088 
1089  return 1;
1090  }
1091 
1092  /* w25qxx_fast_read */
1093  res = w25qxx_fast_read(&gs_handle, addr, gs_buffer_output, 256);
1094  if (res != 0)
1095  {
1096  w25qxx_interface_debug_print("w25qxx: fast read failed.\n");
1097  (void)w25qxx_deinit(&gs_handle);
1098 
1099  return 1;
1100  }
1101  for (j = 0; j < 256; j++)
1102  {
1103  if (gs_buffer_input[j] != gs_buffer_output[j])
1104  {
1105  w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
1106  (void)w25qxx_deinit(&gs_handle);
1107 
1108  return 1;
1109  }
1110  }
1111  w25qxx_interface_debug_print("w25qxx: fast read test passed.\n");
1112 
1113  /* w25qxx_block_erase_64k test */
1114  addr = (rand() % 10) * 64 * 1024;
1115  w25qxx_interface_debug_print("w25qxx: w25qxx_block_erase_64k test with address 0x%X.\n", addr);
1116  res = w25qxx_block_erase_64k(&gs_handle, addr);
1117  if (res != 0)
1118  {
1119  w25qxx_interface_debug_print("w25qxx: sector erase 64k failed.\n");
1120  (void)w25qxx_deinit(&gs_handle);
1121 
1122  return 1;
1123  }
1124  for (j = 0; j < 256; j++)
1125  {
1126  gs_buffer_input[j] = rand() %256;
1127  }
1128 
1129  /* w25qxx_page_program */
1130  res = w25qxx_page_program(&gs_handle, addr, gs_buffer_input, 256);
1131  if (res != 0)
1132  {
1133  w25qxx_interface_debug_print("w25qxx: page program failed.\n");
1134  (void)w25qxx_deinit(&gs_handle);
1135 
1136  return 1;
1137  }
1138 
1139  /* w25qxx_fast_read */
1140  res = w25qxx_fast_read(&gs_handle, addr, gs_buffer_output, 256);
1141  if (res != 0)
1142  {
1143  w25qxx_interface_debug_print("w25qxx: fast read failed.\n");
1144  (void)w25qxx_deinit(&gs_handle);
1145 
1146  return 1;
1147  }
1148  for (j = 0; j < 256; j++)
1149  {
1150  if (gs_buffer_input[j] != gs_buffer_output[j])
1151  {
1152  w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
1153  (void)w25qxx_deinit(&gs_handle);
1154 
1155  return 1;
1156  }
1157  }
1158  w25qxx_interface_debug_print("w25qxx: fast read test passed.\n");
1159 
1160  #if (W25QXX_ENABLE_ERASE_READ_TEST == 1)
1161  /* start chip erasing */
1162  w25qxx_interface_debug_print("w25qxx: start chip erasing.\n");
1163 
1164  /* chip erase */
1165  w25qxx_interface_debug_print("w25qxx: w25qxx_chip_erase test.\n");
1166  res = w25qxx_chip_erase(&gs_handle);
1167  if (res != 0)
1168  {
1169  w25qxx_interface_debug_print("w25qxx: chip erase failed.\n");
1170  (void)w25qxx_deinit(&gs_handle);
1171 
1172  return 1;
1173  }
1174  w25qxx_interface_debug_print("w25qxx: chip erase successful.\n");
1175  #endif
1176 
1177  if (type >= W25Q256)
1178  {
1179  /* set address mode 4 byte */
1180  w25qxx_interface_debug_print("w25qxx: set address mode 4 byte.\n");
1181 
1182  /* set address mode 4 byte */
1183  res = w25qxx_set_address_mode(&gs_handle, W25QXX_ADDRESS_MODE_4_BYTE);
1184  if (res != 0)
1185  {
1186  w25qxx_interface_debug_print("w25qxx: set address mode failed.\n");
1187  (void)w25qxx_deinit(&gs_handle);
1188 
1189  return 1;
1190  }
1191 
1192  /* w25qxx_write/w25qxx_read test */
1193  w25qxx_interface_debug_print("w25qxx: w25qxx_write/w25qxx_read test.\n");
1194 
1195  for (addr = 0; addr < size; addr += step)
1196  {
1197  for (j = 0; j < 600; j++)
1198  {
1199  gs_buffer_input[j] = rand() %256;
1200  }
1201  res = w25qxx_write(&gs_handle, addr, gs_buffer_input, 600);
1202  if (res != 0)
1203  {
1204  w25qxx_interface_debug_print("w25qxx: write failed.\n");
1205  (void)w25qxx_deinit(&gs_handle);
1206 
1207  return 1;
1208  }
1209  res = w25qxx_read(&gs_handle, addr, gs_buffer_output, 600);
1210  if (res != 0)
1211  {
1212  w25qxx_interface_debug_print("w25qxx: read failed.\n");
1213  (void)w25qxx_deinit(&gs_handle);
1214 
1215  return 1;
1216  }
1217  for (j = 0; j < 600; j++)
1218  {
1219  if (gs_buffer_input[j] != gs_buffer_output[j])
1220  {
1221  w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
1222  (void)w25qxx_deinit(&gs_handle);
1223 
1224  return 1;
1225  }
1226  }
1227  w25qxx_interface_debug_print("w25qxx: 0x%08X/0x%08X successful.\n", addr, size);
1228  }
1229 
1230  /* w25qxx_sector_erase_4k test */
1231  addr = (rand() % 10) * 4 * 1024;
1232  w25qxx_interface_debug_print("w25qxx: w25qxx_sector_erase_4k test with address 0x%X.\n", addr);
1233  res = w25qxx_sector_erase_4k(&gs_handle, addr);
1234  if (res != 0)
1235  {
1236  w25qxx_interface_debug_print("w25qxx: sector erase 4k failed.\n");
1237  (void)w25qxx_deinit(&gs_handle);
1238 
1239  return 1;
1240  }
1241  for (j = 0; j < 256; j++)
1242  {
1243  gs_buffer_input[j] = rand() %256;
1244  }
1245 
1246  /* w25qxx_page_program */
1247  res = w25qxx_page_program(&gs_handle, addr, gs_buffer_input, 256);
1248  if (res != 0)
1249  {
1250  w25qxx_interface_debug_print("w25qxx: page program failed.\n");
1251  (void)w25qxx_deinit(&gs_handle);
1252 
1253  return 1;
1254  }
1255 
1256  /* w25qxx_fast_read */
1257  res = w25qxx_fast_read(&gs_handle, addr, gs_buffer_output, 256);
1258  if (res != 0)
1259  {
1260  w25qxx_interface_debug_print("w25qxx: fast read failed.\n");
1261  (void)w25qxx_deinit(&gs_handle);
1262 
1263  return 1;
1264  }
1265  for (j = 0; j < 256; j++)
1266  {
1267  if (gs_buffer_input[j] != gs_buffer_output[j])
1268  {
1269  w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
1270  (void)w25qxx_deinit(&gs_handle);
1271 
1272  return 1;
1273  }
1274  }
1275  w25qxx_interface_debug_print("w25qxx: fast read test passed.\n");
1276 
1277  /* w25qxx_block_erase_32k test */
1278  addr = (rand() % 10) * 32 * 1024;
1279  w25qxx_interface_debug_print("w25qxx: w25qxx_block_erase_32k test with address 0x%X.\n", addr);
1280  res = w25qxx_block_erase_32k(&gs_handle, addr);
1281  if (res != 0)
1282  {
1283  w25qxx_interface_debug_print("w25qxx: sector erase 32k failed.\n");
1284  (void)w25qxx_deinit(&gs_handle);
1285 
1286  return 1;
1287  }
1288  for (j = 0; j < 256; j++)
1289  {
1290  gs_buffer_input[j] = rand() %256;
1291  }
1292 
1293  /* w25qxx_page_program */
1294  res = w25qxx_page_program(&gs_handle, addr, gs_buffer_input, 256);
1295  if (res != 0)
1296  {
1297  w25qxx_interface_debug_print("w25qxx: page program failed.\n");
1298  (void)w25qxx_deinit(&gs_handle);
1299 
1300  return 1;
1301  }
1302 
1303  /* w25qxx_fast_read */
1304  res = w25qxx_fast_read(&gs_handle, addr, gs_buffer_output, 256);
1305  if (res != 0)
1306  {
1307  w25qxx_interface_debug_print("w25qxx: fast read failed.\n");
1308  (void)w25qxx_deinit(&gs_handle);
1309 
1310  return 1;
1311  }
1312  for (j = 0; j < 256; j++)
1313  {
1314  if (gs_buffer_input[j] != gs_buffer_output[j])
1315  {
1316  w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
1317  (void)w25qxx_deinit(&gs_handle);
1318 
1319  return 1;
1320  }
1321  }
1322  w25qxx_interface_debug_print("w25qxx: fast read test passed.\n");
1323 
1324  /* w25qxx_block_erase_64k test */
1325  addr = (rand() % 10) * 64 * 1024;
1326  w25qxx_interface_debug_print("w25qxx: w25qxx_block_erase_64k test with address 0x%X.\n", addr);
1327  res = w25qxx_block_erase_64k(&gs_handle, addr);
1328  if (res != 0)
1329  {
1330  w25qxx_interface_debug_print("w25qxx: sector erase 64k failed.\n");
1331  (void)w25qxx_deinit(&gs_handle);
1332 
1333  return 1;
1334  }
1335  for (j = 0; j < 256; j++)
1336  {
1337  gs_buffer_input[j] = rand() %256;
1338  }
1339 
1340  /* w25qxx_page_program */
1341  res = w25qxx_page_program(&gs_handle, addr, gs_buffer_input, 256);
1342  if (res != 0)
1343  {
1344  w25qxx_interface_debug_print("w25qxx: page program failed.\n");
1345  (void)w25qxx_deinit(&gs_handle);
1346 
1347  return 1;
1348  }
1349 
1350  /* w25qxx_fast_read */
1351  res = w25qxx_fast_read(&gs_handle, addr, gs_buffer_output, 256);
1352  if (res != 0)
1353  {
1354  w25qxx_interface_debug_print("w25qxx: fast read failed.\n");
1355  (void)w25qxx_deinit(&gs_handle);
1356 
1357  return 1;
1358  }
1359  for (j = 0; j < 256; j++)
1360  {
1361  if (gs_buffer_input[j] != gs_buffer_output[j])
1362  {
1363  w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
1364  (void)w25qxx_deinit(&gs_handle);
1365 
1366  return 1;
1367  }
1368  }
1369  w25qxx_interface_debug_print("w25qxx: fast read test passed.\n");
1370 
1371  /* set address mode 3 byte */
1372  w25qxx_interface_debug_print("w25qxx: set address mode 3 byte.\n");
1373 
1374  /* set address mode 3 byte */
1375  res = w25qxx_set_address_mode(&gs_handle, W25QXX_ADDRESS_MODE_3_BYTE);
1376  if (res != 0)
1377  {
1378  w25qxx_interface_debug_print("w25qxx: set address mode failed.\n");
1379  (void)w25qxx_deinit(&gs_handle);
1380 
1381  return 1;
1382  }
1383  }
1384 
1385  if (dual_quad_spi_enable != 0)
1386  {
1387  /* enter to spi mode */
1388  w25qxx_interface_debug_print("w25qxx: enter to spi mode.\n");
1389 
1390  /* exit qspi */
1391  res = w25qxx_exit_qspi_mode(&gs_handle);
1392  if (res != 0)
1393  {
1394  w25qxx_interface_debug_print("w25qxx: exit qspi mode failed.\n");
1395  (void)w25qxx_deinit(&gs_handle);
1396 
1397  return 1;
1398  }
1399 
1400  /* set chip interface spi */
1401  res = w25qxx_set_interface(&gs_handle, W25QXX_INTERFACE_SPI);
1402  if (res != 0)
1403  {
1404  w25qxx_interface_debug_print("w25qxx: set interface failed.\n");
1405 
1406  return 1;
1407  }
1408 
1409  /* random data */
1410  for (j = 0; j < 256; j++)
1411  {
1412  gs_buffer_input[j] = rand() %256;
1413  }
1414 
1415  /* w25qxx_sector_erase_4k */
1416  res = w25qxx_sector_erase_4k(&gs_handle, 0x00000000);
1417  if (res != 0)
1418  {
1419  w25qxx_interface_debug_print("w25qxx: sector erase 4k failed.\n");
1420  (void)w25qxx_deinit(&gs_handle);
1421 
1422  return 1;
1423  }
1424 
1425  /* w25qxx_page_program */
1426  res = w25qxx_page_program(&gs_handle, 0x00000000, gs_buffer_input, 256);
1427  if (res != 0)
1428  {
1429  w25qxx_interface_debug_print("w25qxx: page program failed.\n");
1430  (void)w25qxx_deinit(&gs_handle);
1431 
1432  return 1;
1433  }
1434 
1435  /* fast read dual output */
1436  res = w25qxx_fast_read_dual_output(&gs_handle, 0x00000000, gs_buffer_output, 256);
1437  if (res != 0)
1438  {
1439  w25qxx_interface_debug_print("w25qxx: fast read dual output failed.\n");
1440  (void)w25qxx_deinit(&gs_handle);
1441 
1442  return 1;
1443  }
1444  for (j = 0; j < 256; j++)
1445  {
1446  if (gs_buffer_input[j] != gs_buffer_output[j])
1447  {
1448  w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
1449  (void)w25qxx_deinit(&gs_handle);
1450 
1451  return 1;
1452  }
1453  }
1454  w25qxx_interface_debug_print("w25qxx: fast_read_dual_output check passed.\n");
1455 
1456  /* fast read quad output */
1457  res = w25qxx_fast_read_quad_output(&gs_handle, 0x00000000, gs_buffer_output, 256);
1458  if (res != 0)
1459  {
1460  w25qxx_interface_debug_print("w25qxx: fast read quad output failed.\n");
1461  (void)w25qxx_deinit(&gs_handle);
1462 
1463  return 1;
1464  }
1465  for (j = 0; j < 256; j++)
1466  {
1467  if (gs_buffer_input[j] != gs_buffer_output[j])
1468  {
1469  w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
1470  (void)w25qxx_deinit(&gs_handle);
1471 
1472  return 1;
1473  }
1474  }
1475  w25qxx_interface_debug_print("w25qxx: fast_read_quad_output check passed.\n");
1476 
1477  /* fast read dual io */
1478  res = w25qxx_fast_read_dual_io(&gs_handle, 0x00000000, gs_buffer_output, 256);
1479  if (res != 0)
1480  {
1481  w25qxx_interface_debug_print("w25qxx: fast read dual io failed.\n");
1482  (void)w25qxx_deinit(&gs_handle);
1483 
1484  return 1;
1485  }
1486  for (j = 0; j < 256; j++)
1487  {
1488  if (gs_buffer_input[j] != gs_buffer_output[j])
1489  {
1490  w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
1491  (void)w25qxx_deinit(&gs_handle);
1492 
1493  return 1;
1494  }
1495  }
1496  w25qxx_interface_debug_print("w25qxx: w25qxx_fast_read_dual_io check passed.\n");
1497 
1498  /* fast read quad io */
1499  res = w25qxx_fast_read_quad_io(&gs_handle, 0x00000000, gs_buffer_output, 256);
1500  if (res != 0)
1501  {
1502  w25qxx_interface_debug_print("w25qxx: fast read quad io failed.\n");
1503  (void)w25qxx_deinit(&gs_handle);
1504 
1505  return 1;
1506  }
1507  for (j = 0; j < 256; j++)
1508  {
1509  if (gs_buffer_input[j] != gs_buffer_output[j])
1510  {
1511  w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
1512  (void)w25qxx_deinit(&gs_handle);
1513 
1514  return 1;
1515  }
1516  }
1517  w25qxx_interface_debug_print("w25qxx: w25qxx_fast_read_quad_io check passed.\n");
1518 
1519  /* word read quad io */
1520  res = w25qxx_word_read_quad_io(&gs_handle, 0x00000000, gs_buffer_output, 256);
1521  if (res != 0)
1522  {
1523  w25qxx_interface_debug_print("w25qxx: word read quad io failed.\n");
1524  (void)w25qxx_deinit(&gs_handle);
1525 
1526  return 1;
1527  }
1528  for (j = 0; j < 256; j++)
1529  {
1530  if (gs_buffer_input[j] != gs_buffer_output[j])
1531  {
1532  w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
1533  (void)w25qxx_deinit(&gs_handle);
1534 
1535  return 1;
1536  }
1537  }
1538  w25qxx_interface_debug_print("w25qxx: w25qxx_word_read_quad_io check passed.\n");
1539 
1540  /* octal read quad io */
1541  res = w25qxx_octal_word_read_quad_io(&gs_handle, 0x00000000, gs_buffer_output, 256);
1542  if (res != 0)
1543  {
1544  w25qxx_interface_debug_print("w25qxx: octal read quad io failed.\n");
1545  (void)w25qxx_deinit(&gs_handle);
1546 
1547  return 1;
1548  }
1549  for (j = 0; j < 256; j++)
1550  {
1551  if (gs_buffer_input[j] != gs_buffer_output[j])
1552  {
1553  w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
1554  (void)w25qxx_deinit(&gs_handle);
1555 
1556  return 1;
1557  }
1558  }
1559  w25qxx_interface_debug_print("w25qxx: w25qxx_octal_word_read_quad_io check passed.\n");
1560 
1561  /* random data */
1562  for (j = 0; j < 256; j++)
1563  {
1564  gs_buffer_input[j] = rand() %256;
1565  }
1566 
1567  /* w25qxx_sector_erase_4k */
1568  res = w25qxx_sector_erase_4k(&gs_handle, 0x00000000);
1569  if (res != 0)
1570  {
1571  w25qxx_interface_debug_print("w25qxx: sector erase 4k failed.\n");
1572  (void)w25qxx_deinit(&gs_handle);
1573 
1574  return 1;
1575  }
1576 
1577  /* w25qxx_page_program_quad_input */
1578  res = w25qxx_page_program_quad_input(&gs_handle, 0x00000000, gs_buffer_input, 256);
1579  if (res != 0)
1580  {
1581  w25qxx_interface_debug_print("w25qxx: page program quad input failed.\n");
1582  (void)w25qxx_deinit(&gs_handle);
1583 
1584  return 1;
1585  }
1586 
1587  /* fast read */
1588  res = w25qxx_fast_read(&gs_handle, 0x00000000, gs_buffer_output, 256);
1589  if (res != 0)
1590  {
1591  w25qxx_interface_debug_print("w25qxx: fast read failed.\n");
1592  (void)w25qxx_deinit(&gs_handle);
1593 
1594  return 1;
1595  }
1596  for (j = 0; j < 256; j++)
1597  {
1598  if (gs_buffer_input[j] != gs_buffer_output[j])
1599  {
1600  w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
1601  (void)w25qxx_deinit(&gs_handle);
1602 
1603  return 1;
1604  }
1605  }
1606  w25qxx_interface_debug_print("w25qxx: w25qxx_page_program_quad_input check passed.\n");
1607 
1608  if (type >= W25Q256)
1609  {
1610  /* set address mode 4 byte */
1611  w25qxx_interface_debug_print("w25qxx: set address mode 4 byte.\n");
1612 
1613  /* set address mode 4 byte */
1614  res = w25qxx_set_address_mode(&gs_handle, W25QXX_ADDRESS_MODE_4_BYTE);
1615  if (res != 0)
1616  {
1617  w25qxx_interface_debug_print("w25qxx: set address mode failed.\n");
1618  (void)w25qxx_deinit(&gs_handle);
1619 
1620  return 1;
1621  }
1622 
1623  /* random data */
1624  for (j = 0; j < 256; j++)
1625  {
1626  gs_buffer_input[j] = rand() %256;
1627  }
1628 
1629  /* w25qxx_sector_erase_4k */
1630  res = w25qxx_sector_erase_4k(&gs_handle, 0x00000000);
1631  if (res != 0)
1632  {
1633  w25qxx_interface_debug_print("w25qxx: sector erase 4k failed.\n");
1634  (void)w25qxx_deinit(&gs_handle);
1635 
1636  return 1;
1637  }
1638 
1639  /* w25qxx_page_program */
1640  res = w25qxx_page_program(&gs_handle, 0x00000000, gs_buffer_input, 256);
1641  if (res != 0)
1642  {
1643  w25qxx_interface_debug_print("w25qxx: page program failed.\n");
1644  (void)w25qxx_deinit(&gs_handle);
1645 
1646  return 1;
1647  }
1648 
1649  /* fast read dual output */
1650  res = w25qxx_fast_read_dual_output(&gs_handle, 0x00000000, gs_buffer_output, 256);
1651  if (res != 0)
1652  {
1653  w25qxx_interface_debug_print("w25qxx: fast read dual output failed.\n");
1654  (void)w25qxx_deinit(&gs_handle);
1655 
1656  return 1;
1657  }
1658  for (j = 0; j < 256; j++)
1659  {
1660  if (gs_buffer_input[j] != gs_buffer_output[j])
1661  {
1662  w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
1663  (void)w25qxx_deinit(&gs_handle);
1664 
1665  return 1;
1666  }
1667  }
1668  w25qxx_interface_debug_print("w25qxx: fast_read_dual_output check passed.\n");
1669 
1670  /* fast read quad output */
1671  res = w25qxx_fast_read_quad_output(&gs_handle, 0x00000000, gs_buffer_output, 256);
1672  if (res != 0)
1673  {
1674  w25qxx_interface_debug_print("w25qxx: fast read quad output failed.\n");
1675  (void)w25qxx_deinit(&gs_handle);
1676 
1677  return 1;
1678  }
1679  for (j = 0; j < 256; j++)
1680  {
1681  if (gs_buffer_input[j] != gs_buffer_output[j])
1682  {
1683  w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
1684  (void)w25qxx_deinit(&gs_handle);
1685 
1686  return 1;
1687  }
1688  }
1689  w25qxx_interface_debug_print("w25qxx: fast_read_quad_output check passed.\n");
1690 
1691  /* fast read dual io */
1692  res = w25qxx_fast_read_dual_io(&gs_handle, 0x00000000, gs_buffer_output, 256);
1693  if (res != 0)
1694  {
1695  w25qxx_interface_debug_print("w25qxx: fast read dual io failed.\n");
1696  (void)w25qxx_deinit(&gs_handle);
1697 
1698  return 1;
1699  }
1700  for (j = 0; j < 256; j++)
1701  {
1702  if (gs_buffer_input[j] != gs_buffer_output[j])
1703  {
1704  w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
1705  (void)w25qxx_deinit(&gs_handle);
1706 
1707  return 1;
1708  }
1709  }
1710  w25qxx_interface_debug_print("w25qxx: w25qxx_fast_read_dual_io check passed.\n");
1711 
1712  /* fast read quad io */
1713  res = w25qxx_fast_read_quad_io(&gs_handle, 0x00000000, gs_buffer_output, 256);
1714  if (res != 0)
1715  {
1716  w25qxx_interface_debug_print("w25qxx: fast read quad io failed.\n");
1717  (void)w25qxx_deinit(&gs_handle);
1718 
1719  return 1;
1720  }
1721  for (j = 0; j < 256; j++)
1722  {
1723  if (gs_buffer_input[j] != gs_buffer_output[j])
1724  {
1725  w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
1726  (void)w25qxx_deinit(&gs_handle);
1727 
1728  return 1;
1729  }
1730  }
1731  w25qxx_interface_debug_print("w25qxx: w25qxx_fast_read_quad_io check passed.\n");
1732 
1733  /* word read quad io */
1734  res = w25qxx_word_read_quad_io(&gs_handle, 0x00000000, gs_buffer_output, 256);
1735  if (res != 0)
1736  {
1737  w25qxx_interface_debug_print("w25qxx: word read quad io failed.\n");
1738  (void)w25qxx_deinit(&gs_handle);
1739 
1740  return 1;
1741  }
1742  for (j = 0; j < 256; j++)
1743  {
1744  if (gs_buffer_input[j] != gs_buffer_output[j])
1745  {
1746  w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
1747  (void)w25qxx_deinit(&gs_handle);
1748 
1749  return 1;
1750  }
1751  }
1752  w25qxx_interface_debug_print("w25qxx: w25qxx_word_read_quad_io check passed.\n");
1753 
1754  /* octal read quad io */
1755  res = w25qxx_octal_word_read_quad_io(&gs_handle, 0x00000000, gs_buffer_output, 256);
1756  if (res != 0)
1757  {
1758  w25qxx_interface_debug_print("w25qxx: octal read quad io failed.\n");
1759  (void)w25qxx_deinit(&gs_handle);
1760 
1761  return 1;
1762  }
1763  for (j = 0; j < 256; j++)
1764  {
1765  if (gs_buffer_input[j] != gs_buffer_output[j])
1766  {
1767  w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
1768  (void)w25qxx_deinit(&gs_handle);
1769 
1770  return 1;
1771  }
1772  }
1773  w25qxx_interface_debug_print("w25qxx: w25qxx_octal_word_read_quad_io check passed.\n");
1774 
1775  /* random data */
1776  for (j = 0; j < 256; j++)
1777  {
1778  gs_buffer_input[j] = rand() %256;
1779  }
1780 
1781  /* w25qxx_sector_erase_4k */
1782  res = w25qxx_sector_erase_4k(&gs_handle, 0x00000000);
1783  if (res != 0)
1784  {
1785  w25qxx_interface_debug_print("w25qxx: sector erase 4k failed.\n");
1786  (void)w25qxx_deinit(&gs_handle);
1787 
1788  return 1;
1789  }
1790 
1791  /* w25qxx_page_program_quad_input */
1792  res = w25qxx_page_program_quad_input(&gs_handle, 0x00000000, gs_buffer_input, 256);
1793  if (res != 0)
1794  {
1795  w25qxx_interface_debug_print("w25qxx: page program quad input failed.\n");
1796  (void)w25qxx_deinit(&gs_handle);
1797 
1798  return 1;
1799  }
1800 
1801  /* fast read */
1802  res = w25qxx_fast_read(&gs_handle, 0x00000000, gs_buffer_output, 256);
1803  if (res != 0)
1804  {
1805  w25qxx_interface_debug_print("w25qxx: fast read failed.\n");
1806  (void)w25qxx_deinit(&gs_handle);
1807 
1808  return 1;
1809  }
1810  for (j = 0; j < 256; j++)
1811  {
1812  if (gs_buffer_input[j] != gs_buffer_output[j])
1813  {
1814  w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
1815  (void)w25qxx_deinit(&gs_handle);
1816 
1817  return 1;
1818  }
1819  }
1820  w25qxx_interface_debug_print("w25qxx: w25qxx_page_program_quad_input check passed.\n");
1821 
1822  /* set address mode 3 byte */
1823  w25qxx_interface_debug_print("w25qxx: set address mode 3 byte.\n");
1824 
1825  /* set address mode 3 byte */
1826  res = w25qxx_set_address_mode(&gs_handle, W25QXX_ADDRESS_MODE_3_BYTE);
1827  if (res != 0)
1828  {
1829  w25qxx_interface_debug_print("w25qxx: set address mode failed.\n");
1830  (void)w25qxx_deinit(&gs_handle);
1831 
1832  return 1;
1833  }
1834  }
1835 
1836  /* enter to qspi mode */
1837  w25qxx_interface_debug_print("w25qxx: enter to qspi mode.\n");
1838 
1839  /* enter qspi */
1840  res = w25qxx_enter_qspi_mode(&gs_handle);
1841  if (res != 0)
1842  {
1843  w25qxx_interface_debug_print("w25qxx: enter qspi mode failed.\n");
1844  (void)w25qxx_deinit(&gs_handle);
1845 
1846  return 1;
1847  }
1848 
1849  /* set chip interface spi */
1850  res = w25qxx_set_interface(&gs_handle, W25QXX_INTERFACE_QSPI);
1851  if (res != 0)
1852  {
1853  w25qxx_interface_debug_print("w25qxx: set interface failed.\n");
1854 
1855  return 1;
1856  }
1857  }
1858 
1859  /* w25qxx_set_read_parameters test */
1860  w25qxx_interface_debug_print("w25qxx: w25qxx_set_read_parameters test.\n");
1861 
1862  /* 8 dummy max 80MHz test */
1863  w25qxx_interface_debug_print("w25qxx: set 8 dummy max 80MHz test.\n");
1864 
1865  res = w25qxx_set_read_parameters(&gs_handle, W25QXX_QSPI_READ_DUMMY_8_80MHZ, W25QXX_QSPI_READ_WRAP_LENGTH_8_BYTE);
1866  if (res != 0)
1867  {
1868  w25qxx_interface_debug_print("w25qxx: set read parameters.\n");
1869 
1870  return 1;
1871  }
1872 
1873  for (addr = 0; addr < size; addr += step)
1874  {
1875  for (j = 0; j < 600; j++)
1876  {
1877  gs_buffer_input[j] = rand() %256;
1878  }
1879  res = w25qxx_write(&gs_handle, addr, gs_buffer_input, 600);
1880  if (res != 0)
1881  {
1882  w25qxx_interface_debug_print("w25qxx: write failed.\n");
1883  (void)w25qxx_deinit(&gs_handle);
1884 
1885  return 1;
1886  }
1887  res = w25qxx_read(&gs_handle, addr, gs_buffer_output, 600);
1888  if (res != 0)
1889  {
1890  w25qxx_interface_debug_print("w25qxx: read failed.\n");
1891  (void)w25qxx_deinit(&gs_handle);
1892 
1893  return 1;
1894  }
1895  for (j = 0; j < 600; j++)
1896  {
1897  if (gs_buffer_input[j] != gs_buffer_output[j])
1898  {
1899  w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
1900  (void)w25qxx_deinit(&gs_handle);
1901 
1902  return 1;
1903  }
1904  }
1905  w25qxx_interface_debug_print("w25qxx: 0x%08X/0x%08X successful.\n", addr, size);
1906  }
1907 
1908  /* 6 dummy max 80MHz test */
1909  w25qxx_interface_debug_print("w25qxx: set 6 dummy max 80MHz test.\n");
1910 
1911  res = w25qxx_set_read_parameters(&gs_handle, W25QXX_QSPI_READ_DUMMY_6_80MHZ, W25QXX_QSPI_READ_WRAP_LENGTH_8_BYTE);
1912  if (res != 0)
1913  {
1914  w25qxx_interface_debug_print("w25qxx: set read parameters.\n");
1915 
1916  return 1;
1917  }
1918 
1919  for (addr = 0; addr < size; addr += step)
1920  {
1921  for (j = 0; j < 600; j++)
1922  {
1923  gs_buffer_input[j] = rand() %256;
1924  }
1925  res = w25qxx_write(&gs_handle, addr, gs_buffer_input, 600);
1926  if (res != 0)
1927  {
1928  w25qxx_interface_debug_print("w25qxx: write failed.\n");
1929  (void)w25qxx_deinit(&gs_handle);
1930 
1931  return 1;
1932  }
1933  res = w25qxx_read(&gs_handle, addr, gs_buffer_output, 600);
1934  if (res != 0)
1935  {
1936  w25qxx_interface_debug_print("w25qxx: read failed.\n");
1937  (void)w25qxx_deinit(&gs_handle);
1938 
1939  return 1;
1940  }
1941  for (j = 0; j < 600; j++)
1942  {
1943  if (gs_buffer_input[j] != gs_buffer_output[j])
1944  {
1945  w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
1946  (void)w25qxx_deinit(&gs_handle);
1947 
1948  return 1;
1949  }
1950  }
1951  w25qxx_interface_debug_print("w25qxx: 0x%08X/0x%08X successful.\n", addr, size);
1952  }
1953 
1954  /* 4 dummy max 55MHz test */
1955  w25qxx_interface_debug_print("w25qxx: set 4 dummy max 55MHz test.\n");
1956 
1957  res = w25qxx_set_read_parameters(&gs_handle, W25QXX_QSPI_READ_DUMMY_4_55MHZ, W25QXX_QSPI_READ_WRAP_LENGTH_8_BYTE);
1958  if (res != 0)
1959  {
1960  w25qxx_interface_debug_print("w25qxx: set read parameters.\n");
1961 
1962  return 1;
1963  }
1964 
1965  for (addr = 0; addr < size; addr += step)
1966  {
1967  for (j = 0; j < 600; j++)
1968  {
1969  gs_buffer_input[j] = rand() %256;
1970  }
1971  res = w25qxx_write(&gs_handle, addr, gs_buffer_input, 600);
1972  if (res != 0)
1973  {
1974  w25qxx_interface_debug_print("w25qxx: write failed.\n");
1975  (void)w25qxx_deinit(&gs_handle);
1976 
1977  return 1;
1978  }
1979  res = w25qxx_read(&gs_handle, addr, gs_buffer_output, 600);
1980  if (res != 0)
1981  {
1982  w25qxx_interface_debug_print("w25qxx: read failed.\n");
1983  (void)w25qxx_deinit(&gs_handle);
1984 
1985  return 1;
1986  }
1987  for (j = 0; j < 600; j++)
1988  {
1989  if (gs_buffer_input[j] != gs_buffer_output[j])
1990  {
1991  w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
1992  (void)w25qxx_deinit(&gs_handle);
1993 
1994  return 1;
1995  }
1996  }
1997  w25qxx_interface_debug_print("w25qxx: 0x%08X/0x%08X successful.\n", addr, size);
1998  }
1999 
2000  /* 2 dummy max 33MHz test */
2001  w25qxx_interface_debug_print("w25qxx: set 2 dummy max 33MHz test.\n");
2002 
2003  res = w25qxx_set_read_parameters(&gs_handle, W25QXX_QSPI_READ_DUMMY_2_33MHZ, W25QXX_QSPI_READ_WRAP_LENGTH_8_BYTE);
2004  if (res != 0)
2005  {
2006  w25qxx_interface_debug_print("w25qxx: set read parameters.\n");
2007 
2008  return 1;
2009  }
2010 
2011  for (addr = 0; addr < size; addr += step)
2012  {
2013  for (j = 0; j < 600; j++)
2014  {
2015  gs_buffer_input[j] = rand() %256;
2016  }
2017  res = w25qxx_write(&gs_handle, addr, gs_buffer_input, 600);
2018  if (res != 0)
2019  {
2020  w25qxx_interface_debug_print("w25qxx: write failed.\n");
2021  (void)w25qxx_deinit(&gs_handle);
2022 
2023  return 1;
2024  }
2025  res = w25qxx_read(&gs_handle, addr, gs_buffer_output, 600);
2026  if (res != 0)
2027  {
2028  w25qxx_interface_debug_print("w25qxx: read failed.\n");
2029  (void)w25qxx_deinit(&gs_handle);
2030 
2031  return 1;
2032  }
2033  for (j = 0; j < 600; j++)
2034  {
2035  if (gs_buffer_input[j] != gs_buffer_output[j])
2036  {
2037  w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
2038  (void)w25qxx_deinit(&gs_handle);
2039 
2040  return 1;
2041  }
2042  }
2043  w25qxx_interface_debug_print("w25qxx: 0x%08X/0x%08X successful.\n", addr, size);
2044  }
2045  }
2046 
2047  /* finish read test */
2048  w25qxx_interface_debug_print("w25qxx: finish read test.\n");
2049  (void)w25qxx_deinit(&gs_handle);
2050 
2051  return 0;
2052 }
driver_w25qxx_read_test.h
driver w25qxx read test header file
w25qxx_page_program_quad_input
uint8_t w25qxx_page_program_quad_input(w25qxx_handle_t *handle, uint32_t addr, uint8_t *data, uint16_t len)
quad page program with quad input
Definition: driver_w25qxx.c:4920
w25qxx_get_sfdp
uint8_t w25qxx_get_sfdp(w25qxx_handle_t *handle, uint8_t sfdp[256])
get the sfdp
Definition: driver_w25qxx.c:2880
w25qxx_read_security_register
uint8_t w25qxx_read_security_register(w25qxx_handle_t *handle, w25qxx_security_register_t num, uint8_t data[256])
read the security register
Definition: driver_w25qxx.c:3344
w25qxx_program_security_register
uint8_t w25qxx_program_security_register(w25qxx_handle_t *handle, w25qxx_security_register_t num, uint8_t data[256])
program the security register
Definition: driver_w25qxx.c:3147
w25qxx_exit_qspi_mode
uint8_t w25qxx_exit_qspi_mode(w25qxx_handle_t *handle)
exit the qspi mode
Definition: driver_w25qxx.c:2572
w25qxx_fast_read_dual_output
uint8_t w25qxx_fast_read_dual_output(w25qxx_handle_t *handle, uint32_t addr, uint8_t *data, uint32_t len)
read with dual output in the fast mode
Definition: driver_w25qxx.c:3858
w25qxx_octal_word_read_quad_io
uint8_t w25qxx_octal_word_read_quad_io(w25qxx_handle_t *handle, uint32_t addr, uint8_t *data, uint32_t len)
octal word read with quad io
Definition: driver_w25qxx.c:4459
w25qxx_set_read_parameters
uint8_t w25qxx_set_read_parameters(w25qxx_handle_t *handle, w25qxx_qspi_read_dummy_t dummy, w25qxx_qspi_read_wrap_length_t length)
set the read parameters
Definition: driver_w25qxx.c:2427
w25qxx_enter_qspi_mode
uint8_t w25qxx_enter_qspi_mode(w25qxx_handle_t *handle)
enter the qspi mode
Definition: driver_w25qxx.c:2494
w25qxx_fast_read_quad_io
uint8_t w25qxx_fast_read_quad_io(w25qxx_handle_t *handle, uint32_t addr, uint8_t *data, uint32_t len)
read with quad io in the fast mode
Definition: driver_w25qxx.c:4184
w25qxx_fast_read_dual_io
uint8_t w25qxx_fast_read_dual_io(w25qxx_handle_t *handle, uint32_t addr, uint8_t *data, uint32_t len)
read with dual io in the fast mode
Definition: driver_w25qxx.c:4076
w25qxx_word_read_quad_io
uint8_t w25qxx_word_read_quad_io(w25qxx_handle_t *handle, uint32_t addr, uint8_t *data, uint32_t len)
word read with quad io
Definition: driver_w25qxx.c:4350
w25qxx_erase_security_register
uint8_t w25qxx_erase_security_register(w25qxx_handle_t *handle, w25qxx_security_register_t num)
erase the security register
Definition: driver_w25qxx.c:2952
w25qxx_fast_read_quad_output
uint8_t w25qxx_fast_read_quad_output(w25qxx_handle_t *handle, uint32_t addr, uint8_t *data, uint32_t len)
read with quad output in the fast mode
Definition: driver_w25qxx.c:3967
W25QXX_QSPI_READ_WRAP_LENGTH_8_BYTE
@ W25QXX_QSPI_READ_WRAP_LENGTH_8_BYTE
Definition: driver_w25qxx.h:127
W25QXX_QSPI_READ_DUMMY_4_55MHZ
@ W25QXX_QSPI_READ_DUMMY_4_55MHZ
Definition: driver_w25qxx.h:117
W25QXX_QSPI_READ_DUMMY_6_80MHZ
@ W25QXX_QSPI_READ_DUMMY_6_80MHZ
Definition: driver_w25qxx.h:118
W25QXX_QSPI_READ_DUMMY_2_33MHZ
@ W25QXX_QSPI_READ_DUMMY_2_33MHZ
Definition: driver_w25qxx.h:116
W25QXX_QSPI_READ_DUMMY_8_80MHZ
@ W25QXX_QSPI_READ_DUMMY_8_80MHZ
Definition: driver_w25qxx.h:119
W25QXX_SECURITY_REGISTER_2
@ W25QXX_SECURITY_REGISTER_2
Definition: driver_w25qxx.h:140
W25QXX_SECURITY_REGISTER_3
@ W25QXX_SECURITY_REGISTER_3
Definition: driver_w25qxx.h:141
W25QXX_SECURITY_REGISTER_1
@ W25QXX_SECURITY_REGISTER_1
Definition: driver_w25qxx.h:139
w25qxx_chip_erase
uint8_t w25qxx_chip_erase(w25qxx_handle_t *handle)
erase the chip
Definition: driver_w25qxx.c:1459
w25qxx_only_spi_read
uint8_t w25qxx_only_spi_read(w25qxx_handle_t *handle, uint32_t addr, uint8_t *data, uint32_t len)
read only in the spi interface
Definition: driver_w25qxx.c:3465
w25qxx_block_erase_32k
uint8_t w25qxx_block_erase_32k(w25qxx_handle_t *handle, uint32_t addr)
erase the 32k block
Definition: driver_w25qxx.c:5419
w25qxx_set_interface
uint8_t w25qxx_set_interface(w25qxx_handle_t *handle, w25qxx_interface_t interface)
set the chip interface
Definition: driver_w25qxx.c:259
w25qxx_page_program
uint8_t w25qxx_page_program(w25qxx_handle_t *handle, uint32_t addr, uint8_t *data, uint16_t len)
page program
Definition: driver_w25qxx.c:4569
w25qxx_set_dual_quad_spi
uint8_t w25qxx_set_dual_quad_spi(w25qxx_handle_t *handle, w25qxx_bool_t enable)
enable or disable the dual quad spi
Definition: driver_w25qxx.c:175
w25qxx_type_t
w25qxx_type_t
w25qxx type enumeration definition
Definition: driver_w25qxx.h:63
w25qxx_init
uint8_t w25qxx_init(w25qxx_handle_t *handle)
initialize the chip
Definition: driver_w25qxx.c:6819
w25qxx_info
uint8_t w25qxx_info(w25qxx_info_t *info)
get chip's information
Definition: driver_w25qxx.c:8566
w25qxx_sector_erase_4k
uint8_t w25qxx_sector_erase_4k(w25qxx_handle_t *handle, uint32_t addr)
erase the 4k sector
Definition: driver_w25qxx.c:5080
w25qxx_deinit
uint8_t w25qxx_deinit(w25qxx_handle_t *handle)
close the chip
Definition: driver_w25qxx.c:7195
w25qxx_set_type
uint8_t w25qxx_set_type(w25qxx_handle_t *handle, w25qxx_type_t type)
set the chip type
Definition: driver_w25qxx.c:217
w25qxx_write
uint8_t w25qxx_write(w25qxx_handle_t *handle, uint32_t addr, uint8_t *data, uint32_t len)
write data
Definition: driver_w25qxx.c:8415
w25qxx_fast_read
uint8_t w25qxx_fast_read(w25qxx_handle_t *handle, uint32_t addr, uint8_t *data, uint32_t len)
read in the fast mode
Definition: driver_w25qxx.c:3634
w25qxx_interface_t
w25qxx_interface_t
w25qxx interface enumeration definition
Definition: driver_w25qxx.h:79
w25qxx_set_address_mode
uint8_t w25qxx_set_address_mode(w25qxx_handle_t *handle, w25qxx_address_mode_t mode)
set the chip address mode
Definition: driver_w25qxx.c:304
w25qxx_read
uint8_t w25qxx_read(w25qxx_handle_t *handle, uint32_t addr, uint8_t *data, uint32_t len)
read data
Definition: driver_w25qxx.c:7289
w25qxx_block_erase_64k
uint8_t w25qxx_block_erase_64k(w25qxx_handle_t *handle, uint32_t addr)
erase the 64k block
Definition: driver_w25qxx.c:5758
w25qxx_bool_t
w25qxx_bool_t
w25qxx bool enumeration definition
Definition: driver_w25qxx.h:88
W25Q80
@ W25Q80
Definition: driver_w25qxx.h:64
W25Q256
@ W25Q256
Definition: driver_w25qxx.h:69
W25QXX_ADDRESS_MODE_3_BYTE
@ W25QXX_ADDRESS_MODE_3_BYTE
Definition: driver_w25qxx.h:98
W25QXX_ADDRESS_MODE_4_BYTE
@ W25QXX_ADDRESS_MODE_4_BYTE
Definition: driver_w25qxx.h:99
W25QXX_INTERFACE_QSPI
@ W25QXX_INTERFACE_QSPI
Definition: driver_w25qxx.h:81
W25QXX_INTERFACE_SPI
@ W25QXX_INTERFACE_SPI
Definition: driver_w25qxx.h:80
w25qxx_interface_spi_qspi_deinit
uint8_t w25qxx_interface_spi_qspi_deinit(void)
interface spi qspi bus deinit
Definition: driver_w25qxx_interface_template.c:58
w25qxx_interface_spi_qspi_init
uint8_t w25qxx_interface_spi_qspi_init(void)
interface spi qspi bus init
Definition: driver_w25qxx_interface_template.c:46
w25qxx_interface_delay_us
void w25qxx_interface_delay_us(uint32_t us)
interface delay us
Definition: driver_w25qxx_interface_template.c:108
w25qxx_interface_spi_qspi_write_read
uint8_t w25qxx_interface_spi_qspi_write_read(uint8_t instruction, uint8_t instruction_line, uint32_t address, uint8_t address_line, uint8_t address_len, uint32_t alternate, uint8_t alternate_line, uint8_t alternate_len, uint8_t dummy, uint8_t *in_buf, uint32_t in_len, uint8_t *out_buf, uint32_t out_len, uint8_t data_line)
interface spi qspi bus write read
Definition: driver_w25qxx_interface_template.c:84
w25qxx_interface_debug_print
void w25qxx_interface_debug_print(const char *const fmt,...)
interface print format data
Definition: driver_w25qxx_interface_template.c:118
w25qxx_interface_delay_ms
void w25qxx_interface_delay_ms(uint32_t ms)
interface delay ms
Definition: driver_w25qxx_interface_template.c:98
DRIVER_W25QXX_LINK_DELAY_MS
#define DRIVER_W25QXX_LINK_DELAY_MS(HANDLE, FUC)
link delay_ms function
Definition: driver_w25qxx.h:300
DRIVER_W25QXX_LINK_INIT
#define DRIVER_W25QXX_LINK_INIT(HANDLE, STRUCTURE)
initialize w25qxx_handle_t structure
Definition: driver_w25qxx.h:268
DRIVER_W25QXX_LINK_SPI_QSPI_INIT
#define DRIVER_W25QXX_LINK_SPI_QSPI_INIT(HANDLE, FUC)
link spi_qspi_init function
Definition: driver_w25qxx.h:276
DRIVER_W25QXX_LINK_DEBUG_PRINT
#define DRIVER_W25QXX_LINK_DEBUG_PRINT(HANDLE, FUC)
link debug_print function
Definition: driver_w25qxx.h:316
DRIVER_W25QXX_LINK_SPI_QSPI_WRITE_READ
#define DRIVER_W25QXX_LINK_SPI_QSPI_WRITE_READ(HANDLE, FUC)
link spi_qspi_write_read function
Definition: driver_w25qxx.h:292
DRIVER_W25QXX_LINK_SPI_QSPI_DEINIT
#define DRIVER_W25QXX_LINK_SPI_QSPI_DEINIT(HANDLE, FUC)
link spi_qspi_deinit function
Definition: driver_w25qxx.h:284
DRIVER_W25QXX_LINK_DELAY_US
#define DRIVER_W25QXX_LINK_DELAY_US(HANDLE, FUC)
link delay_us function
Definition: driver_w25qxx.h:308
w25qxx_read_test
uint8_t w25qxx_read_test(w25qxx_type_t type, w25qxx_interface_t interface, w25qxx_bool_t dual_quad_spi_enable)
read test
Definition: driver_w25qxx_read_test.c:55
w25qxx_handle_s
w25qxx handle structure definition
Definition: driver_w25qxx.h:213
w25qxx_info_s
w25qxx information structure definition
Definition: driver_w25qxx.h:239
w25qxx_info_s::temperature_max
float temperature_max
Definition: driver_w25qxx.h:247
w25qxx_info_s::supply_voltage_max_v
float supply_voltage_max_v
Definition: driver_w25qxx.h:244
w25qxx_info_s::driver_version
uint32_t driver_version
Definition: driver_w25qxx.h:248
w25qxx_info_s::interface
char interface[16]
Definition: driver_w25qxx.h:242
w25qxx_info_s::temperature_min
float temperature_min
Definition: driver_w25qxx.h:246
w25qxx_info_s::max_current_ma
float max_current_ma
Definition: driver_w25qxx.h:245
w25qxx_info_s::manufacturer_name
char manufacturer_name[32]
Definition: driver_w25qxx.h:241
w25qxx_info_s::supply_voltage_min_v
float supply_voltage_min_v
Definition: driver_w25qxx.h:243
w25qxx_info_s::chip_name
char chip_name[32]
Definition: driver_w25qxx.h:240