LibDriver W25QXX
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driver_w25qxx_read_test.c
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1
36
37#include "driver_w25qxx_read_test.h"
38#include <stdlib.h>
39
40static w25qxx_handle_t gs_handle;
41static uint8_t gs_buffer_input[600];
42static uint8_t gs_buffer_output[600];
43
54uint8_t w25qxx_read_test(w25qxx_type_t type, w25qxx_interface_t interface, w25qxx_bool_t dual_quad_spi_enable)
55{
56 uint8_t res;
57 w25qxx_info_t info;
58
59 /* link interface function */
60 DRIVER_W25QXX_LINK_INIT(&gs_handle, w25qxx_handle_t);
61 DRIVER_W25QXX_LINK_SPI_QSPI_INIT(&gs_handle, w25qxx_interface_spi_qspi_init);
62 DRIVER_W25QXX_LINK_SPI_QSPI_DEINIT(&gs_handle, w25qxx_interface_spi_qspi_deinit);
63 DRIVER_W25QXX_LINK_SPI_QSPI_WRITE_READ(&gs_handle, w25qxx_interface_spi_qspi_write_read);
64 DRIVER_W25QXX_LINK_DELAY_MS(&gs_handle, w25qxx_interface_delay_ms);
65 DRIVER_W25QXX_LINK_DELAY_US(&gs_handle, w25qxx_interface_delay_us);
66 DRIVER_W25QXX_LINK_DEBUG_PRINT(&gs_handle, w25qxx_interface_debug_print);
67
68 /* get information */
69 res = w25qxx_info(&info);
70 if (res != 0)
71 {
72 w25qxx_interface_debug_print("w25qxx: get info failed.\n");
73
74 return 1;
75 }
76 else
77 {
78 /* print chip information */
79 w25qxx_interface_debug_print("w25qxx: chip is %s.\n", info.chip_name);
80 w25qxx_interface_debug_print("w25qxx: manufacturer is %s.\n", info.manufacturer_name);
81 w25qxx_interface_debug_print("w25qxx: interface is %s.\n", info.interface);
82 w25qxx_interface_debug_print("w25qxx: driver version is %d.%d.\n", info.driver_version / 1000, (info.driver_version % 1000) / 100);
83 w25qxx_interface_debug_print("w25qxx: min supply voltage is %0.1fV.\n", info.supply_voltage_min_v);
84 w25qxx_interface_debug_print("w25qxx: max supply voltage is %0.1fV.\n", info.supply_voltage_max_v);
85 w25qxx_interface_debug_print("w25qxx: max current is %0.2fmA.\n", info.max_current_ma);
86 w25qxx_interface_debug_print("w25qxx: max temperature is %0.1fC.\n", info.temperature_max);
87 w25qxx_interface_debug_print("w25qxx: min temperature is %0.1fC.\n", info.temperature_min);
88 }
89
90 /* set chip type */
91 res = w25qxx_set_type(&gs_handle, type);
92 if (res != 0)
93 {
94 w25qxx_interface_debug_print("w25qxx: set type failed.\n");
95
96 return 1;
97 }
98
99 /* set chip interface */
100 res = w25qxx_set_interface(&gs_handle, interface);
101 if (res != 0)
102 {
103 w25qxx_interface_debug_print("w25qxx: set interface failed.\n");
104
105 return 1;
106 }
107
108 /* set dual quad spi */
109 res = w25qxx_set_dual_quad_spi(&gs_handle, dual_quad_spi_enable);
110 if (res != 0)
111 {
112 w25qxx_interface_debug_print("w25qxx: set dual quad spi failed.\n");
113 (void)w25qxx_deinit(&gs_handle);
114
115 return 1;
116 }
117
118 /* chip init */
119 res = w25qxx_init(&gs_handle);
120 if (res != 0)
121 {
122 w25qxx_interface_debug_print("w25qxx: init failed.\n");
123
124 return 1;
125 }
126
127 /* start read test */
128 w25qxx_interface_debug_print("w25qxx: start read test.\n");
129
130 if (interface == W25QXX_INTERFACE_SPI)
131 {
132 uint32_t size;
133 uint32_t addr, step, j;
134
135 if (type == W25Q10)
136 {
137 size = 0x20000U;
138 }
139 else if (type == W25Q20)
140 {
141 size = 0x40000U;
142 }
143 else if (type == W25Q40)
144 {
145 size = 0x80000U;
146 }
147 else if (type == W25Q80)
148 {
149 size = 0x100000U;
150 }
151 else if (type == W25Q16)
152 {
153 size = 0x200000U;
154 }
155 else if (type == W25Q32)
156 {
157 size = 0x400000U;
158 }
159 else if (type == W25Q64)
160 {
161 size = 0x800000U;
162 }
163 else if (type == W25Q128)
164 {
165 size = 0x1000000U;
166 }
167 else if (type == W25Q256)
168 {
169 size = 0x2000000U;
170 }
171 else if (type == W25Q512)
172 {
173 size = 0x4000000U;
174 }
175 else if (type == W25Q01)
176 {
177 size = 0x8000000U;
178 }
179 else if (type == W25Q02)
180 {
181 size = 0x10000000U;
182 }
183 else
184 {
185 w25qxx_interface_debug_print("w25qxx: invalid type.\n");
186 (void)w25qxx_deinit(&gs_handle);
187
188 return 1;
189 }
190 step = size / 16;
191
192 /* w25qxx_write/w25qxx_read test */
193 w25qxx_interface_debug_print("w25qxx: w25qxx_write/w25qxx_read test.\n");
194
195 for (addr = 0; addr < size; addr += step)
196 {
197 for (j = 0; j < 600; j++)
198 {
199 gs_buffer_input[j] = rand() %256;
200 }
201 res = w25qxx_write(&gs_handle, addr, gs_buffer_input, 600);
202 if (res != 0)
203 {
204 w25qxx_interface_debug_print("w25qxx: write failed.\n");
205 (void)w25qxx_deinit(&gs_handle);
206
207 return 1;
208 }
209 res = w25qxx_read(&gs_handle, addr, gs_buffer_output, 600);
210 if (res != 0)
211 {
212 w25qxx_interface_debug_print("w25qxx: read failed.\n");
213 (void)w25qxx_deinit(&gs_handle);
214
215 return 1;
216 }
217 for (j = 0; j < 600; j++)
218 {
219 if (gs_buffer_input[j] != gs_buffer_output[j])
220 {
221 w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
222 (void)w25qxx_deinit(&gs_handle);
223
224 return 1;
225 }
226 }
227 w25qxx_interface_debug_print("w25qxx: 0x%08X/0x%08X successful.\n", addr, size);
228 }
229
230 /* w25qxx_sector_erase_4k test */
231 addr = (rand() % 10) * 4 * 1024;
232 w25qxx_interface_debug_print("w25qxx: w25qxx_sector_erase_4k test with address 0x%X.\n", addr);
233 res = w25qxx_sector_erase_4k(&gs_handle, addr);
234 if (res != 0)
235 {
236 w25qxx_interface_debug_print("w25qxx: sector erase 4k failed.\n");
237 (void)w25qxx_deinit(&gs_handle);
238
239 return 1;
240 }
241 for (j = 0; j < 256; j++)
242 {
243 gs_buffer_input[j] = rand() %256;
244 }
245
246 /* w25qxx_page_program */
247 res = w25qxx_page_program(&gs_handle, addr, gs_buffer_input, 256);
248 if (res != 0)
249 {
250 w25qxx_interface_debug_print("w25qxx: page program failed.\n");
251 (void)w25qxx_deinit(&gs_handle);
252
253 return 1;
254 }
255
256 /* w25qxx_only_spi_read */
257 res = w25qxx_only_spi_read(&gs_handle, addr, gs_buffer_output, 256);
258 if (res != 0)
259 {
260 w25qxx_interface_debug_print("w25qxx: only spi read failed.\n");
261 (void)w25qxx_deinit(&gs_handle);
262
263 return 1;
264 }
265 for (j = 0; j < 256; j++)
266 {
267 if (gs_buffer_input[j] != gs_buffer_output[j])
268 {
269 w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
270 (void)w25qxx_deinit(&gs_handle);
271
272 return 1;
273 }
274 }
275 w25qxx_interface_debug_print("w25qxx: only spi read test passed.\n");
276
277 /* w25qxx_fast_read */
278 res = w25qxx_fast_read(&gs_handle, addr, gs_buffer_output, 256);
279 if (res != 0)
280 {
281 w25qxx_interface_debug_print("w25qxx: fast read failed.\n");
282 (void)w25qxx_deinit(&gs_handle);
283
284 return 1;
285 }
286 for (j = 0; j < 256; j++)
287 {
288 if (gs_buffer_input[j] != gs_buffer_output[j])
289 {
290 w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
291 (void)w25qxx_deinit(&gs_handle);
292
293 return 1;
294 }
295 }
296 w25qxx_interface_debug_print("w25qxx: fast read test passed.\n");
297
298 /* w25qxx_block_erase_32k test */
299 addr = (rand() % 10) * 32 * 1024;
300 w25qxx_interface_debug_print("w25qxx: w25qxx_block_erase_32k test with address 0x%X.\n", addr);
301 res = w25qxx_block_erase_32k(&gs_handle, addr);
302 if (res != 0)
303 {
304 w25qxx_interface_debug_print("w25qxx: sector erase 32k failed.\n");
305 (void)w25qxx_deinit(&gs_handle);
306
307 return 1;
308 }
309 for (j = 0; j < 256; j++)
310 {
311 gs_buffer_input[j] = rand() %256;
312 }
313
314 /* w25qxx_page_program */
315 res = w25qxx_page_program(&gs_handle, addr, gs_buffer_input, 256);
316 if (res != 0)
317 {
318 w25qxx_interface_debug_print("w25qxx: page program failed.\n");
319 (void)w25qxx_deinit(&gs_handle);
320
321 return 1;
322 }
323
324 /* w25qxx_only_spi_read */
325 res = w25qxx_only_spi_read(&gs_handle, addr, gs_buffer_output, 256);
326 if (res != 0)
327 {
328 w25qxx_interface_debug_print("w25qxx: only spi read failed.\n");
329 (void)w25qxx_deinit(&gs_handle);
330
331 return 1;
332 }
333 for (j = 0; j < 256; j++)
334 {
335 if (gs_buffer_input[j] != gs_buffer_output[j])
336 {
337 w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
338 (void)w25qxx_deinit(&gs_handle);
339
340 return 1;
341 }
342 }
343 w25qxx_interface_debug_print("w25qxx: only spi read test passed.\n");
344
345 /* w25qxx_fast_read */
346 res = w25qxx_fast_read(&gs_handle, addr, gs_buffer_output, 256);
347 if (res != 0)
348 {
349 w25qxx_interface_debug_print("w25qxx: fast read failed.\n");
350 (void)w25qxx_deinit(&gs_handle);
351
352 return 1;
353 }
354 for (j = 0; j < 256; j++)
355 {
356 if (gs_buffer_input[j] != gs_buffer_output[j])
357 {
358 w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
359 (void)w25qxx_deinit(&gs_handle);
360
361 return 1;
362 }
363 }
364 w25qxx_interface_debug_print("w25qxx: fast read test passed.\n");
365
366 /* w25qxx_block_erase_64k test */
367 addr = (rand() % 10) * 64 * 1024;
368 w25qxx_interface_debug_print("w25qxx: w25qxx_block_erase_64k test with address 0x%X.\n", addr);
369 res = w25qxx_block_erase_64k(&gs_handle, addr);
370 if (res != 0)
371 {
372 w25qxx_interface_debug_print("w25qxx: sector erase 64k failed.\n");
373 (void)w25qxx_deinit(&gs_handle);
374
375 return 1;
376 }
377 for (j = 0; j < 256; j++)
378 {
379 gs_buffer_input[j] = rand() %256;
380 }
381
382 /* w25qxx_page_program */
383 res = w25qxx_page_program(&gs_handle, addr, gs_buffer_input, 256);
384 if (res != 0)
385 {
386 w25qxx_interface_debug_print("w25qxx: page program failed.\n");
387 (void)w25qxx_deinit(&gs_handle);
388
389 return 1;
390 }
391
392 /* w25qxx_only_spi_read */
393 res = w25qxx_only_spi_read(&gs_handle, addr, gs_buffer_output, 256);
394 if (res != 0)
395 {
396 w25qxx_interface_debug_print("w25qxx: only spi read failed.\n");
397 (void)w25qxx_deinit(&gs_handle);
398
399 return 1;
400 }
401 for (j = 0; j < 256; j++)
402 {
403 if (gs_buffer_input[j] != gs_buffer_output[j])
404 {
405 w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
406 (void)w25qxx_deinit(&gs_handle);
407
408 return 1;
409 }
410 }
411 w25qxx_interface_debug_print("w25qxx: only spi read test passed.\n");
412
413 /* w25qxx_fast_read */
414 res = w25qxx_fast_read(&gs_handle, addr, gs_buffer_output, 256);
415 if (res != 0)
416 {
417 w25qxx_interface_debug_print("w25qxx: fast read failed.\n");
418 (void)w25qxx_deinit(&gs_handle);
419
420 return 1;
421 }
422 for (j = 0; j < 256; j++)
423 {
424 if (gs_buffer_input[j] != gs_buffer_output[j])
425 {
426 w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
427 (void)w25qxx_deinit(&gs_handle);
428
429 return 1;
430 }
431 }
432 w25qxx_interface_debug_print("w25qxx: fast read test passed.\n");
433
434 /* get sfdp */
435 w25qxx_interface_debug_print("w25qxx: get sfdp.\n");
436 memset(gs_buffer_output, 0, sizeof(uint8_t) * 256);
437 res = w25qxx_get_sfdp(&gs_handle, (uint8_t *)gs_buffer_output);
438 if (res != 0)
439 {
440 w25qxx_interface_debug_print("w25qxx: get sfdp failed.\n");
441 (void)w25qxx_deinit(&gs_handle);
442
443 return 1;
444 }
445 for (j = 0; j < 256; j += 8)
446 {
447 w25qxx_interface_debug_print("w25qxx: sdfp[%d-%d] is 0x%02X 0x%02X 0x%02X 0x%02X 0x%02X 0x%02X 0x%02X 0x%02X.\n",
448 j , j + 7,
449 gs_buffer_output[j + 0], gs_buffer_output[j + 1], gs_buffer_output[j + 2],
450 gs_buffer_output[j + 3], gs_buffer_output[j + 4], gs_buffer_output[j + 5],
451 gs_buffer_output[j + 6], gs_buffer_output[j + 7]);
452 }
453
454 /* security register1 write and read test */
455 w25qxx_interface_debug_print("w25qxx: security register1 write and read test.\n");
456
457 /* security register1 write and read test */
458 res = w25qxx_erase_security_register(&gs_handle, W25QXX_SECURITY_REGISTER_1);
459 if (res != 0)
460 {
461 w25qxx_interface_debug_print("w25qxx: erase security register failed.\n");
462 (void)w25qxx_deinit(&gs_handle);
463
464 return 1;
465 }
466 for (j = 0; j < 256; j++)
467 {
468 gs_buffer_input[j] = rand() %256;
469 }
470 res = w25qxx_program_security_register(&gs_handle, W25QXX_SECURITY_REGISTER_1, gs_buffer_input);
471 if (res != 0)
472 {
473 w25qxx_interface_debug_print("w25qxx: program security register failed.\n");
474 (void)w25qxx_deinit(&gs_handle);
475
476 return 1;
477 }
478 res = w25qxx_read_security_register(&gs_handle, W25QXX_SECURITY_REGISTER_1, gs_buffer_output);
479 if (res != 0)
480 {
481 w25qxx_interface_debug_print("w25qxx: read security register failed.\n");
482 (void)w25qxx_deinit(&gs_handle);
483
484 return 1;
485 }
486 for (j = 0; j < 256; j++)
487 {
488 if (gs_buffer_input[j] != gs_buffer_output[j])
489 {
490 w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
491 (void)w25qxx_deinit(&gs_handle);
492
493 return 1;
494 }
495 }
496 w25qxx_interface_debug_print("w25qxx: security register1 check passed.\n");
497
498 /* security register2 write and read test */
499 w25qxx_interface_debug_print("w25qxx: security register2 write and read test.\n");
500
501 /* security register2 write and read test */
502 res = w25qxx_erase_security_register(&gs_handle, W25QXX_SECURITY_REGISTER_2);
503 if (res != 0)
504 {
505 w25qxx_interface_debug_print("w25qxx: erase security register failed.\n");
506 (void)w25qxx_deinit(&gs_handle);
507
508 return 1;
509 }
510 for (j = 0; j < 256; j++)
511 {
512 gs_buffer_input[j] = rand() %256;
513 }
514 res = w25qxx_program_security_register(&gs_handle, W25QXX_SECURITY_REGISTER_2, gs_buffer_input);
515 if (res != 0)
516 {
517 w25qxx_interface_debug_print("w25qxx: program security register failed.\n");
518 (void)w25qxx_deinit(&gs_handle);
519
520 return 1;
521 }
522 res = w25qxx_read_security_register(&gs_handle, W25QXX_SECURITY_REGISTER_2, gs_buffer_output);
523 if (res != 0)
524 {
525 w25qxx_interface_debug_print("w25qxx: read security register failed.\n");
526 (void)w25qxx_deinit(&gs_handle);
527
528 return 1;
529 }
530 for (j = 0; j < 256; j++)
531 {
532 if (gs_buffer_input[j] != gs_buffer_output[j])
533 {
534 w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
535 (void)w25qxx_deinit(&gs_handle);
536
537 return 1;
538 }
539 }
540 w25qxx_interface_debug_print("w25qxx: security register2 check passed.\n");
541
542 /* security register3 write and read test */
543 w25qxx_interface_debug_print("w25qxx: security register3 write and read test.\n");
544
545 /* security register3 write and read test */
546 res = w25qxx_erase_security_register(&gs_handle, W25QXX_SECURITY_REGISTER_3);
547 if (res != 0)
548 {
549 w25qxx_interface_debug_print("w25qxx: erase security register failed.\n");
550 (void)w25qxx_deinit(&gs_handle);
551
552 return 1;
553 }
554 for (j = 0; j < 256; j++)
555 {
556 gs_buffer_input[j] = rand() %256;
557 }
558 res = w25qxx_program_security_register(&gs_handle, W25QXX_SECURITY_REGISTER_3, gs_buffer_input);
559 if (res != 0)
560 {
561 w25qxx_interface_debug_print("w25qxx: program security register failed.\n");
562 (void)w25qxx_deinit(&gs_handle);
563
564 return 1;
565 }
566 res = w25qxx_read_security_register(&gs_handle, W25QXX_SECURITY_REGISTER_3, gs_buffer_output);
567 if (res != 0)
568 {
569 w25qxx_interface_debug_print("w25qxx: read security register failed.\n");
570 (void)w25qxx_deinit(&gs_handle);
571
572 return 1;
573 }
574 for (j = 0; j < 256; j++)
575 {
576 if (gs_buffer_input[j] != gs_buffer_output[j])
577 {
578 w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
579 (void)w25qxx_deinit(&gs_handle);
580
581 return 1;
582 }
583 }
584 w25qxx_interface_debug_print("w25qxx: security register3 check passed.\n");
585
586 #if (W25QXX_ENABLE_ERASE_READ_TEST == 1)
587 /* start chip erasing */
588 w25qxx_interface_debug_print("w25qxx: start chip erasing.\n");
589
590 /* chip erase */
591 w25qxx_interface_debug_print("w25qxx: w25qxx_chip_erase test.\n");
592 res = w25qxx_chip_erase(&gs_handle);
593 if (res != 0)
594 {
595 w25qxx_interface_debug_print("w25qxx: chip erase failed.\n");
596 (void)w25qxx_deinit(&gs_handle);
597
598 return 1;
599 }
600 w25qxx_interface_debug_print("w25qxx: chip erase successful.\n");
601 #endif
602
603 if (type >= W25Q256)
604 {
605 /* set address mode 4 byte */
606 w25qxx_interface_debug_print("w25qxx: set address mode 4 byte.\n");
607
608 /* set address mode 4 byte */
609 res = w25qxx_set_address_mode(&gs_handle, W25QXX_ADDRESS_MODE_4_BYTE);
610 if (res != 0)
611 {
612 w25qxx_interface_debug_print("w25qxx: set address mode failed.\n");
613 (void)w25qxx_deinit(&gs_handle);
614
615 return 1;
616 }
617
618 /* w25qxx_write/w25qxx_read test */
619 w25qxx_interface_debug_print("w25qxx: w25qxx_write/w25qxx_read test.\n");
620
621 for (addr = 0; addr < size; addr += step)
622 {
623 for (j = 0; j < 600; j++)
624 {
625 gs_buffer_input[j] = rand() %256;
626 }
627 res = w25qxx_write(&gs_handle, addr, gs_buffer_input, 600);
628 if (res != 0)
629 {
630 w25qxx_interface_debug_print("w25qxx: write failed.\n");
631 (void)w25qxx_deinit(&gs_handle);
632
633 return 1;
634 }
635 res = w25qxx_read(&gs_handle, addr, gs_buffer_output, 600);
636 if (res != 0)
637 {
638 w25qxx_interface_debug_print("w25qxx: read failed.\n");
639 (void)w25qxx_deinit(&gs_handle);
640
641 return 1;
642 }
643 for (j = 0; j < 600; j++)
644 {
645 if (gs_buffer_input[j] != gs_buffer_output[j])
646 {
647 w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
648 (void)w25qxx_deinit(&gs_handle);
649
650 return 1;
651 }
652 }
653 w25qxx_interface_debug_print("w25qxx: %d/%d successful.\n", addr, size);
654 }
655
656 /* w25qxx_sector_erase_4k test */
657 addr = (rand() % 10) * 4 * 1024;
658 w25qxx_interface_debug_print("w25qxx: w25qxx_sector_erase_4k test with address 0x%X.\n", addr);
659 res = w25qxx_sector_erase_4k(&gs_handle, addr);
660 if (res != 0)
661 {
662 w25qxx_interface_debug_print("w25qxx: sector erase 4k failed.\n");
663 (void)w25qxx_deinit(&gs_handle);
664
665 return 1;
666 }
667 for (j = 0; j < 256; j++)
668 {
669 gs_buffer_input[j] = rand() %256;
670 }
671
672 /* w25qxx_page_program */
673 res = w25qxx_page_program(&gs_handle, addr, gs_buffer_input, 256);
674 if (res != 0)
675 {
676 w25qxx_interface_debug_print("w25qxx: page program failed.\n");
677 (void)w25qxx_deinit(&gs_handle);
678
679 return 1;
680 }
681
682 /* w25qxx_only_spi_read */
683 res = w25qxx_only_spi_read(&gs_handle, addr, gs_buffer_output, 256);
684 if (res != 0)
685 {
686 w25qxx_interface_debug_print("w25qxx: only spi read failed.\n");
687 (void)w25qxx_deinit(&gs_handle);
688
689 return 1;
690 }
691 for (j = 0; j < 256; j++)
692 {
693 if (gs_buffer_input[j] != gs_buffer_output[j])
694 {
695 w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
696 (void)w25qxx_deinit(&gs_handle);
697
698 return 1;
699 }
700 }
701 w25qxx_interface_debug_print("w25qxx: only spi read test passed.\n");
702
703 /* w25qxx_fast_read */
704 res = w25qxx_fast_read(&gs_handle, addr, gs_buffer_output, 256);
705 if (res != 0)
706 {
707 w25qxx_interface_debug_print("w25qxx: fast read failed.\n");
708 (void)w25qxx_deinit(&gs_handle);
709
710 return 1;
711 }
712 for (j = 0; j < 256; j++)
713 {
714 if (gs_buffer_input[j] != gs_buffer_output[j])
715 {
716 w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
717 (void)w25qxx_deinit(&gs_handle);
718
719 return 1;
720 }
721 }
722 w25qxx_interface_debug_print("w25qxx: fast read test passed.\n");
723
724 /* w25qxx_block_erase_32k test */
725 addr = (rand() % 10) * 32 * 1024;
726 w25qxx_interface_debug_print("w25qxx: w25qxx_block_erase_32k test with address 0x%X.\n", addr);
727 res = w25qxx_block_erase_32k(&gs_handle, addr);
728 if (res != 0)
729 {
730 w25qxx_interface_debug_print("w25qxx: sector erase 32k failed.\n");
731 (void)w25qxx_deinit(&gs_handle);
732
733 return 1;
734 }
735 for (j = 0; j < 256; j++)
736 {
737 gs_buffer_input[j] = rand() %256;
738 }
739
740 /* w25qxx_page_program */
741 res = w25qxx_page_program(&gs_handle, addr, gs_buffer_input, 256);
742 if (res != 0)
743 {
744 w25qxx_interface_debug_print("w25qxx: page program failed.\n");
745 (void)w25qxx_deinit(&gs_handle);
746
747 return 1;
748 }
749
750 /* w25qxx_only_spi_read */
751 res = w25qxx_only_spi_read(&gs_handle, addr, gs_buffer_output, 256);
752 if (res != 0)
753 {
754 w25qxx_interface_debug_print("w25qxx: only spi read failed.\n");
755 (void)w25qxx_deinit(&gs_handle);
756
757 return 1;
758 }
759 for (j = 0; j < 256; j++)
760 {
761 if (gs_buffer_input[j] != gs_buffer_output[j])
762 {
763 w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
764 (void)w25qxx_deinit(&gs_handle);
765
766 return 1;
767 }
768 }
769 w25qxx_interface_debug_print("w25qxx: only spi read test passed.\n");
770
771 /* w25qxx_fast_read */
772 res = w25qxx_fast_read(&gs_handle, addr, gs_buffer_output, 256);
773 if (res != 0)
774 {
775 w25qxx_interface_debug_print("w25qxx: fast read failed.\n");
776 (void)w25qxx_deinit(&gs_handle);
777
778 return 1;
779 }
780 for (j = 0; j < 256; j++)
781 {
782 if (gs_buffer_input[j] != gs_buffer_output[j])
783 {
784 w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
785 (void)w25qxx_deinit(&gs_handle);
786
787 return 1;
788 }
789 }
790 w25qxx_interface_debug_print("w25qxx: fast read test passed.\n");
791
792 /* w25qxx_block_erase_64k test */
793 addr = (rand() % 10) * 64 * 1024;
794 w25qxx_interface_debug_print("w25qxx: w25qxx_block_erase_64k test with address 0x%X.\n", addr);
795 res = w25qxx_block_erase_64k(&gs_handle, addr);
796 if (res != 0)
797 {
798 w25qxx_interface_debug_print("w25qxx: sector erase 64k failed.\n");
799 (void)w25qxx_deinit(&gs_handle);
800
801 return 1;
802 }
803 for (j = 0; j < 256; j++)
804 {
805 gs_buffer_input[j] = rand() %256;
806 }
807
808 /* w25qxx_page_program */
809 res = w25qxx_page_program(&gs_handle, addr, gs_buffer_input, 256);
810 if (res != 0)
811 {
812 w25qxx_interface_debug_print("w25qxx: page program failed.\n");
813 (void)w25qxx_deinit(&gs_handle);
814
815 return 1;
816 }
817
818 /* w25qxx_only_spi_read */
819 res = w25qxx_only_spi_read(&gs_handle, addr, gs_buffer_output, 256);
820 if (res != 0)
821 {
822 w25qxx_interface_debug_print("w25qxx: only spi read failed.\n");
823 (void)w25qxx_deinit(&gs_handle);
824
825 return 1;
826 }
827 for (j = 0; j < 256; j++)
828 {
829 if (gs_buffer_input[j] != gs_buffer_output[j])
830 {
831 w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
832 (void)w25qxx_deinit(&gs_handle);
833
834 return 1;
835 }
836 }
837 w25qxx_interface_debug_print("w25qxx: only spi read test passed.\n");
838
839 /* w25qxx_fast_read */
840 res = w25qxx_fast_read(&gs_handle, addr, gs_buffer_output, 256);
841 if (res != 0)
842 {
843 w25qxx_interface_debug_print("w25qxx: fast read failed.\n");
844 (void)w25qxx_deinit(&gs_handle);
845
846 return 1;
847 }
848 for (j = 0; j < 256; j++)
849 {
850 if (gs_buffer_input[j] != gs_buffer_output[j])
851 {
852 w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
853 (void)w25qxx_deinit(&gs_handle);
854
855 return 1;
856 }
857 }
858 w25qxx_interface_debug_print("w25qxx: fast read test passed.\n");
859
860 /* get sfdp */
861 w25qxx_interface_debug_print("w25qxx: get sfdp.\n");
862 memset(gs_buffer_output, 0, sizeof(uint8_t) * 256);
863 res = w25qxx_get_sfdp(&gs_handle, (uint8_t *)gs_buffer_output);
864 if (res != 0)
865 {
866 w25qxx_interface_debug_print("w25qxx: get sfdp failed.\n");
867 (void)w25qxx_deinit(&gs_handle);
868
869 return 1;
870 }
871 for (j = 0; j < 256; j += 8)
872 {
873 w25qxx_interface_debug_print("w25qxx: sdfp[%d-%d] is 0x%02X 0x%02X 0x%02X 0x%02X 0x%02X 0x%02X 0x%02X 0x%02X.\n",
874 j , j + 7,
875 gs_buffer_output[j + 0], gs_buffer_output[j + 1], gs_buffer_output[j + 2],
876 gs_buffer_output[j + 3], gs_buffer_output[j + 4], gs_buffer_output[j + 5],
877 gs_buffer_output[j + 6], gs_buffer_output[j + 7]);
878 }
879
880 /* security register1 write and read test */
881 w25qxx_interface_debug_print("w25qxx: security register1 write and read test.\n");
882
883 /* security register1 write and read test */
884 res = w25qxx_erase_security_register(&gs_handle, W25QXX_SECURITY_REGISTER_1);
885 if (res != 0)
886 {
887 w25qxx_interface_debug_print("w25qxx: erase security register failed.\n");
888 (void)w25qxx_deinit(&gs_handle);
889
890 return 1;
891 }
892 for (j = 0; j < 256; j++)
893 {
894 gs_buffer_input[j] = rand() %256;
895 }
896 res = w25qxx_program_security_register(&gs_handle, W25QXX_SECURITY_REGISTER_1, gs_buffer_input);
897 if (res != 0)
898 {
899 w25qxx_interface_debug_print("w25qxx: program security register failed.\n");
900 (void)w25qxx_deinit(&gs_handle);
901
902 return 1;
903 }
904 res = w25qxx_read_security_register(&gs_handle, W25QXX_SECURITY_REGISTER_1, gs_buffer_output);
905 if (res != 0)
906 {
907 w25qxx_interface_debug_print("w25qxx: read security register failed.\n");
908 (void)w25qxx_deinit(&gs_handle);
909
910 return 1;
911 }
912 for (j = 0; j < 256; j++)
913 {
914 if (gs_buffer_input[j] != gs_buffer_output[j])
915 {
916 w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
917 (void)w25qxx_deinit(&gs_handle);
918
919 return 1;
920 }
921 }
922 w25qxx_interface_debug_print("w25qxx: security register1 check passed.\n");
923
924 /* security register2 write and read test */
925 w25qxx_interface_debug_print("w25qxx: security register2 write and read test.\n");
926
927 /* security register2 write and read test */
928 res = w25qxx_erase_security_register(&gs_handle, W25QXX_SECURITY_REGISTER_2);
929 if (res != 0)
930 {
931 w25qxx_interface_debug_print("w25qxx: erase security register failed.\n");
932 (void)w25qxx_deinit(&gs_handle);
933
934 return 1;
935 }
936 for (j = 0; j < 256; j++)
937 {
938 gs_buffer_input[j] = rand() %256;
939 }
940 res = w25qxx_program_security_register(&gs_handle, W25QXX_SECURITY_REGISTER_2, gs_buffer_input);
941 if (res != 0)
942 {
943 w25qxx_interface_debug_print("w25qxx: program security register failed.\n");
944 (void)w25qxx_deinit(&gs_handle);
945
946 return 1;
947 }
948 res = w25qxx_read_security_register(&gs_handle, W25QXX_SECURITY_REGISTER_2, gs_buffer_output);
949 if (res != 0)
950 {
951 w25qxx_interface_debug_print("w25qxx: read security register failed.\n");
952 (void)w25qxx_deinit(&gs_handle);
953
954 return 1;
955 }
956 for (j = 0; j < 256; j++)
957 {
958 if (gs_buffer_input[j] != gs_buffer_output[j])
959 {
960 w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
961 (void)w25qxx_deinit(&gs_handle);
962
963 return 1;
964 }
965 }
966 w25qxx_interface_debug_print("w25qxx: security register2 check passed.\n");
967
968 /* security register3 write and read test */
969 w25qxx_interface_debug_print("w25qxx: security register3 write and read test.\n");
970
971 /* security register3 write and read test */
972 res = w25qxx_erase_security_register(&gs_handle, W25QXX_SECURITY_REGISTER_3);
973 if (res != 0)
974 {
975 w25qxx_interface_debug_print("w25qxx: erase security register failed.\n");
976 (void)w25qxx_deinit(&gs_handle);
977
978 return 1;
979 }
980 for (j = 0; j < 256; j++)
981 {
982 gs_buffer_input[j] = rand() %256;
983 }
984 res = w25qxx_program_security_register(&gs_handle, W25QXX_SECURITY_REGISTER_3, gs_buffer_input);
985 if (res != 0)
986 {
987 w25qxx_interface_debug_print("w25qxx: program security register failed.\n");
988 (void)w25qxx_deinit(&gs_handle);
989
990 return 1;
991 }
992 res = w25qxx_read_security_register(&gs_handle, W25QXX_SECURITY_REGISTER_3, gs_buffer_output);
993 if (res != 0)
994 {
995 w25qxx_interface_debug_print("w25qxx: read security register failed.\n");
996 (void)w25qxx_deinit(&gs_handle);
997
998 return 1;
999 }
1000 for (j = 0; j < 256; j++)
1001 {
1002 if (gs_buffer_input[j] != gs_buffer_output[j])
1003 {
1004 w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
1005 (void)w25qxx_deinit(&gs_handle);
1006
1007 return 1;
1008 }
1009 }
1010 w25qxx_interface_debug_print("w25qxx: security register3 check passed.\n");
1011
1012 /* set address mode 3 byte */
1013 w25qxx_interface_debug_print("w25qxx: set address mode 3 byte.\n");
1014
1015 /* set address mode 3 byte */
1016 res = w25qxx_set_address_mode(&gs_handle, W25QXX_ADDRESS_MODE_3_BYTE);
1017 if (res != 0)
1018 {
1019 w25qxx_interface_debug_print("w25qxx: set address mode failed.\n");
1020 (void)w25qxx_deinit(&gs_handle);
1021
1022 return 1;
1023 }
1024 }
1025 }
1026 else
1027 {
1028 uint32_t size;
1029 uint32_t addr, step, j;
1030
1031 if (type == W25Q10)
1032 {
1033 size = 0x20000U;
1034 }
1035 else if (type == W25Q20)
1036 {
1037 size = 0x40000U;
1038 }
1039 else if (type == W25Q40)
1040 {
1041 size = 0x80000U;
1042 }
1043 else if (type == W25Q80)
1044 {
1045 size = 0x100000U;
1046 }
1047 else if (type == W25Q16)
1048 {
1049 size = 0x200000U;
1050 }
1051 else if (type == W25Q32)
1052 {
1053 size = 0x400000U;
1054 }
1055 else if (type == W25Q64)
1056 {
1057 size = 0x800000U;
1058 }
1059 else if (type == W25Q128)
1060 {
1061 size = 0x1000000U;
1062 }
1063 else if (type == W25Q256)
1064 {
1065 size = 0x2000000U;
1066 }
1067 else if (type == W25Q512)
1068 {
1069 size = 0x4000000U;
1070 }
1071 else if (type == W25Q01)
1072 {
1073 size = 0x8000000U;
1074 }
1075 else if (type == W25Q02)
1076 {
1077 size = 0x10000000U;
1078 }
1079 else
1080 {
1081 w25qxx_interface_debug_print("w25qxx: invalid type.\n");
1082 (void)w25qxx_deinit(&gs_handle);
1083
1084 return 1;
1085 }
1086 step = size / 16;
1087
1088 /* w25qxx_write/w25qxx_read test */
1089 w25qxx_interface_debug_print("w25qxx: w25qxx_write/w25qxx_read test.\n");
1090
1091 for (addr = 0; addr < size; addr += step)
1092 {
1093 for (j = 0; j < 600; j++)
1094 {
1095 gs_buffer_input[j] = rand() %256;
1096 }
1097 res = w25qxx_write(&gs_handle, addr, gs_buffer_input, 600);
1098 if (res != 0)
1099 {
1100 w25qxx_interface_debug_print("w25qxx: write failed.\n");
1101 (void)w25qxx_deinit(&gs_handle);
1102
1103 return 1;
1104 }
1105 res = w25qxx_read(&gs_handle, addr, gs_buffer_output, 600);
1106 if (res != 0)
1107 {
1108 w25qxx_interface_debug_print("w25qxx: read failed.\n");
1109 (void)w25qxx_deinit(&gs_handle);
1110
1111 return 1;
1112 }
1113 for (j = 0; j < 600; j++)
1114 {
1115 if (gs_buffer_input[j] != gs_buffer_output[j])
1116 {
1117 w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
1118 (void)w25qxx_deinit(&gs_handle);
1119
1120 return 1;
1121 }
1122 }
1123 w25qxx_interface_debug_print("w25qxx: 0x%08X/0x%08X successful.\n", addr, size);
1124 }
1125
1126 /* w25qxx_sector_erase_4k test */
1127 addr = (rand() % 10) * 4 * 1024;
1128 w25qxx_interface_debug_print("w25qxx: w25qxx_sector_erase_4k test with address 0x%X.\n", addr);
1129 res = w25qxx_sector_erase_4k(&gs_handle, addr);
1130 if (res != 0)
1131 {
1132 w25qxx_interface_debug_print("w25qxx: sector erase 4k failed.\n");
1133 (void)w25qxx_deinit(&gs_handle);
1134
1135 return 1;
1136 }
1137 for (j = 0; j < 256; j++)
1138 {
1139 gs_buffer_input[j] = rand() %256;
1140 }
1141
1142 /* w25qxx_page_program */
1143 res = w25qxx_page_program(&gs_handle, addr, gs_buffer_input, 256);
1144 if (res != 0)
1145 {
1146 w25qxx_interface_debug_print("w25qxx: page program failed.\n");
1147 (void)w25qxx_deinit(&gs_handle);
1148
1149 return 1;
1150 }
1151
1152 /* w25qxx_fast_read */
1153 res = w25qxx_fast_read(&gs_handle, addr, gs_buffer_output, 256);
1154 if (res != 0)
1155 {
1156 w25qxx_interface_debug_print("w25qxx: fast read failed.\n");
1157 (void)w25qxx_deinit(&gs_handle);
1158
1159 return 1;
1160 }
1161 for (j = 0; j < 256; j++)
1162 {
1163 if (gs_buffer_input[j] != gs_buffer_output[j])
1164 {
1165 w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
1166 (void)w25qxx_deinit(&gs_handle);
1167
1168 return 1;
1169 }
1170 }
1171 w25qxx_interface_debug_print("w25qxx: fast read test passed.\n");
1172
1173 /* w25qxx_block_erase_32k test */
1174 addr = (rand() % 10) * 32 * 1024;
1175 w25qxx_interface_debug_print("w25qxx: w25qxx_block_erase_32k test with address 0x%X.\n", addr);
1176 res = w25qxx_block_erase_32k(&gs_handle, addr);
1177 if (res != 0)
1178 {
1179 w25qxx_interface_debug_print("w25qxx: sector erase 32k failed.\n");
1180 (void)w25qxx_deinit(&gs_handle);
1181
1182 return 1;
1183 }
1184 for (j = 0; j < 256; j++)
1185 {
1186 gs_buffer_input[j] = rand() %256;
1187 }
1188
1189 /* w25qxx_page_program */
1190 res = w25qxx_page_program(&gs_handle, addr, gs_buffer_input, 256);
1191 if (res != 0)
1192 {
1193 w25qxx_interface_debug_print("w25qxx: page program failed.\n");
1194 (void)w25qxx_deinit(&gs_handle);
1195
1196 return 1;
1197 }
1198
1199 /* w25qxx_fast_read */
1200 res = w25qxx_fast_read(&gs_handle, addr, gs_buffer_output, 256);
1201 if (res != 0)
1202 {
1203 w25qxx_interface_debug_print("w25qxx: fast read failed.\n");
1204 (void)w25qxx_deinit(&gs_handle);
1205
1206 return 1;
1207 }
1208 for (j = 0; j < 256; j++)
1209 {
1210 if (gs_buffer_input[j] != gs_buffer_output[j])
1211 {
1212 w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
1213 (void)w25qxx_deinit(&gs_handle);
1214
1215 return 1;
1216 }
1217 }
1218 w25qxx_interface_debug_print("w25qxx: fast read test passed.\n");
1219
1220 /* w25qxx_block_erase_64k test */
1221 addr = (rand() % 10) * 64 * 1024;
1222 w25qxx_interface_debug_print("w25qxx: w25qxx_block_erase_64k test with address 0x%X.\n", addr);
1223 res = w25qxx_block_erase_64k(&gs_handle, addr);
1224 if (res != 0)
1225 {
1226 w25qxx_interface_debug_print("w25qxx: sector erase 64k failed.\n");
1227 (void)w25qxx_deinit(&gs_handle);
1228
1229 return 1;
1230 }
1231 for (j = 0; j < 256; j++)
1232 {
1233 gs_buffer_input[j] = rand() %256;
1234 }
1235
1236 /* w25qxx_page_program */
1237 res = w25qxx_page_program(&gs_handle, addr, gs_buffer_input, 256);
1238 if (res != 0)
1239 {
1240 w25qxx_interface_debug_print("w25qxx: page program failed.\n");
1241 (void)w25qxx_deinit(&gs_handle);
1242
1243 return 1;
1244 }
1245
1246 /* w25qxx_fast_read */
1247 res = w25qxx_fast_read(&gs_handle, addr, gs_buffer_output, 256);
1248 if (res != 0)
1249 {
1250 w25qxx_interface_debug_print("w25qxx: fast read failed.\n");
1251 (void)w25qxx_deinit(&gs_handle);
1252
1253 return 1;
1254 }
1255 for (j = 0; j < 256; j++)
1256 {
1257 if (gs_buffer_input[j] != gs_buffer_output[j])
1258 {
1259 w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
1260 (void)w25qxx_deinit(&gs_handle);
1261
1262 return 1;
1263 }
1264 }
1265 w25qxx_interface_debug_print("w25qxx: fast read test passed.\n");
1266
1267 #if (W25QXX_ENABLE_ERASE_READ_TEST == 1)
1268 /* start chip erasing */
1269 w25qxx_interface_debug_print("w25qxx: start chip erasing.\n");
1270
1271 /* chip erase */
1272 w25qxx_interface_debug_print("w25qxx: w25qxx_chip_erase test.\n");
1273 res = w25qxx_chip_erase(&gs_handle);
1274 if (res != 0)
1275 {
1276 w25qxx_interface_debug_print("w25qxx: chip erase failed.\n");
1277 (void)w25qxx_deinit(&gs_handle);
1278
1279 return 1;
1280 }
1281 w25qxx_interface_debug_print("w25qxx: chip erase successful.\n");
1282 #endif
1283
1284 if (type >= W25Q256)
1285 {
1286 /* set address mode 4 byte */
1287 w25qxx_interface_debug_print("w25qxx: set address mode 4 byte.\n");
1288
1289 /* set address mode 4 byte */
1290 res = w25qxx_set_address_mode(&gs_handle, W25QXX_ADDRESS_MODE_4_BYTE);
1291 if (res != 0)
1292 {
1293 w25qxx_interface_debug_print("w25qxx: set address mode failed.\n");
1294 (void)w25qxx_deinit(&gs_handle);
1295
1296 return 1;
1297 }
1298
1299 /* w25qxx_write/w25qxx_read test */
1300 w25qxx_interface_debug_print("w25qxx: w25qxx_write/w25qxx_read test.\n");
1301
1302 for (addr = 0; addr < size; addr += step)
1303 {
1304 for (j = 0; j < 600; j++)
1305 {
1306 gs_buffer_input[j] = rand() %256;
1307 }
1308 res = w25qxx_write(&gs_handle, addr, gs_buffer_input, 600);
1309 if (res != 0)
1310 {
1311 w25qxx_interface_debug_print("w25qxx: write failed.\n");
1312 (void)w25qxx_deinit(&gs_handle);
1313
1314 return 1;
1315 }
1316 res = w25qxx_read(&gs_handle, addr, gs_buffer_output, 600);
1317 if (res != 0)
1318 {
1319 w25qxx_interface_debug_print("w25qxx: read failed.\n");
1320 (void)w25qxx_deinit(&gs_handle);
1321
1322 return 1;
1323 }
1324 for (j = 0; j < 600; j++)
1325 {
1326 if (gs_buffer_input[j] != gs_buffer_output[j])
1327 {
1328 w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
1329 (void)w25qxx_deinit(&gs_handle);
1330
1331 return 1;
1332 }
1333 }
1334 w25qxx_interface_debug_print("w25qxx: 0x%08X/0x%08X successful.\n", addr, size);
1335 }
1336
1337 /* w25qxx_sector_erase_4k test */
1338 addr = (rand() % 10) * 4 * 1024;
1339 w25qxx_interface_debug_print("w25qxx: w25qxx_sector_erase_4k test with address 0x%X.\n", addr);
1340 res = w25qxx_sector_erase_4k(&gs_handle, addr);
1341 if (res != 0)
1342 {
1343 w25qxx_interface_debug_print("w25qxx: sector erase 4k failed.\n");
1344 (void)w25qxx_deinit(&gs_handle);
1345
1346 return 1;
1347 }
1348 for (j = 0; j < 256; j++)
1349 {
1350 gs_buffer_input[j] = rand() %256;
1351 }
1352
1353 /* w25qxx_page_program */
1354 res = w25qxx_page_program(&gs_handle, addr, gs_buffer_input, 256);
1355 if (res != 0)
1356 {
1357 w25qxx_interface_debug_print("w25qxx: page program failed.\n");
1358 (void)w25qxx_deinit(&gs_handle);
1359
1360 return 1;
1361 }
1362
1363 /* w25qxx_fast_read */
1364 res = w25qxx_fast_read(&gs_handle, addr, gs_buffer_output, 256);
1365 if (res != 0)
1366 {
1367 w25qxx_interface_debug_print("w25qxx: fast read failed.\n");
1368 (void)w25qxx_deinit(&gs_handle);
1369
1370 return 1;
1371 }
1372 for (j = 0; j < 256; j++)
1373 {
1374 if (gs_buffer_input[j] != gs_buffer_output[j])
1375 {
1376 w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
1377 (void)w25qxx_deinit(&gs_handle);
1378
1379 return 1;
1380 }
1381 }
1382 w25qxx_interface_debug_print("w25qxx: fast read test passed.\n");
1383
1384 /* w25qxx_block_erase_32k test */
1385 addr = (rand() % 10) * 32 * 1024;
1386 w25qxx_interface_debug_print("w25qxx: w25qxx_block_erase_32k test with address 0x%X.\n", addr);
1387 res = w25qxx_block_erase_32k(&gs_handle, addr);
1388 if (res != 0)
1389 {
1390 w25qxx_interface_debug_print("w25qxx: sector erase 32k failed.\n");
1391 (void)w25qxx_deinit(&gs_handle);
1392
1393 return 1;
1394 }
1395 for (j = 0; j < 256; j++)
1396 {
1397 gs_buffer_input[j] = rand() %256;
1398 }
1399
1400 /* w25qxx_page_program */
1401 res = w25qxx_page_program(&gs_handle, addr, gs_buffer_input, 256);
1402 if (res != 0)
1403 {
1404 w25qxx_interface_debug_print("w25qxx: page program failed.\n");
1405 (void)w25qxx_deinit(&gs_handle);
1406
1407 return 1;
1408 }
1409
1410 /* w25qxx_fast_read */
1411 res = w25qxx_fast_read(&gs_handle, addr, gs_buffer_output, 256);
1412 if (res != 0)
1413 {
1414 w25qxx_interface_debug_print("w25qxx: fast read failed.\n");
1415 (void)w25qxx_deinit(&gs_handle);
1416
1417 return 1;
1418 }
1419 for (j = 0; j < 256; j++)
1420 {
1421 if (gs_buffer_input[j] != gs_buffer_output[j])
1422 {
1423 w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
1424 (void)w25qxx_deinit(&gs_handle);
1425
1426 return 1;
1427 }
1428 }
1429 w25qxx_interface_debug_print("w25qxx: fast read test passed.\n");
1430
1431 /* w25qxx_block_erase_64k test */
1432 addr = (rand() % 10) * 64 * 1024;
1433 w25qxx_interface_debug_print("w25qxx: w25qxx_block_erase_64k test with address 0x%X.\n", addr);
1434 res = w25qxx_block_erase_64k(&gs_handle, addr);
1435 if (res != 0)
1436 {
1437 w25qxx_interface_debug_print("w25qxx: sector erase 64k failed.\n");
1438 (void)w25qxx_deinit(&gs_handle);
1439
1440 return 1;
1441 }
1442 for (j = 0; j < 256; j++)
1443 {
1444 gs_buffer_input[j] = rand() %256;
1445 }
1446
1447 /* w25qxx_page_program */
1448 res = w25qxx_page_program(&gs_handle, addr, gs_buffer_input, 256);
1449 if (res != 0)
1450 {
1451 w25qxx_interface_debug_print("w25qxx: page program failed.\n");
1452 (void)w25qxx_deinit(&gs_handle);
1453
1454 return 1;
1455 }
1456
1457 /* w25qxx_fast_read */
1458 res = w25qxx_fast_read(&gs_handle, addr, gs_buffer_output, 256);
1459 if (res != 0)
1460 {
1461 w25qxx_interface_debug_print("w25qxx: fast read failed.\n");
1462 (void)w25qxx_deinit(&gs_handle);
1463
1464 return 1;
1465 }
1466 for (j = 0; j < 256; j++)
1467 {
1468 if (gs_buffer_input[j] != gs_buffer_output[j])
1469 {
1470 w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
1471 (void)w25qxx_deinit(&gs_handle);
1472
1473 return 1;
1474 }
1475 }
1476 w25qxx_interface_debug_print("w25qxx: fast read test passed.\n");
1477
1478 /* set address mode 3 byte */
1479 w25qxx_interface_debug_print("w25qxx: set address mode 3 byte.\n");
1480
1481 /* set address mode 3 byte */
1482 res = w25qxx_set_address_mode(&gs_handle, W25QXX_ADDRESS_MODE_3_BYTE);
1483 if (res != 0)
1484 {
1485 w25qxx_interface_debug_print("w25qxx: set address mode failed.\n");
1486 (void)w25qxx_deinit(&gs_handle);
1487
1488 return 1;
1489 }
1490 }
1491
1492 if (dual_quad_spi_enable != 0)
1493 {
1494 /* enter to spi mode */
1495 w25qxx_interface_debug_print("w25qxx: enter to spi mode.\n");
1496
1497 /* exit qspi */
1498 res = w25qxx_exit_qspi_mode(&gs_handle);
1499 if (res != 0)
1500 {
1501 w25qxx_interface_debug_print("w25qxx: exit qspi mode failed.\n");
1502 (void)w25qxx_deinit(&gs_handle);
1503
1504 return 1;
1505 }
1506
1507 /* set chip interface spi */
1508 res = w25qxx_set_interface(&gs_handle, W25QXX_INTERFACE_SPI);
1509 if (res != 0)
1510 {
1511 w25qxx_interface_debug_print("w25qxx: set interface failed.\n");
1512
1513 return 1;
1514 }
1515
1516 /* random data */
1517 for (j = 0; j < 256; j++)
1518 {
1519 gs_buffer_input[j] = rand() %256;
1520 }
1521
1522 /* w25qxx_sector_erase_4k */
1523 res = w25qxx_sector_erase_4k(&gs_handle, 0x00000000);
1524 if (res != 0)
1525 {
1526 w25qxx_interface_debug_print("w25qxx: sector erase 4k failed.\n");
1527 (void)w25qxx_deinit(&gs_handle);
1528
1529 return 1;
1530 }
1531
1532 /* w25qxx_page_program */
1533 res = w25qxx_page_program(&gs_handle, 0x00000000, gs_buffer_input, 256);
1534 if (res != 0)
1535 {
1536 w25qxx_interface_debug_print("w25qxx: page program failed.\n");
1537 (void)w25qxx_deinit(&gs_handle);
1538
1539 return 1;
1540 }
1541
1542 /* fast read dual output */
1543 res = w25qxx_fast_read_dual_output(&gs_handle, 0x00000000, gs_buffer_output, 256);
1544 if (res != 0)
1545 {
1546 w25qxx_interface_debug_print("w25qxx: fast read dual output failed.\n");
1547 (void)w25qxx_deinit(&gs_handle);
1548
1549 return 1;
1550 }
1551 for (j = 0; j < 256; j++)
1552 {
1553 if (gs_buffer_input[j] != gs_buffer_output[j])
1554 {
1555 w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
1556 (void)w25qxx_deinit(&gs_handle);
1557
1558 return 1;
1559 }
1560 }
1561 w25qxx_interface_debug_print("w25qxx: fast_read_dual_output check passed.\n");
1562
1563 /* fast read quad output */
1564 res = w25qxx_fast_read_quad_output(&gs_handle, 0x00000000, gs_buffer_output, 256);
1565 if (res != 0)
1566 {
1567 w25qxx_interface_debug_print("w25qxx: fast read quad output failed.\n");
1568 (void)w25qxx_deinit(&gs_handle);
1569
1570 return 1;
1571 }
1572 for (j = 0; j < 256; j++)
1573 {
1574 if (gs_buffer_input[j] != gs_buffer_output[j])
1575 {
1576 w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
1577 (void)w25qxx_deinit(&gs_handle);
1578
1579 return 1;
1580 }
1581 }
1582 w25qxx_interface_debug_print("w25qxx: fast_read_quad_output check passed.\n");
1583
1584 /* fast read dual io */
1585 res = w25qxx_fast_read_dual_io(&gs_handle, 0x00000000, gs_buffer_output, 256);
1586 if (res != 0)
1587 {
1588 w25qxx_interface_debug_print("w25qxx: fast read dual io failed.\n");
1589 (void)w25qxx_deinit(&gs_handle);
1590
1591 return 1;
1592 }
1593 for (j = 0; j < 256; j++)
1594 {
1595 if (gs_buffer_input[j] != gs_buffer_output[j])
1596 {
1597 w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
1598 (void)w25qxx_deinit(&gs_handle);
1599
1600 return 1;
1601 }
1602 }
1603 w25qxx_interface_debug_print("w25qxx: w25qxx_fast_read_dual_io check passed.\n");
1604
1605 /* fast read quad io */
1606 res = w25qxx_fast_read_quad_io(&gs_handle, 0x00000000, gs_buffer_output, 256);
1607 if (res != 0)
1608 {
1609 w25qxx_interface_debug_print("w25qxx: fast read quad io failed.\n");
1610 (void)w25qxx_deinit(&gs_handle);
1611
1612 return 1;
1613 }
1614 for (j = 0; j < 256; j++)
1615 {
1616 if (gs_buffer_input[j] != gs_buffer_output[j])
1617 {
1618 w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
1619 (void)w25qxx_deinit(&gs_handle);
1620
1621 return 1;
1622 }
1623 }
1624 w25qxx_interface_debug_print("w25qxx: w25qxx_fast_read_quad_io check passed.\n");
1625
1626 /* word read quad io */
1627 res = w25qxx_word_read_quad_io(&gs_handle, 0x00000000, gs_buffer_output, 256);
1628 if (res != 0)
1629 {
1630 w25qxx_interface_debug_print("w25qxx: word read quad io failed.\n");
1631 (void)w25qxx_deinit(&gs_handle);
1632
1633 return 1;
1634 }
1635 for (j = 0; j < 256; j++)
1636 {
1637 if (gs_buffer_input[j] != gs_buffer_output[j])
1638 {
1639 w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
1640 (void)w25qxx_deinit(&gs_handle);
1641
1642 return 1;
1643 }
1644 }
1645 w25qxx_interface_debug_print("w25qxx: w25qxx_word_read_quad_io check passed.\n");
1646
1647 /* octal read quad io */
1648 res = w25qxx_octal_word_read_quad_io(&gs_handle, 0x00000000, gs_buffer_output, 256);
1649 if (res != 0)
1650 {
1651 w25qxx_interface_debug_print("w25qxx: octal read quad io failed.\n");
1652 (void)w25qxx_deinit(&gs_handle);
1653
1654 return 1;
1655 }
1656 for (j = 0; j < 256; j++)
1657 {
1658 if (gs_buffer_input[j] != gs_buffer_output[j])
1659 {
1660 w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
1661 (void)w25qxx_deinit(&gs_handle);
1662
1663 return 1;
1664 }
1665 }
1666 w25qxx_interface_debug_print("w25qxx: w25qxx_octal_word_read_quad_io check passed.\n");
1667
1668 /* random data */
1669 for (j = 0; j < 256; j++)
1670 {
1671 gs_buffer_input[j] = rand() %256;
1672 }
1673
1674 /* w25qxx_sector_erase_4k */
1675 res = w25qxx_sector_erase_4k(&gs_handle, 0x00000000);
1676 if (res != 0)
1677 {
1678 w25qxx_interface_debug_print("w25qxx: sector erase 4k failed.\n");
1679 (void)w25qxx_deinit(&gs_handle);
1680
1681 return 1;
1682 }
1683
1684 /* w25qxx_page_program_quad_input */
1685 res = w25qxx_page_program_quad_input(&gs_handle, 0x00000000, gs_buffer_input, 256);
1686 if (res != 0)
1687 {
1688 w25qxx_interface_debug_print("w25qxx: page program quad input failed.\n");
1689 (void)w25qxx_deinit(&gs_handle);
1690
1691 return 1;
1692 }
1693
1694 /* fast read */
1695 res = w25qxx_fast_read(&gs_handle, 0x00000000, gs_buffer_output, 256);
1696 if (res != 0)
1697 {
1698 w25qxx_interface_debug_print("w25qxx: fast read failed.\n");
1699 (void)w25qxx_deinit(&gs_handle);
1700
1701 return 1;
1702 }
1703 for (j = 0; j < 256; j++)
1704 {
1705 if (gs_buffer_input[j] != gs_buffer_output[j])
1706 {
1707 w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
1708 (void)w25qxx_deinit(&gs_handle);
1709
1710 return 1;
1711 }
1712 }
1713 w25qxx_interface_debug_print("w25qxx: w25qxx_page_program_quad_input check passed.\n");
1714
1715 if (type >= W25Q256)
1716 {
1717 /* set address mode 4 byte */
1718 w25qxx_interface_debug_print("w25qxx: set address mode 4 byte.\n");
1719
1720 /* set address mode 4 byte */
1721 res = w25qxx_set_address_mode(&gs_handle, W25QXX_ADDRESS_MODE_4_BYTE);
1722 if (res != 0)
1723 {
1724 w25qxx_interface_debug_print("w25qxx: set address mode failed.\n");
1725 (void)w25qxx_deinit(&gs_handle);
1726
1727 return 1;
1728 }
1729
1730 /* random data */
1731 for (j = 0; j < 256; j++)
1732 {
1733 gs_buffer_input[j] = rand() %256;
1734 }
1735
1736 /* w25qxx_sector_erase_4k */
1737 res = w25qxx_sector_erase_4k(&gs_handle, 0x00000000);
1738 if (res != 0)
1739 {
1740 w25qxx_interface_debug_print("w25qxx: sector erase 4k failed.\n");
1741 (void)w25qxx_deinit(&gs_handle);
1742
1743 return 1;
1744 }
1745
1746 /* w25qxx_page_program */
1747 res = w25qxx_page_program(&gs_handle, 0x00000000, gs_buffer_input, 256);
1748 if (res != 0)
1749 {
1750 w25qxx_interface_debug_print("w25qxx: page program failed.\n");
1751 (void)w25qxx_deinit(&gs_handle);
1752
1753 return 1;
1754 }
1755
1756 /* fast read dual output */
1757 res = w25qxx_fast_read_dual_output(&gs_handle, 0x00000000, gs_buffer_output, 256);
1758 if (res != 0)
1759 {
1760 w25qxx_interface_debug_print("w25qxx: fast read dual output failed.\n");
1761 (void)w25qxx_deinit(&gs_handle);
1762
1763 return 1;
1764 }
1765 for (j = 0; j < 256; j++)
1766 {
1767 if (gs_buffer_input[j] != gs_buffer_output[j])
1768 {
1769 w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
1770 (void)w25qxx_deinit(&gs_handle);
1771
1772 return 1;
1773 }
1774 }
1775 w25qxx_interface_debug_print("w25qxx: fast_read_dual_output check passed.\n");
1776
1777 /* fast read quad output */
1778 res = w25qxx_fast_read_quad_output(&gs_handle, 0x00000000, gs_buffer_output, 256);
1779 if (res != 0)
1780 {
1781 w25qxx_interface_debug_print("w25qxx: fast read quad output failed.\n");
1782 (void)w25qxx_deinit(&gs_handle);
1783
1784 return 1;
1785 }
1786 for (j = 0; j < 256; j++)
1787 {
1788 if (gs_buffer_input[j] != gs_buffer_output[j])
1789 {
1790 w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
1791 (void)w25qxx_deinit(&gs_handle);
1792
1793 return 1;
1794 }
1795 }
1796 w25qxx_interface_debug_print("w25qxx: fast_read_quad_output check passed.\n");
1797
1798 /* fast read dual io */
1799 res = w25qxx_fast_read_dual_io(&gs_handle, 0x00000000, gs_buffer_output, 256);
1800 if (res != 0)
1801 {
1802 w25qxx_interface_debug_print("w25qxx: fast read dual io failed.\n");
1803 (void)w25qxx_deinit(&gs_handle);
1804
1805 return 1;
1806 }
1807 for (j = 0; j < 256; j++)
1808 {
1809 if (gs_buffer_input[j] != gs_buffer_output[j])
1810 {
1811 w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
1812 (void)w25qxx_deinit(&gs_handle);
1813
1814 return 1;
1815 }
1816 }
1817 w25qxx_interface_debug_print("w25qxx: w25qxx_fast_read_dual_io check passed.\n");
1818
1819 /* fast read quad io */
1820 res = w25qxx_fast_read_quad_io(&gs_handle, 0x00000000, gs_buffer_output, 256);
1821 if (res != 0)
1822 {
1823 w25qxx_interface_debug_print("w25qxx: fast read quad io failed.\n");
1824 (void)w25qxx_deinit(&gs_handle);
1825
1826 return 1;
1827 }
1828 for (j = 0; j < 256; j++)
1829 {
1830 if (gs_buffer_input[j] != gs_buffer_output[j])
1831 {
1832 w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
1833 (void)w25qxx_deinit(&gs_handle);
1834
1835 return 1;
1836 }
1837 }
1838 w25qxx_interface_debug_print("w25qxx: w25qxx_fast_read_quad_io check passed.\n");
1839
1840 /* word read quad io */
1841 res = w25qxx_word_read_quad_io(&gs_handle, 0x00000000, gs_buffer_output, 256);
1842 if (res != 0)
1843 {
1844 w25qxx_interface_debug_print("w25qxx: word read quad io failed.\n");
1845 (void)w25qxx_deinit(&gs_handle);
1846
1847 return 1;
1848 }
1849 for (j = 0; j < 256; j++)
1850 {
1851 if (gs_buffer_input[j] != gs_buffer_output[j])
1852 {
1853 w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
1854 (void)w25qxx_deinit(&gs_handle);
1855
1856 return 1;
1857 }
1858 }
1859 w25qxx_interface_debug_print("w25qxx: w25qxx_word_read_quad_io check passed.\n");
1860
1861 /* octal read quad io */
1862 res = w25qxx_octal_word_read_quad_io(&gs_handle, 0x00000000, gs_buffer_output, 256);
1863 if (res != 0)
1864 {
1865 w25qxx_interface_debug_print("w25qxx: octal read quad io failed.\n");
1866 (void)w25qxx_deinit(&gs_handle);
1867
1868 return 1;
1869 }
1870 for (j = 0; j < 256; j++)
1871 {
1872 if (gs_buffer_input[j] != gs_buffer_output[j])
1873 {
1874 w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
1875 (void)w25qxx_deinit(&gs_handle);
1876
1877 return 1;
1878 }
1879 }
1880 w25qxx_interface_debug_print("w25qxx: w25qxx_octal_word_read_quad_io check passed.\n");
1881
1882 /* random data */
1883 for (j = 0; j < 256; j++)
1884 {
1885 gs_buffer_input[j] = rand() %256;
1886 }
1887
1888 /* w25qxx_sector_erase_4k */
1889 res = w25qxx_sector_erase_4k(&gs_handle, 0x00000000);
1890 if (res != 0)
1891 {
1892 w25qxx_interface_debug_print("w25qxx: sector erase 4k failed.\n");
1893 (void)w25qxx_deinit(&gs_handle);
1894
1895 return 1;
1896 }
1897
1898 /* w25qxx_page_program_quad_input */
1899 res = w25qxx_page_program_quad_input(&gs_handle, 0x00000000, gs_buffer_input, 256);
1900 if (res != 0)
1901 {
1902 w25qxx_interface_debug_print("w25qxx: page program quad input failed.\n");
1903 (void)w25qxx_deinit(&gs_handle);
1904
1905 return 1;
1906 }
1907
1908 /* fast read */
1909 res = w25qxx_fast_read(&gs_handle, 0x00000000, gs_buffer_output, 256);
1910 if (res != 0)
1911 {
1912 w25qxx_interface_debug_print("w25qxx: fast read failed.\n");
1913 (void)w25qxx_deinit(&gs_handle);
1914
1915 return 1;
1916 }
1917 for (j = 0; j < 256; j++)
1918 {
1919 if (gs_buffer_input[j] != gs_buffer_output[j])
1920 {
1921 w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
1922 (void)w25qxx_deinit(&gs_handle);
1923
1924 return 1;
1925 }
1926 }
1927 w25qxx_interface_debug_print("w25qxx: w25qxx_page_program_quad_input check passed.\n");
1928
1929 /* set address mode 3 byte */
1930 w25qxx_interface_debug_print("w25qxx: set address mode 3 byte.\n");
1931
1932 /* set address mode 3 byte */
1933 res = w25qxx_set_address_mode(&gs_handle, W25QXX_ADDRESS_MODE_3_BYTE);
1934 if (res != 0)
1935 {
1936 w25qxx_interface_debug_print("w25qxx: set address mode failed.\n");
1937 (void)w25qxx_deinit(&gs_handle);
1938
1939 return 1;
1940 }
1941 }
1942
1943 /* enter to qspi mode */
1944 w25qxx_interface_debug_print("w25qxx: enter to qspi mode.\n");
1945
1946 /* enter qspi */
1947 res = w25qxx_enter_qspi_mode(&gs_handle);
1948 if (res != 0)
1949 {
1950 w25qxx_interface_debug_print("w25qxx: enter qspi mode failed.\n");
1951 (void)w25qxx_deinit(&gs_handle);
1952
1953 return 1;
1954 }
1955
1956 /* set chip interface spi */
1957 res = w25qxx_set_interface(&gs_handle, W25QXX_INTERFACE_QSPI);
1958 if (res != 0)
1959 {
1960 w25qxx_interface_debug_print("w25qxx: set interface failed.\n");
1961
1962 return 1;
1963 }
1964 }
1965
1966 /* w25qxx_set_read_parameters test */
1967 w25qxx_interface_debug_print("w25qxx: w25qxx_set_read_parameters test.\n");
1968
1969 /* 8 dummy max 80MHz test */
1970 w25qxx_interface_debug_print("w25qxx: set 8 dummy max 80MHz test.\n");
1971
1972 res = w25qxx_set_read_parameters(&gs_handle, W25QXX_QSPI_READ_DUMMY_8_80MHZ, W25QXX_QSPI_READ_WRAP_LENGTH_8_BYTE);
1973 if (res != 0)
1974 {
1975 w25qxx_interface_debug_print("w25qxx: set read parameters.\n");
1976
1977 return 1;
1978 }
1979
1980 for (addr = 0; addr < size; addr += step)
1981 {
1982 for (j = 0; j < 600; j++)
1983 {
1984 gs_buffer_input[j] = rand() %256;
1985 }
1986 res = w25qxx_write(&gs_handle, addr, gs_buffer_input, 600);
1987 if (res != 0)
1988 {
1989 w25qxx_interface_debug_print("w25qxx: write failed.\n");
1990 (void)w25qxx_deinit(&gs_handle);
1991
1992 return 1;
1993 }
1994 res = w25qxx_read(&gs_handle, addr, gs_buffer_output, 600);
1995 if (res != 0)
1996 {
1997 w25qxx_interface_debug_print("w25qxx: read failed.\n");
1998 (void)w25qxx_deinit(&gs_handle);
1999
2000 return 1;
2001 }
2002 for (j = 0; j < 600; j++)
2003 {
2004 if (gs_buffer_input[j] != gs_buffer_output[j])
2005 {
2006 w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
2007 (void)w25qxx_deinit(&gs_handle);
2008
2009 return 1;
2010 }
2011 }
2012 w25qxx_interface_debug_print("w25qxx: 0x%08X/0x%08X successful.\n", addr, size);
2013 }
2014
2015 /* 6 dummy max 80MHz test */
2016 w25qxx_interface_debug_print("w25qxx: set 6 dummy max 80MHz test.\n");
2017
2018 res = w25qxx_set_read_parameters(&gs_handle, W25QXX_QSPI_READ_DUMMY_6_80MHZ, W25QXX_QSPI_READ_WRAP_LENGTH_8_BYTE);
2019 if (res != 0)
2020 {
2021 w25qxx_interface_debug_print("w25qxx: set read parameters.\n");
2022
2023 return 1;
2024 }
2025
2026 for (addr = 0; addr < size; addr += step)
2027 {
2028 for (j = 0; j < 600; j++)
2029 {
2030 gs_buffer_input[j] = rand() %256;
2031 }
2032 res = w25qxx_write(&gs_handle, addr, gs_buffer_input, 600);
2033 if (res != 0)
2034 {
2035 w25qxx_interface_debug_print("w25qxx: write failed.\n");
2036 (void)w25qxx_deinit(&gs_handle);
2037
2038 return 1;
2039 }
2040 res = w25qxx_read(&gs_handle, addr, gs_buffer_output, 600);
2041 if (res != 0)
2042 {
2043 w25qxx_interface_debug_print("w25qxx: read failed.\n");
2044 (void)w25qxx_deinit(&gs_handle);
2045
2046 return 1;
2047 }
2048 for (j = 0; j < 600; j++)
2049 {
2050 if (gs_buffer_input[j] != gs_buffer_output[j])
2051 {
2052 w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
2053 (void)w25qxx_deinit(&gs_handle);
2054
2055 return 1;
2056 }
2057 }
2058 w25qxx_interface_debug_print("w25qxx: 0x%08X/0x%08X successful.\n", addr, size);
2059 }
2060
2061 /* 4 dummy max 55MHz test */
2062 w25qxx_interface_debug_print("w25qxx: set 4 dummy max 55MHz test.\n");
2063
2064 res = w25qxx_set_read_parameters(&gs_handle, W25QXX_QSPI_READ_DUMMY_4_55MHZ, W25QXX_QSPI_READ_WRAP_LENGTH_8_BYTE);
2065 if (res != 0)
2066 {
2067 w25qxx_interface_debug_print("w25qxx: set read parameters.\n");
2068
2069 return 1;
2070 }
2071
2072 for (addr = 0; addr < size; addr += step)
2073 {
2074 for (j = 0; j < 600; j++)
2075 {
2076 gs_buffer_input[j] = rand() %256;
2077 }
2078 res = w25qxx_write(&gs_handle, addr, gs_buffer_input, 600);
2079 if (res != 0)
2080 {
2081 w25qxx_interface_debug_print("w25qxx: write failed.\n");
2082 (void)w25qxx_deinit(&gs_handle);
2083
2084 return 1;
2085 }
2086 res = w25qxx_read(&gs_handle, addr, gs_buffer_output, 600);
2087 if (res != 0)
2088 {
2089 w25qxx_interface_debug_print("w25qxx: read failed.\n");
2090 (void)w25qxx_deinit(&gs_handle);
2091
2092 return 1;
2093 }
2094 for (j = 0; j < 600; j++)
2095 {
2096 if (gs_buffer_input[j] != gs_buffer_output[j])
2097 {
2098 w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
2099 (void)w25qxx_deinit(&gs_handle);
2100
2101 return 1;
2102 }
2103 }
2104 w25qxx_interface_debug_print("w25qxx: 0x%08X/0x%08X successful.\n", addr, size);
2105 }
2106
2107 /* 2 dummy max 33MHz test */
2108 w25qxx_interface_debug_print("w25qxx: set 2 dummy max 33MHz test.\n");
2109
2110 res = w25qxx_set_read_parameters(&gs_handle, W25QXX_QSPI_READ_DUMMY_2_33MHZ, W25QXX_QSPI_READ_WRAP_LENGTH_8_BYTE);
2111 if (res != 0)
2112 {
2113 w25qxx_interface_debug_print("w25qxx: set read parameters.\n");
2114
2115 return 1;
2116 }
2117
2118 for (addr = 0; addr < size; addr += step)
2119 {
2120 for (j = 0; j < 600; j++)
2121 {
2122 gs_buffer_input[j] = rand() %256;
2123 }
2124 res = w25qxx_write(&gs_handle, addr, gs_buffer_input, 600);
2125 if (res != 0)
2126 {
2127 w25qxx_interface_debug_print("w25qxx: write failed.\n");
2128 (void)w25qxx_deinit(&gs_handle);
2129
2130 return 1;
2131 }
2132 res = w25qxx_read(&gs_handle, addr, gs_buffer_output, 600);
2133 if (res != 0)
2134 {
2135 w25qxx_interface_debug_print("w25qxx: read failed.\n");
2136 (void)w25qxx_deinit(&gs_handle);
2137
2138 return 1;
2139 }
2140 for (j = 0; j < 600; j++)
2141 {
2142 if (gs_buffer_input[j] != gs_buffer_output[j])
2143 {
2144 w25qxx_interface_debug_print("w25qxx: write read check failed.\n");
2145 (void)w25qxx_deinit(&gs_handle);
2146
2147 return 1;
2148 }
2149 }
2150 w25qxx_interface_debug_print("w25qxx: 0x%08X/0x%08X successful.\n", addr, size);
2151 }
2152 }
2153
2154 /* finish read test */
2155 w25qxx_interface_debug_print("w25qxx: finish read test.\n");
2156 (void)w25qxx_deinit(&gs_handle);
2157
2158 return 0;
2159}
driver_w25qxx_read_test.h
driver w25qxx read test header file
w25qxx_page_program_quad_input
uint8_t w25qxx_page_program_quad_input(w25qxx_handle_t *handle, uint32_t addr, uint8_t *data, uint16_t len)
quad page program with quad input
Definition driver_w25qxx.c:4920
w25qxx_get_sfdp
uint8_t w25qxx_get_sfdp(w25qxx_handle_t *handle, uint8_t sfdp[256])
get the sfdp
Definition driver_w25qxx.c:2880
w25qxx_read_security_register
uint8_t w25qxx_read_security_register(w25qxx_handle_t *handle, w25qxx_security_register_t num, uint8_t data[256])
read the security register
Definition driver_w25qxx.c:3344
w25qxx_program_security_register
uint8_t w25qxx_program_security_register(w25qxx_handle_t *handle, w25qxx_security_register_t num, uint8_t data[256])
program the security register
Definition driver_w25qxx.c:3147
w25qxx_exit_qspi_mode
uint8_t w25qxx_exit_qspi_mode(w25qxx_handle_t *handle)
exit the qspi mode
Definition driver_w25qxx.c:2572
w25qxx_fast_read_dual_output
uint8_t w25qxx_fast_read_dual_output(w25qxx_handle_t *handle, uint32_t addr, uint8_t *data, uint32_t len)
read with dual output in the fast mode
Definition driver_w25qxx.c:3858
w25qxx_octal_word_read_quad_io
uint8_t w25qxx_octal_word_read_quad_io(w25qxx_handle_t *handle, uint32_t addr, uint8_t *data, uint32_t len)
octal word read with quad io
Definition driver_w25qxx.c:4459
w25qxx_set_read_parameters
uint8_t w25qxx_set_read_parameters(w25qxx_handle_t *handle, w25qxx_qspi_read_dummy_t dummy, w25qxx_qspi_read_wrap_length_t length)
set the read parameters
Definition driver_w25qxx.c:2427
w25qxx_enter_qspi_mode
uint8_t w25qxx_enter_qspi_mode(w25qxx_handle_t *handle)
enter the qspi mode
Definition driver_w25qxx.c:2494
w25qxx_fast_read_quad_io
uint8_t w25qxx_fast_read_quad_io(w25qxx_handle_t *handle, uint32_t addr, uint8_t *data, uint32_t len)
read with quad io in the fast mode
Definition driver_w25qxx.c:4184
w25qxx_fast_read_dual_io
uint8_t w25qxx_fast_read_dual_io(w25qxx_handle_t *handle, uint32_t addr, uint8_t *data, uint32_t len)
read with dual io in the fast mode
Definition driver_w25qxx.c:4076
w25qxx_word_read_quad_io
uint8_t w25qxx_word_read_quad_io(w25qxx_handle_t *handle, uint32_t addr, uint8_t *data, uint32_t len)
word read with quad io
Definition driver_w25qxx.c:4350
w25qxx_erase_security_register
uint8_t w25qxx_erase_security_register(w25qxx_handle_t *handle, w25qxx_security_register_t num)
erase the security register
Definition driver_w25qxx.c:2952
w25qxx_fast_read_quad_output
uint8_t w25qxx_fast_read_quad_output(w25qxx_handle_t *handle, uint32_t addr, uint8_t *data, uint32_t len)
read with quad output in the fast mode
Definition driver_w25qxx.c:3967
W25QXX_QSPI_READ_WRAP_LENGTH_8_BYTE
@ W25QXX_QSPI_READ_WRAP_LENGTH_8_BYTE
Definition driver_w25qxx.h:186
W25QXX_QSPI_READ_DUMMY_4_55MHZ
@ W25QXX_QSPI_READ_DUMMY_4_55MHZ
Definition driver_w25qxx.h:176
W25QXX_QSPI_READ_DUMMY_6_80MHZ
@ W25QXX_QSPI_READ_DUMMY_6_80MHZ
Definition driver_w25qxx.h:177
W25QXX_QSPI_READ_DUMMY_2_33MHZ
@ W25QXX_QSPI_READ_DUMMY_2_33MHZ
Definition driver_w25qxx.h:175
W25QXX_QSPI_READ_DUMMY_8_80MHZ
@ W25QXX_QSPI_READ_DUMMY_8_80MHZ
Definition driver_w25qxx.h:178
W25QXX_SECURITY_REGISTER_2
@ W25QXX_SECURITY_REGISTER_2
Definition driver_w25qxx.h:199
W25QXX_SECURITY_REGISTER_3
@ W25QXX_SECURITY_REGISTER_3
Definition driver_w25qxx.h:200
W25QXX_SECURITY_REGISTER_1
@ W25QXX_SECURITY_REGISTER_1
Definition driver_w25qxx.h:198
w25qxx_chip_erase
uint8_t w25qxx_chip_erase(w25qxx_handle_t *handle)
erase the chip
Definition driver_w25qxx.c:1459
w25qxx_only_spi_read
uint8_t w25qxx_only_spi_read(w25qxx_handle_t *handle, uint32_t addr, uint8_t *data, uint32_t len)
read only in the spi interface
Definition driver_w25qxx.c:3465
w25qxx_block_erase_32k
uint8_t w25qxx_block_erase_32k(w25qxx_handle_t *handle, uint32_t addr)
erase the 32k block
Definition driver_w25qxx.c:5419
w25qxx_set_interface
uint8_t w25qxx_set_interface(w25qxx_handle_t *handle, w25qxx_interface_t interface)
set the chip interface
Definition driver_w25qxx.c:259
w25qxx_handle_t
struct w25qxx_handle_s w25qxx_handle_t
w25qxx handle structure definition
w25qxx_info_t
struct w25qxx_info_s w25qxx_info_t
w25qxx information structure definition
w25qxx_page_program
uint8_t w25qxx_page_program(w25qxx_handle_t *handle, uint32_t addr, uint8_t *data, uint16_t len)
page program
Definition driver_w25qxx.c:4569
w25qxx_set_dual_quad_spi
uint8_t w25qxx_set_dual_quad_spi(w25qxx_handle_t *handle, w25qxx_bool_t enable)
enable or disable the dual quad spi
Definition driver_w25qxx.c:175
w25qxx_type_t
w25qxx_type_t
w25qxx type enumeration definition
Definition driver_w25qxx.h:119
w25qxx_init
uint8_t w25qxx_init(w25qxx_handle_t *handle)
initialize the chip
Definition driver_w25qxx.c:6819
w25qxx_info
uint8_t w25qxx_info(w25qxx_info_t *info)
get chip's information
Definition driver_w25qxx.c:8566
w25qxx_sector_erase_4k
uint8_t w25qxx_sector_erase_4k(w25qxx_handle_t *handle, uint32_t addr)
erase the 4k sector
Definition driver_w25qxx.c:5080
w25qxx_deinit
uint8_t w25qxx_deinit(w25qxx_handle_t *handle)
close the chip
Definition driver_w25qxx.c:7195
w25qxx_set_type
uint8_t w25qxx_set_type(w25qxx_handle_t *handle, w25qxx_type_t type)
set the chip type
Definition driver_w25qxx.c:217
w25qxx_write
uint8_t w25qxx_write(w25qxx_handle_t *handle, uint32_t addr, uint8_t *data, uint32_t len)
write data
Definition driver_w25qxx.c:8415
w25qxx_fast_read
uint8_t w25qxx_fast_read(w25qxx_handle_t *handle, uint32_t addr, uint8_t *data, uint32_t len)
read in the fast mode
Definition driver_w25qxx.c:3634
w25qxx_interface_t
w25qxx_interface_t
w25qxx interface enumeration definition
Definition driver_w25qxx.h:138
w25qxx_set_address_mode
uint8_t w25qxx_set_address_mode(w25qxx_handle_t *handle, w25qxx_address_mode_t mode)
set the chip address mode
Definition driver_w25qxx.c:304
w25qxx_read
uint8_t w25qxx_read(w25qxx_handle_t *handle, uint32_t addr, uint8_t *data, uint32_t len)
read data
Definition driver_w25qxx.c:7289
w25qxx_block_erase_64k
uint8_t w25qxx_block_erase_64k(w25qxx_handle_t *handle, uint32_t addr)
erase the 64k block
Definition driver_w25qxx.c:5758
w25qxx_bool_t
w25qxx_bool_t
w25qxx bool enumeration definition
Definition driver_w25qxx.h:147
W25Q80
@ W25Q80
Definition driver_w25qxx.h:123
W25Q01
@ W25Q01
Definition driver_w25qxx.h:130
W25Q64
@ W25Q64
Definition driver_w25qxx.h:126
W25Q10
@ W25Q10
Definition driver_w25qxx.h:120
W25Q32
@ W25Q32
Definition driver_w25qxx.h:125
W25Q02
@ W25Q02
Definition driver_w25qxx.h:131
W25Q512
@ W25Q512
Definition driver_w25qxx.h:129
W25Q20
@ W25Q20
Definition driver_w25qxx.h:121
W25Q16
@ W25Q16
Definition driver_w25qxx.h:124
W25Q128
@ W25Q128
Definition driver_w25qxx.h:127
W25Q40
@ W25Q40
Definition driver_w25qxx.h:122
W25Q256
@ W25Q256
Definition driver_w25qxx.h:128
W25QXX_ADDRESS_MODE_3_BYTE
@ W25QXX_ADDRESS_MODE_3_BYTE
Definition driver_w25qxx.h:157
W25QXX_ADDRESS_MODE_4_BYTE
@ W25QXX_ADDRESS_MODE_4_BYTE
Definition driver_w25qxx.h:158
W25QXX_INTERFACE_QSPI
@ W25QXX_INTERFACE_QSPI
Definition driver_w25qxx.h:140
W25QXX_INTERFACE_SPI
@ W25QXX_INTERFACE_SPI
Definition driver_w25qxx.h:139
w25qxx_interface_spi_qspi_deinit
uint8_t w25qxx_interface_spi_qspi_deinit(void)
interface spi qspi bus deinit
Definition driver_w25qxx_interface_template.c:58
w25qxx_interface_spi_qspi_init
uint8_t w25qxx_interface_spi_qspi_init(void)
interface spi qspi bus init
Definition driver_w25qxx_interface_template.c:46
w25qxx_interface_delay_us
void w25qxx_interface_delay_us(uint32_t us)
interface delay us
Definition driver_w25qxx_interface_template.c:108
w25qxx_interface_spi_qspi_write_read
uint8_t w25qxx_interface_spi_qspi_write_read(uint8_t instruction, uint8_t instruction_line, uint32_t address, uint8_t address_line, uint8_t address_len, uint32_t alternate, uint8_t alternate_line, uint8_t alternate_len, uint8_t dummy, uint8_t *in_buf, uint32_t in_len, uint8_t *out_buf, uint32_t out_len, uint8_t data_line)
interface spi qspi bus write read
Definition driver_w25qxx_interface_template.c:84
w25qxx_interface_debug_print
void w25qxx_interface_debug_print(const char *const fmt,...)
interface print format data
Definition driver_w25qxx_interface_template.c:118
w25qxx_interface_delay_ms
void w25qxx_interface_delay_ms(uint32_t ms)
interface delay ms
Definition driver_w25qxx_interface_template.c:98
DRIVER_W25QXX_LINK_DELAY_MS
#define DRIVER_W25QXX_LINK_DELAY_MS(HANDLE, FUC)
link delay_ms function
Definition driver_w25qxx.h:359
DRIVER_W25QXX_LINK_INIT
#define DRIVER_W25QXX_LINK_INIT(HANDLE, STRUCTURE)
initialize w25qxx_handle_t structure
Definition driver_w25qxx.h:327
DRIVER_W25QXX_LINK_SPI_QSPI_INIT
#define DRIVER_W25QXX_LINK_SPI_QSPI_INIT(HANDLE, FUC)
link spi_qspi_init function
Definition driver_w25qxx.h:335
DRIVER_W25QXX_LINK_DEBUG_PRINT
#define DRIVER_W25QXX_LINK_DEBUG_PRINT(HANDLE, FUC)
link debug_print function
Definition driver_w25qxx.h:375
DRIVER_W25QXX_LINK_SPI_QSPI_WRITE_READ
#define DRIVER_W25QXX_LINK_SPI_QSPI_WRITE_READ(HANDLE, FUC)
link spi_qspi_write_read function
Definition driver_w25qxx.h:351
DRIVER_W25QXX_LINK_SPI_QSPI_DEINIT
#define DRIVER_W25QXX_LINK_SPI_QSPI_DEINIT(HANDLE, FUC)
link spi_qspi_deinit function
Definition driver_w25qxx.h:343
DRIVER_W25QXX_LINK_DELAY_US
#define DRIVER_W25QXX_LINK_DELAY_US(HANDLE, FUC)
link delay_us function
Definition driver_w25qxx.h:367
w25qxx_read_test
uint8_t w25qxx_read_test(w25qxx_type_t type, w25qxx_interface_t interface, w25qxx_bool_t dual_quad_spi_enable)
read test
Definition driver_w25qxx_read_test.c:54
w25qxx_info_s::temperature_max
float temperature_max
Definition driver_w25qxx.h:306
w25qxx_info_s::supply_voltage_max_v
float supply_voltage_max_v
Definition driver_w25qxx.h:303
w25qxx_info_s::driver_version
uint32_t driver_version
Definition driver_w25qxx.h:307
w25qxx_info_s::interface
char interface[16]
Definition driver_w25qxx.h:301
w25qxx_info_s::temperature_min
float temperature_min
Definition driver_w25qxx.h:305
w25qxx_info_s::max_current_ma
float max_current_ma
Definition driver_w25qxx.h:304
w25qxx_info_s::manufacturer_name
char manufacturer_name[32]
Definition driver_w25qxx.h:300
w25qxx_info_s::supply_voltage_min_v
float supply_voltage_min_v
Definition driver_w25qxx.h:302
w25qxx_info_s::chip_name
char chip_name[32]
Definition driver_w25qxx.h:299